diff --git a/data/chips/STM32H503CB.json b/data/chips/STM32H503CB.json index 3c90283..6ddba5f 100644 --- a/data/chips/STM32H503CB.json +++ b/data/chips/STM32H503CB.json @@ -175,6 +175,11 @@ { "name": "COMP1", "address": 1073758208, + "registers": { + "kind": "comp", + "version": "h5", + "block": "COMP" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H503EB.json b/data/chips/STM32H503EB.json index de10ca6..ecc94ed 100644 --- a/data/chips/STM32H503EB.json +++ b/data/chips/STM32H503EB.json @@ -139,6 +139,11 @@ { "name": "COMP1", "address": 1073758208, + "registers": { + "kind": "comp", + "version": "h5", + "block": "COMP" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H503KB.json b/data/chips/STM32H503KB.json index ab27d61..e9db936 100644 --- a/data/chips/STM32H503KB.json +++ b/data/chips/STM32H503KB.json @@ -171,6 +171,11 @@ { "name": "COMP1", "address": 1073758208, + "registers": { + "kind": "comp", + "version": "h5", + "block": "COMP" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H503RB.json b/data/chips/STM32H503RB.json index 415f988..84264b5 100644 --- a/data/chips/STM32H503RB.json +++ b/data/chips/STM32H503RB.json @@ -211,6 +211,11 @@ { "name": "COMP1", "address": 1073758208, + "registers": { + "kind": "comp", + "version": "h5", + "block": "COMP" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H742AG.json b/data/chips/STM32H742AG.json index 91d9eb4..82c60e4 100644 --- a/data/chips/STM32H742AG.json +++ b/data/chips/STM32H742AG.json @@ -835,6 +835,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -867,6 +872,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H742AI.json b/data/chips/STM32H742AI.json index 7b90583..17d8d64 100644 --- a/data/chips/STM32H742AI.json +++ b/data/chips/STM32H742AI.json @@ -846,6 +846,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -878,6 +883,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H742BG.json b/data/chips/STM32H742BG.json index 8cc576d..4287bd0 100644 --- a/data/chips/STM32H742BG.json +++ b/data/chips/STM32H742BG.json @@ -835,6 +835,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -867,6 +872,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H742BI.json b/data/chips/STM32H742BI.json index 10734ba..ab17755 100644 --- a/data/chips/STM32H742BI.json +++ b/data/chips/STM32H742BI.json @@ -846,6 +846,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -878,6 +883,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H742IG.json b/data/chips/STM32H742IG.json index 6938b5b..7b84c3d 100644 --- a/data/chips/STM32H742IG.json +++ b/data/chips/STM32H742IG.json @@ -839,6 +839,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -871,6 +876,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H742II.json b/data/chips/STM32H742II.json index 3d4d7e3..801e416 100644 --- a/data/chips/STM32H742II.json +++ b/data/chips/STM32H742II.json @@ -850,6 +850,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -882,6 +887,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H742VG.json b/data/chips/STM32H742VG.json index d6dbc58..90d17b5 100644 --- a/data/chips/STM32H742VG.json +++ b/data/chips/STM32H742VG.json @@ -739,6 +739,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -771,6 +776,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H742VI.json b/data/chips/STM32H742VI.json index 4e6ddae..d90a664 100644 --- a/data/chips/STM32H742VI.json +++ b/data/chips/STM32H742VI.json @@ -750,6 +750,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -782,6 +787,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H742XG.json b/data/chips/STM32H742XG.json index 3cfa002..1d6912a 100644 --- a/data/chips/STM32H742XG.json +++ b/data/chips/STM32H742XG.json @@ -899,6 +899,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -931,6 +936,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H742XI.json b/data/chips/STM32H742XI.json index ea88621..157f031 100644 --- a/data/chips/STM32H742XI.json +++ b/data/chips/STM32H742XI.json @@ -910,6 +910,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -942,6 +947,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H742ZG.json b/data/chips/STM32H742ZG.json index 52a6794..f85793a 100644 --- a/data/chips/STM32H742ZG.json +++ b/data/chips/STM32H742ZG.json @@ -807,6 +807,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -839,6 +844,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H742ZI.json b/data/chips/STM32H742ZI.json index a9c7e56..baf8be5 100644 --- a/data/chips/STM32H742ZI.json +++ b/data/chips/STM32H742ZI.json @@ -818,6 +818,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -850,6 +855,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H743AG.json b/data/chips/STM32H743AG.json index 1821177..ef84519 100644 --- a/data/chips/STM32H743AG.json +++ b/data/chips/STM32H743AG.json @@ -877,6 +877,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -909,6 +914,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H743AI.json b/data/chips/STM32H743AI.json index 5e89a3a..d126c65 100644 --- a/data/chips/STM32H743AI.json +++ b/data/chips/STM32H743AI.json @@ -888,6 +888,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -920,6 +925,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H743BG.json b/data/chips/STM32H743BG.json index 9c99f77..59e9206 100644 --- a/data/chips/STM32H743BG.json +++ b/data/chips/STM32H743BG.json @@ -877,6 +877,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -909,6 +914,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H743BI.json b/data/chips/STM32H743BI.json index eabc904..134f59a 100644 --- a/data/chips/STM32H743BI.json +++ b/data/chips/STM32H743BI.json @@ -888,6 +888,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -920,6 +925,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H743IG.json b/data/chips/STM32H743IG.json index 63c1189..a92ca35 100644 --- a/data/chips/STM32H743IG.json +++ b/data/chips/STM32H743IG.json @@ -881,6 +881,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -913,6 +918,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H743II.json b/data/chips/STM32H743II.json index 82aa028..2bf53a9 100644 --- a/data/chips/STM32H743II.json +++ b/data/chips/STM32H743II.json @@ -892,6 +892,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -924,6 +929,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H743VG.json b/data/chips/STM32H743VG.json index 4885c22..33fa627 100644 --- a/data/chips/STM32H743VG.json +++ b/data/chips/STM32H743VG.json @@ -781,6 +781,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -813,6 +818,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H743VI.json b/data/chips/STM32H743VI.json index ff67e75..ca2dac4 100644 --- a/data/chips/STM32H743VI.json +++ b/data/chips/STM32H743VI.json @@ -792,6 +792,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -824,6 +829,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H743XG.json b/data/chips/STM32H743XG.json index 385dea2..c818848 100644 --- a/data/chips/STM32H743XG.json +++ b/data/chips/STM32H743XG.json @@ -941,6 +941,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -973,6 +978,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H743XI.json b/data/chips/STM32H743XI.json index dc27610..082acb2 100644 --- a/data/chips/STM32H743XI.json +++ b/data/chips/STM32H743XI.json @@ -952,6 +952,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -984,6 +989,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H743ZG.json b/data/chips/STM32H743ZG.json index a7ea107..642ad02 100644 --- a/data/chips/STM32H743ZG.json +++ b/data/chips/STM32H743ZG.json @@ -849,6 +849,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -881,6 +886,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H743ZI.json b/data/chips/STM32H743ZI.json index 35d84b6..499b13e 100644 --- a/data/chips/STM32H743ZI.json +++ b/data/chips/STM32H743ZI.json @@ -860,6 +860,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -892,6 +897,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H745BG.json b/data/chips/STM32H745BG.json index 8be1b79..18aa8ae 100644 --- a/data/chips/STM32H745BG.json +++ b/data/chips/STM32H745BG.json @@ -859,6 +859,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -891,6 +896,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -10667,6 +10677,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -10699,6 +10714,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H745BI.json b/data/chips/STM32H745BI.json index c2defe2..0431226 100644 --- a/data/chips/STM32H745BI.json +++ b/data/chips/STM32H745BI.json @@ -870,6 +870,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -902,6 +907,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -10678,6 +10688,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -10710,6 +10725,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H745IG.json b/data/chips/STM32H745IG.json index 784432b..b8fd67a 100644 --- a/data/chips/STM32H745IG.json +++ b/data/chips/STM32H745IG.json @@ -927,6 +927,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -959,6 +964,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -10477,6 +10487,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -10509,6 +10524,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H745II.json b/data/chips/STM32H745II.json index 6beb85b..389b52b 100644 --- a/data/chips/STM32H745II.json +++ b/data/chips/STM32H745II.json @@ -938,6 +938,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -970,6 +975,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -10488,6 +10498,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -10520,6 +10535,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H745XG.json b/data/chips/STM32H745XG.json index ef70f4c..25c4b82 100644 --- a/data/chips/STM32H745XG.json +++ b/data/chips/STM32H745XG.json @@ -923,6 +923,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -955,6 +960,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -10900,6 +10910,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -10932,6 +10947,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H745XI.json b/data/chips/STM32H745XI.json index 7175177..cfd1401 100644 --- a/data/chips/STM32H745XI.json +++ b/data/chips/STM32H745XI.json @@ -934,6 +934,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -966,6 +971,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -10911,6 +10921,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -10943,6 +10958,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H745ZG.json b/data/chips/STM32H745ZG.json index 24ee17c..1014ac5 100644 --- a/data/chips/STM32H745ZG.json +++ b/data/chips/STM32H745ZG.json @@ -799,6 +799,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -831,6 +836,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -9542,6 +9552,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -9574,6 +9589,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H745ZI.json b/data/chips/STM32H745ZI.json index d8e07d2..56ac5cc 100644 --- a/data/chips/STM32H745ZI.json +++ b/data/chips/STM32H745ZI.json @@ -810,6 +810,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -842,6 +847,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -9553,6 +9563,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -9585,6 +9600,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H747AG.json b/data/chips/STM32H747AG.json index a9ffaf8..84d864e 100644 --- a/data/chips/STM32H747AG.json +++ b/data/chips/STM32H747AG.json @@ -837,6 +837,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -869,6 +874,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -9799,6 +9809,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -9831,6 +9846,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H747AI.json b/data/chips/STM32H747AI.json index aa4b6ea..34d5e9c 100644 --- a/data/chips/STM32H747AI.json +++ b/data/chips/STM32H747AI.json @@ -848,6 +848,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -880,6 +885,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -9810,6 +9820,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -9842,6 +9857,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H747BG.json b/data/chips/STM32H747BG.json index 8c0960b..7d38907 100644 --- a/data/chips/STM32H747BG.json +++ b/data/chips/STM32H747BG.json @@ -865,6 +865,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -897,6 +902,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -10502,6 +10512,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -10534,6 +10549,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H747BI.json b/data/chips/STM32H747BI.json index bd7a346..d902630 100644 --- a/data/chips/STM32H747BI.json +++ b/data/chips/STM32H747BI.json @@ -876,6 +876,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -908,6 +913,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -10513,6 +10523,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -10545,6 +10560,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H747IG.json b/data/chips/STM32H747IG.json index cc4c5e8..10ab6b4 100644 --- a/data/chips/STM32H747IG.json +++ b/data/chips/STM32H747IG.json @@ -837,6 +837,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -869,6 +874,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -9799,6 +9809,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -9831,6 +9846,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H747II.json b/data/chips/STM32H747II.json index b51bb1f..62b5390 100644 --- a/data/chips/STM32H747II.json +++ b/data/chips/STM32H747II.json @@ -848,6 +848,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -880,6 +885,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -9810,6 +9820,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -9842,6 +9857,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H747XG.json b/data/chips/STM32H747XG.json index 37c4483..39de366 100644 --- a/data/chips/STM32H747XG.json +++ b/data/chips/STM32H747XG.json @@ -929,6 +929,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -961,6 +966,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -10910,6 +10920,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -10942,6 +10957,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H747XI.json b/data/chips/STM32H747XI.json index 4ae3dc4..f461de6 100644 --- a/data/chips/STM32H747XI.json +++ b/data/chips/STM32H747XI.json @@ -940,6 +940,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -972,6 +977,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -10921,6 +10931,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -10953,6 +10968,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H747ZI.json b/data/chips/STM32H747ZI.json index 6a0d865..15aaf34 100644 --- a/data/chips/STM32H747ZI.json +++ b/data/chips/STM32H747ZI.json @@ -816,6 +816,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -848,6 +853,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -9235,6 +9245,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -9267,6 +9282,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H750IB.json b/data/chips/STM32H750IB.json index 88d5d1f..85c4156 100644 --- a/data/chips/STM32H750IB.json +++ b/data/chips/STM32H750IB.json @@ -869,6 +869,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -901,6 +906,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H750VB.json b/data/chips/STM32H750VB.json index c7e2ef4..ce20efb 100644 --- a/data/chips/STM32H750VB.json +++ b/data/chips/STM32H750VB.json @@ -765,6 +765,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -797,6 +802,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H750XB.json b/data/chips/STM32H750XB.json index c189c9c..8dea6e8 100644 --- a/data/chips/STM32H750XB.json +++ b/data/chips/STM32H750XB.json @@ -929,6 +929,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -961,6 +966,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H750ZB.json b/data/chips/STM32H750ZB.json index 9f89ee8..fcc9d45 100644 --- a/data/chips/STM32H750ZB.json +++ b/data/chips/STM32H750ZB.json @@ -825,6 +825,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -857,6 +862,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H753AI.json b/data/chips/STM32H753AI.json index 60af719..c157f40 100644 --- a/data/chips/STM32H753AI.json +++ b/data/chips/STM32H753AI.json @@ -894,6 +894,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -926,6 +931,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H753BI.json b/data/chips/STM32H753BI.json index 0d72511..52ca90d 100644 --- a/data/chips/STM32H753BI.json +++ b/data/chips/STM32H753BI.json @@ -894,6 +894,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -926,6 +931,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H753II.json b/data/chips/STM32H753II.json index a1c577a..ea5174f 100644 --- a/data/chips/STM32H753II.json +++ b/data/chips/STM32H753II.json @@ -898,6 +898,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -930,6 +935,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H753VI.json b/data/chips/STM32H753VI.json index 8dd98a4..e2b3b82 100644 --- a/data/chips/STM32H753VI.json +++ b/data/chips/STM32H753VI.json @@ -798,6 +798,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -830,6 +835,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H753XI.json b/data/chips/STM32H753XI.json index 088c77e..b901f5a 100644 --- a/data/chips/STM32H753XI.json +++ b/data/chips/STM32H753XI.json @@ -958,6 +958,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -990,6 +995,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H753ZI.json b/data/chips/STM32H753ZI.json index 883834d..ba74305 100644 --- a/data/chips/STM32H753ZI.json +++ b/data/chips/STM32H753ZI.json @@ -866,6 +866,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -898,6 +903,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H755BI.json b/data/chips/STM32H755BI.json index 2743bfe..43dac0d 100644 --- a/data/chips/STM32H755BI.json +++ b/data/chips/STM32H755BI.json @@ -876,6 +876,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -908,6 +913,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -10761,6 +10771,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -10793,6 +10808,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H755II.json b/data/chips/STM32H755II.json index 9b3a1e5..2a66389 100644 --- a/data/chips/STM32H755II.json +++ b/data/chips/STM32H755II.json @@ -944,6 +944,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -976,6 +981,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -10571,6 +10581,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -10603,6 +10618,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H755XI.json b/data/chips/STM32H755XI.json index 3b2e44f..7c9b548 100644 --- a/data/chips/STM32H755XI.json +++ b/data/chips/STM32H755XI.json @@ -940,6 +940,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -972,6 +977,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -10994,6 +11004,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -11026,6 +11041,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H755ZI.json b/data/chips/STM32H755ZI.json index e36fa63..6b4307d 100644 --- a/data/chips/STM32H755ZI.json +++ b/data/chips/STM32H755ZI.json @@ -816,6 +816,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -848,6 +853,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -9636,6 +9646,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -9668,6 +9683,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H757AI.json b/data/chips/STM32H757AI.json index 30123ad..a2d1a90 100644 --- a/data/chips/STM32H757AI.json +++ b/data/chips/STM32H757AI.json @@ -854,6 +854,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -886,6 +891,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -9893,6 +9903,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -9925,6 +9940,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H757BI.json b/data/chips/STM32H757BI.json index 8505a8f..5042d0c 100644 --- a/data/chips/STM32H757BI.json +++ b/data/chips/STM32H757BI.json @@ -882,6 +882,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -914,6 +919,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -10596,6 +10606,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -10628,6 +10643,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H757II.json b/data/chips/STM32H757II.json index 29324e0..3d0430c 100644 --- a/data/chips/STM32H757II.json +++ b/data/chips/STM32H757II.json @@ -854,6 +854,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -886,6 +891,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -9893,6 +9903,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -9925,6 +9940,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H757XI.json b/data/chips/STM32H757XI.json index e0db0b6..7aba8c1 100644 --- a/data/chips/STM32H757XI.json +++ b/data/chips/STM32H757XI.json @@ -946,6 +946,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -978,6 +983,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -11004,6 +11014,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -11036,6 +11051,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H757ZI.json b/data/chips/STM32H757ZI.json index 6592b3c..d91dd85 100644 --- a/data/chips/STM32H757ZI.json +++ b/data/chips/STM32H757ZI.json @@ -822,6 +822,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -854,6 +859,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", @@ -9318,6 +9328,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -9350,6 +9365,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_b", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7A3AG.json b/data/chips/STM32H7A3AG.json index a24ef30..8c79e08 100644 --- a/data/chips/STM32H7A3AG.json +++ b/data/chips/STM32H7A3AG.json @@ -742,6 +742,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -774,6 +779,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7A3AI.json b/data/chips/STM32H7A3AI.json index ba08fa0..49c6682 100644 --- a/data/chips/STM32H7A3AI.json +++ b/data/chips/STM32H7A3AI.json @@ -753,6 +753,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -785,6 +790,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7A3IG.json b/data/chips/STM32H7A3IG.json index 578c27e..0fb324b 100644 --- a/data/chips/STM32H7A3IG.json +++ b/data/chips/STM32H7A3IG.json @@ -754,6 +754,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -786,6 +791,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7A3II.json b/data/chips/STM32H7A3II.json index ea3f74f..d6b777d 100644 --- a/data/chips/STM32H7A3II.json +++ b/data/chips/STM32H7A3II.json @@ -765,6 +765,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -797,6 +802,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7A3LG.json b/data/chips/STM32H7A3LG.json index b91f936..0d018a5 100644 --- a/data/chips/STM32H7A3LG.json +++ b/data/chips/STM32H7A3LG.json @@ -736,6 +736,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -768,6 +773,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7A3LI.json b/data/chips/STM32H7A3LI.json index 0775217..1407754 100644 --- a/data/chips/STM32H7A3LI.json +++ b/data/chips/STM32H7A3LI.json @@ -753,6 +753,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -785,6 +790,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7A3NG.json b/data/chips/STM32H7A3NG.json index f064dea..e9b295f 100644 --- a/data/chips/STM32H7A3NG.json +++ b/data/chips/STM32H7A3NG.json @@ -698,6 +698,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -730,6 +735,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7A3NI.json b/data/chips/STM32H7A3NI.json index 16ece5a..1feab0d 100644 --- a/data/chips/STM32H7A3NI.json +++ b/data/chips/STM32H7A3NI.json @@ -709,6 +709,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -741,6 +746,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7A3QI.json b/data/chips/STM32H7A3QI.json index db4ffb8..2b009ea 100644 --- a/data/chips/STM32H7A3QI.json +++ b/data/chips/STM32H7A3QI.json @@ -713,6 +713,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -745,6 +750,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7A3RG.json b/data/chips/STM32H7A3RG.json index ec3bf7c..a96cf55 100644 --- a/data/chips/STM32H7A3RG.json +++ b/data/chips/STM32H7A3RG.json @@ -694,6 +694,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", diff --git a/data/chips/STM32H7A3RI.json b/data/chips/STM32H7A3RI.json index fca5ece..6dc5224 100644 --- a/data/chips/STM32H7A3RI.json +++ b/data/chips/STM32H7A3RI.json @@ -705,6 +705,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", diff --git a/data/chips/STM32H7A3VG.json b/data/chips/STM32H7A3VG.json index 6b3d600..67eeb45 100644 --- a/data/chips/STM32H7A3VG.json +++ b/data/chips/STM32H7A3VG.json @@ -686,6 +686,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -718,6 +723,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7A3VI.json b/data/chips/STM32H7A3VI.json index 57d4aa3..3767038 100644 --- a/data/chips/STM32H7A3VI.json +++ b/data/chips/STM32H7A3VI.json @@ -697,6 +697,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -729,6 +734,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7A3ZG.json b/data/chips/STM32H7A3ZG.json index f8fad01..7d30ba2 100644 --- a/data/chips/STM32H7A3ZG.json +++ b/data/chips/STM32H7A3ZG.json @@ -702,6 +702,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -734,6 +739,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7A3ZI.json b/data/chips/STM32H7A3ZI.json index 14039de..9e1c972 100644 --- a/data/chips/STM32H7A3ZI.json +++ b/data/chips/STM32H7A3ZI.json @@ -713,6 +713,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -745,6 +750,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7B0AB.json b/data/chips/STM32H7B0AB.json index 19e54d2..0e25e3a 100644 --- a/data/chips/STM32H7B0AB.json +++ b/data/chips/STM32H7B0AB.json @@ -748,6 +748,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -780,6 +785,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7B0IB.json b/data/chips/STM32H7B0IB.json index bc797ff..f2f5226 100644 --- a/data/chips/STM32H7B0IB.json +++ b/data/chips/STM32H7B0IB.json @@ -752,6 +752,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -784,6 +789,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7B0RB.json b/data/chips/STM32H7B0RB.json index c0e5a3a..06b6b81 100644 --- a/data/chips/STM32H7B0RB.json +++ b/data/chips/STM32H7B0RB.json @@ -700,6 +700,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", diff --git a/data/chips/STM32H7B0VB.json b/data/chips/STM32H7B0VB.json index e8bdcf3..f3d0fe2 100644 --- a/data/chips/STM32H7B0VB.json +++ b/data/chips/STM32H7B0VB.json @@ -680,6 +680,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -712,6 +717,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7B0ZB.json b/data/chips/STM32H7B0ZB.json index 07aeed0..f7e9973 100644 --- a/data/chips/STM32H7B0ZB.json +++ b/data/chips/STM32H7B0ZB.json @@ -704,6 +704,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -736,6 +741,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7B3AI.json b/data/chips/STM32H7B3AI.json index 82228ca..a8a0cf0 100644 --- a/data/chips/STM32H7B3AI.json +++ b/data/chips/STM32H7B3AI.json @@ -765,6 +765,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -797,6 +802,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7B3II.json b/data/chips/STM32H7B3II.json index fe90aa3..940ed79 100644 --- a/data/chips/STM32H7B3II.json +++ b/data/chips/STM32H7B3II.json @@ -777,6 +777,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -809,6 +814,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7B3LI.json b/data/chips/STM32H7B3LI.json index 6557ac1..f8e57ed 100644 --- a/data/chips/STM32H7B3LI.json +++ b/data/chips/STM32H7B3LI.json @@ -765,6 +765,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -797,6 +802,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7B3NI.json b/data/chips/STM32H7B3NI.json index 76ba4df..2eeb42e 100644 --- a/data/chips/STM32H7B3NI.json +++ b/data/chips/STM32H7B3NI.json @@ -721,6 +721,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -753,6 +758,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7B3QI.json b/data/chips/STM32H7B3QI.json index ef060c8..88c228f 100644 --- a/data/chips/STM32H7B3QI.json +++ b/data/chips/STM32H7B3QI.json @@ -725,6 +725,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -757,6 +762,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7B3RI.json b/data/chips/STM32H7B3RI.json index 645fbe4..0be619c 100644 --- a/data/chips/STM32H7B3RI.json +++ b/data/chips/STM32H7B3RI.json @@ -717,6 +717,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", diff --git a/data/chips/STM32H7B3VI.json b/data/chips/STM32H7B3VI.json index eb53252..e68ad22 100644 --- a/data/chips/STM32H7B3VI.json +++ b/data/chips/STM32H7B3VI.json @@ -709,6 +709,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -741,6 +746,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/chips/STM32H7B3ZI.json b/data/chips/STM32H7B3ZI.json index f37312e..2e24089 100644 --- a/data/chips/STM32H7B3ZI.json +++ b/data/chips/STM32H7B3ZI.json @@ -725,6 +725,11 @@ { "name": "COMP1", "address": 1476409356, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PB0", @@ -757,6 +762,11 @@ { "name": "COMP2", "address": 1476409360, + "registers": { + "kind": "comp", + "version": "h7_a", + "block": "COMP" + }, "pins": [ { "pin": "PE10", diff --git a/data/registers/comp_h5.json b/data/registers/comp_h5.json new file mode 100644 index 0000000..871f826 --- /dev/null +++ b/data/registers/comp_h5.json @@ -0,0 +1,293 @@ +{ + "block/COMP": { + "description": "Comparator.", + "items": [ + { + "name": "SR", + "description": "Comparator status register.", + "byte_offset": 0, + "fieldset": "SR" + }, + { + "name": "ICFR", + "description": "Comparator interrupt clear flag register.", + "byte_offset": 4, + "fieldset": "ICFR" + }, + { + "name": "CFGR1", + "description": "Comparator configuration register 1.", + "byte_offset": 12, + "fieldset": "CFGR1" + }, + { + "name": "CFGR2", + "description": "Comparator configuration register 2.", + "byte_offset": 16, + "fieldset": "CFGR2" + } + ] + }, + "fieldset/CFGR1": { + "description": "Comparator configuration register 1.", + "fields": [ + { + "name": "EN", + "description": "COMP Channel1 enable This bit is set and cleared by software (only if LOCK not set). It enables the COMP-Channel1.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "BRGEN", + "description": "Scaler bridge enable This bit is set and cleared by software (only if LOCK not set). This bit enables the bridge of the scaler. If SCALEN is set and BRGEN is reset, all four scaler outputs provide the same level V<sub>REF_COMP</sub> (similar to V<sub>REFINT</sub>). If SCALEN and BRGEN are set, the four scaler outputs provide V<sub>REF_COMP</sub>, 3/4-V<sub>REF_COMP</sub>, 1/2-V<sub>REF_COMP</sub> and 1/4-V<sub>REF_COMP</sub> levels, respectively.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "SCALEN", + "description": "Voltage scaler enable This bit is set and cleared by software (only if LOCK not set). This bit enables the V<sub>REFINT</sub> scaler for the COMP channels.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "POLARITY", + "description": "COMP channel1 polarity selection This bit is set and cleared by software (only if LOCK not set). It inverts COMP channel1 polarity.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "ITEN", + "description": "COMP channel1 interrupt enable This bit is set and cleared by software (only if LOCK not set). This bit enable the interrupt generation of the COMP channel1.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "HYST", + "description": "COMP channel1 hysteresis selection These bits are set and cleared by software (only if LOCK not set). They select the hysteresis voltage of the COMP channel1.", + "bit_offset": 8, + "bit_size": 2, + "enum": "HYST" + }, + { + "name": "PWRMODE", + "description": "Power mode of the COMP channel1 These bits are set and cleared by software (only if LOCK not set). They control the power/speed of the COMP channel1.", + "bit_offset": 12, + "bit_size": 2, + "enum": "PWRMODE" + }, + { + "name": "INMSEL", + "description": "COMP channel1 inverting input selection These bits are set and cleared by software (only if LOCK not set). They select which input is connected to the input minus of the COMP channel. Note: See Table-146: COMP1 inverting input assignment for more details.", + "bit_offset": 16, + "bit_size": 4, + "enum": "INMSEL" + }, + { + "name": "INPSEL1", + "description": "COMP noninverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of COMP channel. Note: See Table-145: COMP1 noninverting input assignment for more details.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "INPSEL2", + "description": "COMP noninverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of the COMP channel. See Table-145: COMP1 noninverting input assignment for more details.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "BLANKING", + "description": "COMP Channel1 blanking source selection Bits of this field are set and cleared by software (only if LOCK not set). The field selects the input source for COMP Channel1 output blanking: All other values: reserved.", + "bit_offset": 24, + "bit_size": 4, + "enum": "BLANKING" + }, + { + "name": "LOCK", + "description": "Lock This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP Channel1 configuration register COMP_CFGR1[31:0].", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/CFGR2": { + "description": "Comparator configuration register 2.", + "fields": [ + { + "name": "INPSEL0", + "description": "COMP non-inverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of COMP channel. See Table-145: COMP1 noninverting input assignment for more details.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "LOCK", + "description": "Lock This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP Channel1 configuration register COMP_CFGR2[31:0].", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/ICFR": { + "description": "Comparator interrupt clear flag register.", + "fields": [ + { + "name": "CCIF", + "description": "Clear COMP Channel1 interrupt flag Writing 1 clears the C1IF flag in the COMP_SR register.", + "bit_offset": 16, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + } + ] + }, + "fieldset/SR": { + "description": "Comparator status register.", + "fields": [ + { + "name": "CIF", + "description": "COMP Channel1 interrupt flag This bit is set by hardware when the COMP Channel1 output is set This bit is cleared by software writing 1 the CC1IF bit in the COMP_ICFR register.", + "bit_offset": 16, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "CVAL", + "description": "COMP Channel1 output status bit This bit is read-only. It reflects the current COMP Channel1 output taking into account POLARITY and BLANKING bits effect.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + } + ] + }, + "enum/BLANKING": { + "bit_size": 4, + "variants": [ + { + "name": "NoBlanking", + "value": 0 + }, + { + "name": "Tim1Oc5", + "value": 1 + }, + { + "name": "Tim2Oc3", + "value": 2 + }, + { + "name": "Tim3Oc3", + "value": 3 + }, + { + "name": "Tim3Oc4", + "value": 4 + }, + { + "name": "Lptim1Ch2", + "value": 5 + }, + { + "name": "Lptim2Ch2", + "value": 6 + } + ] + }, + "enum/HYST": { + "bit_size": 2, + "variants": [ + { + "name": "None", + "value": 0 + }, + { + "name": "Low", + "value": 1 + }, + { + "name": "Medium", + "value": 2 + }, + { + "name": "High", + "value": 3 + } + ] + }, + "enum/INMSEL": { + "bit_size": 4, + "variants": [ + { + "name": "VRef_1over4", + "value": 0 + }, + { + "name": "VRef_1over2", + "value": 1 + }, + { + "name": "VRef_3over4", + "value": 2 + }, + { + "name": "VRef", + "value": 3 + }, + { + "name": "Dac1Out1", + "value": 4 + }, + { + "name": "Inm1", + "value": 5 + }, + { + "name": "Inm2", + "value": 6 + }, + { + "name": "Inm3", + "value": 7 + }, + { + "name": "VSense", + "value": 8 + }, + { + "name": "VBat_1over4", + "value": 9 + } + ] + }, + "enum/PWRMODE": { + "bit_size": 2, + "variants": [ + { + "name": "High", + "description": "High speed / full power", + "value": 0 + }, + { + "name": "Medium", + "description": "Medium speed / medium power", + "value": 1 + }, + { + "name": "MediumEither", + "description": "Medium speed / medium power", + "value": 2 + }, + { + "name": "Low", + "description": "Ultra low power / ultra-low-power", + "value": 3 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/comp_h7_a.json b/data/registers/comp_h7_a.json new file mode 100644 index 0000000..35fd497 --- /dev/null +++ b/data/registers/comp_h7_a.json @@ -0,0 +1,315 @@ +{ + "block/COMP": { + "description": "COMP1.", + "items": [ + { + "name": "SR", + "description": "Comparator status register.", + "byte_offset": 0, + "access": "Read", + "fieldset": "SR" + }, + { + "name": "ICFR", + "description": "Comparator interrupt clear flag register.", + "byte_offset": 4, + "access": "Write", + "fieldset": "ICFR" + }, + { + "name": "OR", + "description": "Comparator option register.", + "byte_offset": 8, + "fieldset": "OR" + }, + { + "name": "CFGR1", + "description": "Comparator configuration register 1.", + "byte_offset": 12, + "fieldset": "CFGR1" + }, + { + "name": "CFGR2", + "description": "Comparator configuration register 2.", + "byte_offset": 16, + "fieldset": "CFGR2" + } + ] + }, + "fieldset/CFGR1": { + "description": "Comparator configuration register 1.", + "fields": [ + { + "name": "EN", + "description": "COMP channel 1 enable bit.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "BRGEN", + "description": "Scaler bridge enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "SCALEN", + "description": "Voltage scaler enable bit.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "POLARITY", + "description": "COMP channel 1 polarity selection bit.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "ITEN", + "description": "COMP channel 1 interrupt enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "HYST", + "description": "COMP channel 1 hysteresis selection bits.", + "bit_offset": 8, + "bit_size": 2, + "enum": "HYST" + }, + { + "name": "PWRMODE", + "description": "Power Mode of the COMP channel 1.", + "bit_offset": 12, + "bit_size": 2, + "enum": "PWRMODE" + }, + { + "name": "INMSEL", + "description": "COMP channel 1 inverting input selection field.", + "bit_offset": 16, + "bit_size": 4, + "enum": "INMSEL" + }, + { + "name": "INPSEL", + "description": "COMP channel 1 non-inverting input selection bit.", + "bit_offset": 20, + "bit_size": 1, + "enum": "INPSEL" + }, + { + "name": "BLANKING", + "description": "COMP channel 1 blanking source selection bits.", + "bit_offset": 24, + "bit_size": 4, + "enum": "BLANKING" + }, + { + "name": "LOCK", + "description": "Lock bit.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/CFGR2": { + "extends": "CFGR1", + "description": "Comparator configuration register 2.", + "fields": [ + { + "name": "WINMODE", + "description": "Window comparator mode selection bit.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/ICFR": { + "description": "Comparator interrupt clear flag register.", + "fields": [ + { + "name": "CCIF", + "description": "Clear COMP channel 1 Interrupt Flag.", + "bit_offset": 16, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + } + ] + }, + "fieldset/OR": { + "description": "Comparator option register.", + "fields": [ + { + "name": "AFOP", + "description": "Selection of source for alternate function of output ports.", + "bit_offset": 0, + "bit_size": 11 + } + ] + }, + "fieldset/SR": { + "description": "Comparator status register.", + "fields": [ + { + "name": "CVAL", + "description": "COMP channel 1 output status bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + }, + { + "name": "CIF", + "description": "COMP channel 1 Interrupt Flag.", + "bit_offset": 16, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + } + ] + }, + "enum/BLANKING": { + "bit_size": 4, + "variants": [ + { + "name": "NoBlanking", + "value": 0 + }, + { + "name": "Tim1Oc5", + "value": 1 + }, + { + "name": "Tim2Oc3", + "value": 2 + }, + { + "name": "Tim3Oc3", + "value": 3 + }, + { + "name": "Tim3Oc4", + "value": 4 + }, + { + "name": "Tim8Oc5", + "value": 5 + }, + { + "name": "Tim15Oc1", + "value": 6 + } + ] + }, + "enum/HYST": { + "bit_size": 2, + "variants": [ + { + "name": "None", + "value": 0 + }, + { + "name": "Low", + "value": 1 + }, + { + "name": "Medium", + "value": 2 + }, + { + "name": "High", + "value": 3 + } + ] + }, + "enum/INMSEL": { + "bit_size": 4, + "variants": [ + { + "name": "VRef_1over4", + "value": 0 + }, + { + "name": "VRef_1over2", + "value": 1 + }, + { + "name": "VRef_3over4", + "value": 2 + }, + { + "name": "VRef", + "value": 3 + }, + { + "name": "Inm4", + "value": 4 + }, + { + "name": "Inm5", + "value": 5 + }, + { + "name": "Inm6", + "value": 6 + }, + { + "name": "Inm7", + "value": 7 + }, + { + "name": "Inm8", + "value": 8 + }, + { + "name": "Inm9", + "value": 9 + } + ] + }, + "enum/INPSEL": { + "bit_size": 1, + "variants": [ + { + "name": "INP1", + "value": 0 + }, + { + "name": "INP2", + "value": 1 + } + ] + }, + "enum/PWRMODE": { + "bit_size": 2, + "variants": [ + { + "name": "High", + "description": "High speed / full power", + "value": 0 + }, + { + "name": "Medium", + "description": "Medium speed / medium power", + "value": 1 + }, + { + "name": "MediumEither", + "description": "Medium speed / medium power", + "value": 2 + }, + { + "name": "Low", + "description": "Ultra low power / ultra-low-power", + "value": 3 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/comp_h7_b.json b/data/registers/comp_h7_b.json new file mode 100644 index 0000000..4ed41b7 --- /dev/null +++ b/data/registers/comp_h7_b.json @@ -0,0 +1,307 @@ +{ + "block/COMP": { + "description": "COMP1.", + "items": [ + { + "name": "SR", + "description": "Comparator status register.", + "byte_offset": 0, + "access": "Read", + "fieldset": "SR" + }, + { + "name": "ICFR", + "description": "Comparator interrupt clear flag register.", + "byte_offset": 4, + "access": "Write", + "fieldset": "ICFR" + }, + { + "name": "OR", + "description": "Comparator option register.", + "byte_offset": 8, + "fieldset": "OR" + }, + { + "name": "CFGR1", + "description": "Comparator configuration register 1.", + "byte_offset": 12, + "fieldset": "CFGR1" + }, + { + "name": "CFGR2", + "description": "Comparator configuration register 2.", + "byte_offset": 16, + "fieldset": "CFGR2" + } + ] + }, + "fieldset/CFGR1": { + "description": "Comparator configuration register 1.", + "fields": [ + { + "name": "EN", + "description": "COMP channel 1 enable bit.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "BRGEN", + "description": "Scaler bridge enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "SCALEN", + "description": "Voltage scaler enable bit.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "POLARITY", + "description": "COMP channel 1 polarity selection bit.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "ITEN", + "description": "COMP channel 1 interrupt enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "HYST", + "description": "COMP channel 1 hysteresis selection bits.", + "bit_offset": 8, + "bit_size": 2, + "enum": "HYST" + }, + { + "name": "PWRMODE", + "description": "Power Mode of the COMP channel 1.", + "bit_offset": 12, + "bit_size": 2, + "enum": "PWRMODE" + }, + { + "name": "INMSEL", + "description": "COMP channel 1 inverting input selection field.", + "bit_offset": 16, + "bit_size": 3, + "enum": "INMSEL" + }, + { + "name": "INPSEL", + "description": "COMP channel 1 non-inverting input selection bit.", + "bit_offset": 20, + "bit_size": 1, + "enum": "INPSEL" + }, + { + "name": "BLANKING", + "description": "COMP channel 1 blanking source selection bits.", + "bit_offset": 24, + "bit_size": 4, + "enum": "BLANKING" + }, + { + "name": "LOCK", + "description": "Lock bit.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/CFGR2": { + "extends": "CFGR1", + "description": "Comparator configuration register 2.", + "fields": [ + { + "name": "WINMODE", + "description": "Window comparator mode selection bit.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/ICFR": { + "description": "Comparator interrupt clear flag register.", + "fields": [ + { + "name": "CCIF", + "description": "Clear COMP channel 1 Interrupt Flag.", + "bit_offset": 16, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + } + ] + }, + "fieldset/OR": { + "description": "Comparator option register.", + "fields": [ + { + "name": "AFOP", + "description": "Selection of source for alternate function of output ports.", + "bit_offset": 0, + "bit_size": 11 + } + ] + }, + "fieldset/SR": { + "description": "Comparator status register.", + "fields": [ + { + "name": "CVAL", + "description": "COMP channel 1 output status bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + }, + { + "name": "CIF", + "description": "COMP channel 1 Interrupt Flag.", + "bit_offset": 16, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + } + ] + }, + "enum/BLANKING": { + "bit_size": 4, + "variants": [ + { + "name": "NoBlanking", + "value": 0 + }, + { + "name": "Tim1Oc5", + "value": 1 + }, + { + "name": "Tim2Oc3", + "value": 2 + }, + { + "name": "Tim3Oc3", + "value": 3 + }, + { + "name": "Tim3Oc4", + "value": 4 + }, + { + "name": "Tim8Oc5", + "value": 5 + }, + { + "name": "Tim15Oc1", + "value": 6 + } + ] + }, + "enum/HYST": { + "bit_size": 2, + "variants": [ + { + "name": "None", + "value": 0 + }, + { + "name": "Low", + "value": 1 + }, + { + "name": "Medium", + "value": 2 + }, + { + "name": "High", + "value": 3 + } + ] + }, + "enum/INMSEL": { + "bit_size": 3, + "variants": [ + { + "name": "VRef_1over4", + "value": 0 + }, + { + "name": "VRef_1over2", + "value": 1 + }, + { + "name": "VRef_3over4", + "value": 2 + }, + { + "name": "VRef", + "value": 3 + }, + { + "name": "Inm1", + "value": 4 + }, + { + "name": "Inm2", + "value": 5 + }, + { + "name": "COMPx_Inm1", + "value": 6 + }, + { + "name": "COMPx_Inm2", + "value": 7 + } + ] + }, + "enum/INPSEL": { + "bit_size": 1, + "variants": [ + { + "name": "INP1", + "value": 0 + }, + { + "name": "INP2", + "value": 1 + } + ] + }, + "enum/PWRMODE": { + "bit_size": 2, + "variants": [ + { + "name": "High", + "description": "High speed / full power", + "value": 0 + }, + { + "name": "Medium", + "description": "Medium speed / medium power", + "value": 1 + }, + { + "name": "MediumEither", + "description": "Medium speed / medium power", + "value": 2 + }, + { + "name": "Low", + "description": "Ultra low power / ultra-low-power", + "value": 3 + } + ] + } +} \ No newline at end of file