block/CS:
  description: CS.
  items:
  - name: CSCTL0
    description: Clock System Control 0.
    byte_offset: 0
    bit_size: 16
    fieldset: CSCTL0
  - name: CSCTL1
    description: Clock System Control 1.
    byte_offset: 2
    bit_size: 16
    fieldset: CSCTL1
  - name: CSCTL2
    description: Clock System Control 2.
    byte_offset: 4
    bit_size: 16
    fieldset: CSCTL2
  - name: CSCTL3
    description: Clock System Control 3.
    byte_offset: 6
    bit_size: 16
    fieldset: CSCTL3
  - name: CSCTL4
    description: Clock System Control 4.
    byte_offset: 8
    bit_size: 16
    fieldset: CSCTL4
  - name: CSCTL5
    description: Clock System Control 5.
    byte_offset: 10
    bit_size: 16
    fieldset: CSCTL5
  - name: CSCTL6
    description: Clock System Control 6.
    byte_offset: 12
    bit_size: 16
    fieldset: CSCTL6
  - name: CSCTL7
    description: Clock System Control Register 7.
    byte_offset: 14
    bit_size: 16
    fieldset: CSCTL7
  - name: CSCTL8
    description: Clock System Control Register 8.
    byte_offset: 16
    bit_size: 16
    fieldset: CSCTL8
fieldset/CSCTL0:
  description: Clock System Control 0.
  bit_size: 16
  fields:
  - name: DCO
    description: DCO tap selection. These bits select the DCO tap and are modified automatically during FLL operation.
    bit_offset: 0
    bit_size: 9
  - name: MOD
    description: Modulation bit counter. These bits select the modulation pattern. All MOD bits are modified automatically during FLL operation. The DCO register value is incremented when the modulation bit counter rolls over from 31 to 0. If the modulation bit counter decrements from 0 to the maximum count, the DCO register value is also decreased.
    bit_offset: 9
    bit_size: 5
fieldset/CSCTL1:
  description: Clock System Control 1.
  bit_size: 16
  fields:
  - name: DISMOD
    description: Modulation. This bit enables/disables the modulation.
    bit_offset: 0
    bit_size: 1
    enum: DISMOD
  - name: DCORSEL
    description: DCO Range Select.
    bit_offset: 1
    bit_size: 3
    enum: DCORSEL
  - name: DCOFTRIM
    description: DCO frequency trim. These bits trims the DCO frequency. By default, it is chipspecific trimmed. These bits can also be trimmed by user code.
    bit_offset: 4
    bit_size: 3
  - name: DCOFTRIMEN
    description: DCO Frequency Trim Enable. When this bit is set, DCOFTRIM value is selected to set DCO frequency. Otherwise, DCOFTRIM value is bypassed and DCO applies default settings in manufacture.
    bit_offset: 7
    bit_size: 1
    enum: DCOFTRIMEN
fieldset/CSCTL2:
  description: Clock System Control 2.
  bit_size: 16
  fields:
  - name: FLLN
    description: Multiplier bits. These bits set the multiplier value N of the DCO. N must be greater than 0. Writing zero to FLLN causes N to be set to 1.
    bit_offset: 0
    bit_size: 10
  - name: FLLD
    description: FLL loop divider. These bits divide f(DCOCLK) in the FLL feedback loop. This results in an additional multiplier for the multiplier bits. See also multiplier bits.
    bit_offset: 12
    bit_size: 3
    enum: FLLD
fieldset/CSCTL3:
  description: Clock System Control 3.
  bit_size: 16
  fields:
  - name: FLLREFDIV
    description: FLL reference divider. These bits define the divide factor for f(FLLREFCLK). If XT1 supports high frequency input higher than 32 kHz, the divided frequency is used as the FLL reference frequency. If XT1 only supports 32-kHz clock, FLLREFDIV is always read and written as zero, 000b = fFLLREFCLK / 1.
    bit_offset: 0
    bit_size: 3
    enum: FLLREFDIV
  - name: SELREF
    description: FLL reference select. These bits select the FLL reference clock source.
    bit_offset: 4
    bit_size: 2
    enum: SELREF
  - name: REFOLP
    description: REFO Low Power Enable. This bit turns on REFO low-power mode. During switch, the low-power mode will be invalid until REFOREADY is set.
    bit_offset: 7
    bit_size: 1
    enum: REFOLP
fieldset/CSCTL4:
  description: Clock System Control 4.
  bit_size: 16
  fields:
  - name: SELMS
    description: Selects the MCLK and SMCLK source.
    bit_offset: 0
    bit_size: 3
    enum: SELMS
  - name: SELA
    description: Selects the ACLK source.
    bit_offset: 8
    bit_size: 2
    enum: SELA
fieldset/CSCTL5:
  description: Clock System Control 5.
  bit_size: 16
  fields:
  - name: DIVM
    description: MCLK source divider.
    bit_offset: 0
    bit_size: 3
    enum: DIVM
  - name: DIVS
    description: SMCLK source divider. SMCLK directly derives from MCLK. SMCLK frequency is the combination of DIVM and DIVS out of selected clock source.
    bit_offset: 4
    bit_size: 2
    enum: DIVS
  - name: SMCLKOFF
    description: SMCLK off. This bit turns off SMCLK clock.
    bit_offset: 8
    bit_size: 1
    enum: SMCLKOFF
  - name: VLOAUTOOFF
    description: VLO automatic off enable. This bit turns off VLO, if VLO is not used.
    bit_offset: 12
    bit_size: 1
    enum: VLOAUTOOFF
fieldset/CSCTL6:
  description: Clock System Control 6.
  bit_size: 16
  fields:
  - name: XT1AUTOOFF
    description: XT1 automatic off enable. This bit allows XT1 turned turns off when it is not used.
    bit_offset: 0
    bit_size: 1
    enum: XT1AUTOOFF
  - name: XT1AGCOFF
    description: Automatic Gain Control (AGC) disable.
    bit_offset: 1
    bit_size: 1
    enum: XT1AGCOFF
  - name: XT1HFFREQ
    description: The XT1 High-frequency selection. These bits must be set to appropriate frequency for crystal or bypass modes of operation.
    bit_offset: 2
    bit_size: 2
    enum: XT1HFFREQ
  - name: XT1BYPASS
    description: XT1 bypass select.
    bit_offset: 4
    bit_size: 1
    enum: XT1BYPASS
  - name: XTS
    description: XT1 mode select.
    bit_offset: 5
    bit_size: 1
    enum: XTS
  - name: XT1DRIVE
    description: The XT1 oscillator current can be adjusted to its drive needs. Initially, it starts with the highest supply current for reliable and quick startup. If needed, user software can reduce the drive strength. The configuration of these bits is retained during LPM3.5 until LOCKLPM5 is cleared, but not the register bits itself; therefore, reconfiguration after wake-up from LPM3.5 before clearing LOCKLPM5 is required.
    bit_offset: 6
    bit_size: 2
    enum: XT1DRIVE
  - name: DIVA
    description: ACLK source divider.
    bit_offset: 8
    bit_size: 4
    enum: DIVA
  - name: XT1FAULTOFF
    description: The XT1 oscillator fault detection off.
    bit_offset: 13
    bit_size: 1
    enum: XT1FAULTOFF
fieldset/CSCTL7:
  description: Clock System Control Register 7.
  bit_size: 16
  fields:
  - name: DCOFFG
    description: DCO fault flag. If this bit is set, the OFIFG flag is also set. The DCOFFG bit is set if DCO = {0} or DCO = {511}. DCOFFG can be cleared by software. If the DCO fault condition still remains, DCOFFG is set. As long as DCOFFG is set, FLLUNLOCK shows the DCOERROR condition.
    bit_offset: 0
    bit_size: 1
    enum: DCOFFG
  - name: XT1OFFG
    description: T1 oscillator fault flag. If this bit is set, the OFIFG flag is also set. XT1OFFG is set if a XT1 fault condition exists. XT1OFFG can be cleared by software. If the XT1 fault condition still remains, XT1OFFG is set.
    bit_offset: 1
    bit_size: 1
    enum: XT1OFFG
  - name: REFOREADY
    description: REFO ready flag. This bit reflects the REFO readiness whent REFO is good for operation (such as FLL reference).
    bit_offset: 2
    bit_size: 1
    enum: REFOREADY
  - name: FLLULIFG
    description: FLL unlock interrupt flag. This flag is set when FLLUNLOCK bits equal 10b (DCO too fast). If FLLULPUC is also set, a PUC is triggered when FLLUIFG is set.
    bit_offset: 4
    bit_size: 1
    enum: FLLULIFG
  - name: ENSTFCNT1
    description: Enable start counter for XT1.
    bit_offset: 6
    bit_size: 1
    enum: ENSTFCNT1
  - name: FLLUNLOCK
    description: Unlock. These bits indicate the current FLL unlock condition. These bits are both set as long as the DCOFFG flag is set.
    bit_offset: 8
    bit_size: 2
    enum: FLLUNLOCK
  - name: FLLUNLOCKHIS
    description: Unlock history bits. These bits indicate the FLL unlock condition history. As soon as any unlock condition happens, the respective bits are set and remain set until cleared by software by writing 0 to it or by a POR.
    bit_offset: 10
    bit_size: 2
    enum: FLLUNLOCKHIS
  - name: FLLULPUC
    description: FLL unlock PUC enable. If the FLLULPUC bit is set, a reset (PUC) is triggered if FLLULIFG is set. FLLULIFG indicates when FLLUNLOCK bits equal 10 (too fast). FLLULPUC is automatically cleared upon servicing the event. If FLLULPUC is cleared (0), no PUC can be triggered by FLLULIFG.
    bit_offset: 12
    bit_size: 1
  - name: FLLWARNEN
    description: Warning enable. If this bit is set, an interrupt is generated based on the FLLUNLOCKHIS bits. If FLLUNLOCKHIS is not equal to 00, an OFIFG is generated.
    bit_offset: 13
    bit_size: 1
    enum: FLLWARNEN
fieldset/CSCTL8:
  description: Clock System Control Register 8.
  bit_size: 16
  fields:
  - name: ACLKREQEN
    description: ACLK clock request enable. Setting this enables conditional module requests for ACLK.
    bit_offset: 0
    bit_size: 1
    enum: ACLKREQEN
  - name: MCLKREQEN
    description: MCLK clock request enable. Setting this enables conditional module requests for MCLK.
    bit_offset: 1
    bit_size: 1
    enum: MCLKREQEN
  - name: SMCLKREQEN
    description: SMCLK clock request enable. Setting this enables conditional module requests for SMCLK.
    bit_offset: 2
    bit_size: 1
    enum: SMCLKREQEN
  - name: MODOSCREQEN
    description: MODOSC clock request enable. Setting this enables conditional module requests for MODOSC.
    bit_offset: 3
    bit_size: 1
    enum: MODOSCREQEN
enum/ACLKREQEN:
  bit_size: 1
  variants:
  - name: ACLKREQEN_0
    description: ACLK conditional requests are disabled.
    value: 0
  - name: ACLKREQEN_1
    description: ACLK conditional requests are enabled.
    value: 1
enum/DCOFFG:
  bit_size: 1
  variants:
  - name: DCOFFG_0
    description: No fault condition occurred after the last reset.
    value: 0
  - name: DCOFFG_1
    description: DCO fault. A DCO fault occurred after the last reset.
    value: 1
enum/DCOFTRIMEN:
  bit_size: 1
  variants:
  - name: DCOFTRIMEN_0
    description: Disable frequency trim.
    value: 0
  - name: DCOFTRIMEN_1
    description: Enable frequency trim.
    value: 1
enum/DCORSEL:
  bit_size: 3
  variants:
  - name: DCORSEL_0
    description: 1 MHz.
    value: 0
  - name: DCORSEL_1
    description: 2 MHz.
    value: 1
  - name: DCORSEL_2
    description: 4 MHz.
    value: 2
  - name: DCORSEL_3
    description: 8 MHz.
    value: 3
  - name: DCORSEL_4
    description: 12 MHz.
    value: 4
  - name: DCORSEL_5
    description: 16 MHz.
    value: 5
  - name: DCORSEL_6
    description: 20 MHz(Only avaliable in 24MHz clock system).
    value: 6
  - name: DCORSEL_7
    description: 24 MHz(Only avaliable in 24MHz clock system).
    value: 7
enum/DISMOD:
  bit_size: 1
  variants:
  - name: DISMOD_0
    description: Modulation enabled.
    value: 0
  - name: DISMOD_1
    description: Modulation disabled.
    value: 1
enum/DIVA:
  bit_size: 4
  variants:
  - name: '1'
    description: /1.
    value: 0
  - name: '16'
    description: /16.
    value: 1
  - name: '32'
    description: /32.
    value: 2
  - name: '64'
    description: /64.
    value: 3
  - name: '128'
    description: /128.
    value: 4
  - name: '256'
    description: /256.
    value: 5
  - name: '384'
    description: /384.
    value: 6
  - name: '512'
    description: /512.
    value: 7
  - name: '768'
    description: /768(Only available in 24MHz clock system, 24 MHz preference).
    value: 8
  - name: '1024'
    description: /1024(Only available in 24MHz clock system, 24 MHz preference).
    value: 9
  - name: '108'
    description: /108(Only available in 24MHz clock system, 24 MHz preference).
    value: 10
  - name: '338'
    description: 338(Only available in 24MHz clock system, 24 MHz preference).
    value: 11
  - name: '414'
    description: 414(Only available in 24MHz clock system, 24 MHz preference).
    value: 12
  - name: '640'
    description: 640(Only available in 24MHz clock system, 24 MHz preference).
    value: 13
  - name: DIVA_14
    description: Reserved.
    value: 14
  - name: DIVA_15
    description: Reserved.
    value: 15
enum/DIVM:
  bit_size: 3
  variants:
  - name: '1'
    description: /1.
    value: 0
  - name: '2'
    description: /2.
    value: 1
  - name: '4'
    description: /4.
    value: 2
  - name: '8'
    description: /8.
    value: 3
  - name: '16'
    description: /16.
    value: 4
  - name: '32'
    description: /32.
    value: 5
  - name: '64'
    description: /64.
    value: 6
  - name: '128'
    description: /128.
    value: 7
enum/DIVS:
  bit_size: 2
  variants:
  - name: '1'
    description: /1.
    value: 0
  - name: '2'
    description: /2.
    value: 1
  - name: '4'
    description: /4.
    value: 2
  - name: '8'
    description: /8.
    value: 3
enum/ENSTFCNT1:
  bit_size: 1
  variants:
  - name: ENSTFCNT1_0
    description: Startup fault counter disabled. Counter is cleared..
    value: 0
  - name: ENSTFCNT1_1
    description: Startup fault counter enabled.
    value: 1
enum/FLLD:
  bit_size: 3
  variants:
  - name: '1'
    description: fDCOCLK / 1.
    value: 0
  - name: '2'
    description: fDCOCLK / 2.
    value: 1
  - name: '4'
    description: fDCOCLK / 4.
    value: 2
  - name: '8'
    description: fDCOCLK / 8.
    value: 3
  - name: '16'
    description: fDCOCLK / 16.
    value: 4
  - name: '32'
    description: fDCOCLK / 32.
    value: 5
  - name: FLLD_6
    description: fDCOCLK / 40(Only avaliable in 24MHz clock system).
    value: 6
  - name: FLLD_7
    description: fDCOCLK / 48(Only avaliable in 24MHz clock system).
    value: 7
enum/FLLREFDIV:
  bit_size: 3
  variants:
  - name: '1'
    description: fFLLREFCLK / 1.
    value: 0
  - name: '32'
    description: fFLLREFCLK / 32.
    value: 1
  - name: '64'
    description: fFLLREFCLK / 64.
    value: 2
  - name: '128'
    description: fFLLREFCLK / 128.
    value: 3
  - name: '256'
    description: fFLLREFCLK / 256.
    value: 4
  - name: '512'
    description: fFLLREFCLK / 512.
    value: 5
  - name: FLLREFDIV_6
    description: fFLLREFCLK / 640 (only available in 24MHz clock system).
    value: 6
  - name: FLLREFDIV_7
    description: fFLLREFCLK / 768(only available in 24MHz clock system).
    value: 7
enum/FLLULIFG:
  bit_size: 1
  variants:
  - name: FLLULIFG_0
    description: FLLUNLOCK bits not equal to 10b.
    value: 0
  - name: FLLULIFG_1
    description: FLLUNLOCK bits equal to 10b.
    value: 1
enum/FLLUNLOCK:
  bit_size: 2
  variants:
  - name: FLLUNLOCK_0
    description: FLL is locked. No unlock condition currently active.
    value: 0
  - name: FLLUNLOCK_1
    description: DCOCLK is currently too slow.
    value: 1
  - name: FLLUNLOCK_2
    description: DCOCLK is currently too fast.
    value: 2
  - name: FLLUNLOCK_3
    description: DCOERROR. DCO out of range.
    value: 3
enum/FLLUNLOCKHIS:
  bit_size: 2
  variants:
  - name: FLLUNLOCKHIS_0
    description: FLL is locked. No unlock situation has been detected since the last reset of these bits.
    value: 0
  - name: FLLUNLOCKHIS_1
    description: DCOCLK has been too slow since the bits were cleared.
    value: 1
  - name: FLLUNLOCKHIS_2
    description: DCOCLK has been too fast since the bits were cleared.
    value: 2
  - name: FLLUNLOCKHIS_3
    description: DCOCLK has been both too fast and too slow since the bits were cleared.
    value: 3
enum/FLLWARNEN:
  bit_size: 1
  variants:
  - name: FLLWARNEN_0
    description: FLLUNLOCKHIS status cannot set OFIFG.
    value: 0
  - name: FLLWARNEN_1
    description: FLLUNLOCKHIS status can set OFIFG.
    value: 1
enum/MCLKREQEN:
  bit_size: 1
  variants:
  - name: MCLKREQEN_0
    description: MCLK conditional requests are disabled.
    value: 0
  - name: MCLKREQEN_1
    description: MCLK conditional requests are enabled.
    value: 1
enum/MODOSCREQEN:
  bit_size: 1
  variants:
  - name: MODOSCREQEN_0
    description: MODOSC conditional requests are disabled.
    value: 0
  - name: MODOSCREQEN_1
    description: MODOSC conditional requests are enabled.
    value: 1
enum/REFOLP:
  bit_size: 1
  variants:
  - name: REFOLP_0
    description: REFO Low Power Disabled (High Power Mode).
    value: 0
  - name: REFOLP_1
    description: REFO Low Power Enabled.
    value: 1
enum/REFOREADY:
  bit_size: 1
  variants:
  - name: REFOREADY_0
    description: REFO unstable.
    value: 0
  - name: REFOREADY_1
    description: REFO ready to go.
    value: 1
enum/SELA:
  bit_size: 2
  variants:
  - name: XT1CLK
    description: XT1CLK with divider (must be no more than 40 kHz).
    value: 0
  - name: REFOCLK
    description: REFO (internal 32-kHz clock source).
    value: 1
  - name: VLOCLK
    description: VLO (internal 10-kHz clock source).
    value: 2
  - name: RESERVED
    description: Reserved.
    value: 3
enum/SELMS:
  bit_size: 3
  variants:
  - name: DCOCLKDIV
    description: DCOCLKDIV.
    value: 0
  - name: REFOCLK
    description: REFOCLK.
    value: 1
  - name: XT1CLK
    description: XT1CLK.
    value: 2
  - name: VLOCLK
    description: VLOCLK.
    value: 3
  - name: SELMS_4
    description: Reserved for future use.
    value: 4
  - name: SELMS_5
    description: Reserved for future use.
    value: 5
  - name: SELMS_6
    description: Reserved for future use.
    value: 6
  - name: SELMS_7
    description: Reserved for future use.
    value: 7
enum/SELREF:
  bit_size: 2
  variants:
  - name: XT1CLK
    description: XT1CLK.
    value: 0
  - name: REFOCLK
    description: REFOCLK.
    value: 1
  - name: SELREF_2
    description: served for future use.
    value: 2
  - name: SELREF_3
    description: served for future use.
    value: 3
enum/SMCLKOFF:
  bit_size: 1
  variants:
  - name: SMCLKOFF_0
    description: SMCLK on.
    value: 0
  - name: SMCLKOFF_1
    description: SMCLK off.
    value: 1
enum/SMCLKREQEN:
  bit_size: 1
  variants:
  - name: SMCLKREQEN_0
    description: SMCLK conditional requests are disabled.
    value: 0
  - name: SMCLKREQEN_1
    description: SMCLK conditional requests are enabled.
    value: 1
enum/VLOAUTOOFF:
  bit_size: 1
  variants:
  - name: VLOAUTOOFF_0
    description: VLO always on.
    value: 0
  - name: VLOAUTOOFF_1
    description: VLO automatically turned off if not used(default).
    value: 1
enum/XT1AGCOFF:
  bit_size: 1
  variants:
  - name: XT1AGCOFF_0
    description: AGC on.
    value: 0
  - name: XT1AGCOFF_1
    description: AGC off.
    value: 1
enum/XT1AUTOOFF:
  bit_size: 1
  variants:
  - name: XT1AUTOOFF_0
    description: XT1 is on if XT1 is selected by the port selection and XT1 is not in bypass mode of operation.
    value: 0
  - name: XT1AUTOOFF_1
    description: XT1 is off if it is not used as a source for ACLK, MCLK, or SMCLK or is not used as a reference source required for FLL operation.
    value: 1
enum/XT1BYPASS:
  bit_size: 1
  variants:
  - name: XT1BYPASS_0
    description: XT1 source internally.
    value: 0
  - name: XT1BYPASS_1
    description: XT1 sources externally from pin.
    value: 1
enum/XT1DRIVE:
  bit_size: 2
  variants:
  - name: XT1DRIVE_0
    description: Lowest drive strength and current consumption.
    value: 0
  - name: XT1DRIVE_1
    description: Lower drive strength and current consumption.
    value: 1
  - name: XT1DRIVE_2
    description: Higher drive strength and current consumption.
    value: 2
  - name: XT1DRIVE_3
    description: Highest drive strength and current consumption.
    value: 3
enum/XT1FAULTOFF:
  bit_size: 1
  variants:
  - name: XT1FAULTOFF_0
    description: Enabling XT1 fault to switch ACLK to REFO.
    value: 0
  - name: XT1FAULTOFF_1
    description: Disabling XT1 fault to switch ACLK to REFO.
    value: 1
enum/XT1HFFREQ:
  bit_size: 2
  variants:
  - name: XT1HFFREQ_0
    description: 1 to 4 MHz.
    value: 0
  - name: XT1HFFREQ_1
    description: 4 MHz to 6 MHz.
    value: 1
  - name: XT1HFFREQ_2
    description: 6 MHz to 16 MHz.
    value: 2
  - name: XT1HFFREQ_3
    description: 16 MHz to 24 MHz.
    value: 3
enum/XT1OFFG:
  bit_size: 1
  variants:
  - name: XT1OFFG_0
    description: No fault condition occurred after the last reset.
    value: 0
  - name: XT1OFFG_1
    description: XT1 fault. An XT1 fault occurred after the last reset.
    value: 1
enum/XTS:
  bit_size: 1
  variants:
  - name: XTS_0
    description: Low-frequency mode.
    value: 0
  - name: XTS_1
    description: High-frequency mode.
    value: 1