block/UART0: description: UART (Universal Asynchronous Receiver-Transmitter) Controller 0. items: - name: FIFO description: FIFO data register. byte_offset: 0 fieldset: FIFO - name: INT_RAW description: Raw interrupt status. byte_offset: 4 fieldset: INT_RAW - name: INT_ST description: Masked interrupt status. byte_offset: 8 fieldset: INT_ST - name: INT_ENA description: Interrupt enable bits. byte_offset: 12 fieldset: INT_ENA - name: INT_CLR description: Interrupt clear bits. byte_offset: 16 fieldset: INT_CLR - name: CLKDIV description: Clock divider configuration. byte_offset: 20 fieldset: CLKDIV - name: RX_FILT description: Rx Filter configuration. byte_offset: 24 fieldset: RX_FILT - name: STATUS description: UART status register. byte_offset: 28 fieldset: STATUS - name: CONF0 description: a. byte_offset: 32 fieldset: CONF0 - name: CONF1 description: Configuration register 1. byte_offset: 36 fieldset: CONF1 - name: LOWPULSE description: Autobaud minimum low pulse duration register. byte_offset: 40 fieldset: LOWPULSE - name: HIGHPULSE description: Autobaud minimum high pulse duration register. byte_offset: 44 fieldset: HIGHPULSE - name: RXD_CNT description: Autobaud edge change count register. byte_offset: 48 fieldset: RXD_CNT - name: FLOW_CONF description: Software flow-control configuration. byte_offset: 52 fieldset: FLOW_CONF - name: SLEEP_CONF description: Sleep-mode configuration. byte_offset: 56 fieldset: SLEEP_CONF - name: SWFC_CONF0 description: Software flow-control character configuration. byte_offset: 60 fieldset: SWFC_CONF0 - name: SWFC_CONF1 description: Software flow-control character configuration. byte_offset: 64 fieldset: SWFC_CONF1 - name: TXBRK_CONF description: Tx Break character configuration. byte_offset: 68 fieldset: TXBRK_CONF - name: IDLE_CONF description: Frame-end idle configuration. byte_offset: 72 fieldset: IDLE_CONF - name: RS485_CONF description: RS485 mode configuration. byte_offset: 76 fieldset: RS485_CONF - name: AT_CMD_PRECNT description: Pre-sequence timing configuration. byte_offset: 80 fieldset: AT_CMD_PRECNT - name: AT_CMD_POSTCNT description: Post-sequence timing configuration. byte_offset: 84 fieldset: AT_CMD_POSTCNT - name: AT_CMD_GAPTOUT description: Timeout configuration. byte_offset: 88 fieldset: AT_CMD_GAPTOUT - name: AT_CMD_CHAR description: AT escape sequence detection configuration. byte_offset: 92 fieldset: AT_CMD_CHAR - name: MEM_CONF description: UART threshold and allocation configuration. byte_offset: 96 fieldset: MEM_CONF - name: MEM_TX_STATUS description: Tx-FIFO write and read offset address. byte_offset: 100 fieldset: MEM_TX_STATUS - name: MEM_RX_STATUS description: Rx-FIFO write and read offset address. byte_offset: 104 fieldset: MEM_RX_STATUS - name: FSM_STATUS description: UART transmit and receive status. byte_offset: 108 fieldset: FSM_STATUS - name: POSPULSE description: Autobaud high pulse register. byte_offset: 112 fieldset: POSPULSE - name: NEGPULSE description: Autobaud low pulse register. byte_offset: 116 fieldset: NEGPULSE - name: CLK_CONF description: UART core clock configuration. byte_offset: 120 fieldset: CLK_CONF - name: DATE description: UART Version register. byte_offset: 124 fieldset: DATE - name: ID description: UART ID register. byte_offset: 128 fieldset: ID fieldset/AT_CMD_CHAR: description: AT escape sequence detection configuration. fields: - name: AT_CMD_CHAR description: This register is used to configure the content of at_cmd char. bit_offset: 0 bit_size: 8 - name: CHAR_NUM description: This register is used to configure the num of continuous at_cmd chars received by receiver. bit_offset: 8 bit_size: 8 fieldset/AT_CMD_GAPTOUT: description: Timeout configuration. fields: - name: RX_GAP_TOUT description: This register is used to configure the duration time between the at_cmd chars. bit_offset: 0 bit_size: 16 fieldset/AT_CMD_POSTCNT: description: Post-sequence timing configuration. fields: - name: POST_IDLE_NUM description: This register is used to configure the duration time between the last at_cmd and the next data. bit_offset: 0 bit_size: 16 fieldset/AT_CMD_PRECNT: description: Pre-sequence timing configuration. fields: - name: PRE_IDLE_NUM description: This register is used to configure the idle duration time before the first at_cmd is received by receiver. bit_offset: 0 bit_size: 16 fieldset/CLKDIV: description: Clock divider configuration. fields: - name: CLKDIV description: The integral part of the frequency divider factor. bit_offset: 0 bit_size: 12 - name: FRAG description: The decimal part of the frequency divider factor. bit_offset: 20 bit_size: 4 fieldset/CLK_CONF: description: UART core clock configuration. fields: - name: SCLK_DIV_B description: The denominator of the frequency divider factor. bit_offset: 0 bit_size: 6 - name: SCLK_DIV_A description: The numerator of the frequency divider factor. bit_offset: 6 bit_size: 6 - name: SCLK_DIV_NUM description: The integral part of the frequency divider factor. bit_offset: 12 bit_size: 8 - name: SCLK_SEL description: 'UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.' bit_offset: 20 bit_size: 2 - name: SCLK_EN description: Set this bit to enable UART Tx/Rx clock. bit_offset: 22 bit_size: 1 - name: RST_CORE description: Write 1 then write 0 to this bit, reset UART Tx/Rx. bit_offset: 23 bit_size: 1 - name: TX_SCLK_EN description: Set this bit to enable UART Tx clock. bit_offset: 24 bit_size: 1 - name: RX_SCLK_EN description: Set this bit to enable UART Rx clock. bit_offset: 25 bit_size: 1 - name: TX_RST_CORE description: Write 1 then write 0 to this bit, reset UART Tx. bit_offset: 26 bit_size: 1 - name: RX_RST_CORE description: Write 1 then write 0 to this bit, reset UART Rx. bit_offset: 27 bit_size: 1 fieldset/CONF0: description: a. fields: - name: PARITY description: This register is used to configure the parity check mode. bit_offset: 0 bit_size: 1 - name: PARITY_EN description: Set this bit to enable uart parity check. bit_offset: 1 bit_size: 1 - name: BIT_NUM description: This register is used to set the length of data. bit_offset: 2 bit_size: 2 - name: STOP_BIT_NUM description: This register is used to set the length of stop bit. bit_offset: 4 bit_size: 2 - name: SW_RTS description: This register is used to configure the software rts signal which is used in software flow control. bit_offset: 6 bit_size: 1 - name: SW_DTR description: This register is used to configure the software dtr signal which is used in software flow control. bit_offset: 7 bit_size: 1 - name: TXD_BRK description: Set this bit to enbale transmitter to send NULL when the process of sending data is done. bit_offset: 8 bit_size: 1 - name: IRDA_DPLX description: Set this bit to enable IrDA loopback mode. bit_offset: 9 bit_size: 1 - name: IRDA_TX_EN description: This is the start enable bit for IrDA transmitter. bit_offset: 10 bit_size: 1 - name: IRDA_WCTL description: '1''h1: The IrDA transmitter''s 11th bit is the same as 10th bit. 1''h0: Set IrDA transmitter''s 11th bit to 0.' bit_offset: 11 bit_size: 1 - name: IRDA_TX_INV description: Set this bit to invert the level of IrDA transmitter. bit_offset: 12 bit_size: 1 - name: IRDA_RX_INV description: Set this bit to invert the level of IrDA receiver. bit_offset: 13 bit_size: 1 - name: LOOPBACK description: Set this bit to enable uart loopback test mode. bit_offset: 14 bit_size: 1 - name: TX_FLOW_EN description: Set this bit to enable flow control function for transmitter. bit_offset: 15 bit_size: 1 - name: IRDA_EN description: Set this bit to enable IrDA protocol. bit_offset: 16 bit_size: 1 - name: RXFIFO_RST description: Set this bit to reset the uart receive-FIFO. bit_offset: 17 bit_size: 1 - name: TXFIFO_RST description: Set this bit to reset the uart transmit-FIFO. bit_offset: 18 bit_size: 1 - name: RXD_INV description: Set this bit to inverse the level value of uart rxd signal. bit_offset: 19 bit_size: 1 - name: CTS_INV description: Set this bit to inverse the level value of uart cts signal. bit_offset: 20 bit_size: 1 - name: DSR_INV description: Set this bit to inverse the level value of uart dsr signal. bit_offset: 21 bit_size: 1 - name: TXD_INV description: Set this bit to inverse the level value of uart txd signal. bit_offset: 22 bit_size: 1 - name: RTS_INV description: Set this bit to inverse the level value of uart rts signal. bit_offset: 23 bit_size: 1 - name: DTR_INV description: Set this bit to inverse the level value of uart dtr signal. bit_offset: 24 bit_size: 1 - name: CLK_EN description: '1''h1: Force clock on for register. 1''h0: Support clock only when application writes registers.' bit_offset: 25 bit_size: 1 - name: ERR_WR_MASK description: '1''h1: Receiver stops storing data into FIFO when data is wrong. 1''h0: Receiver stores the data even if the received data is wrong.' bit_offset: 26 bit_size: 1 - name: AUTOBAUD_EN description: This is the enable bit for detecting baudrate. bit_offset: 27 bit_size: 1 - name: MEM_CLK_EN description: UART memory clock gate enable signal. bit_offset: 28 bit_size: 1 fieldset/CONF1: description: Configuration register 1. fields: - name: RXFIFO_FULL_THRHD description: It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. bit_offset: 0 bit_size: 9 - name: TXFIFO_EMPTY_THRHD description: It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. bit_offset: 9 bit_size: 9 - name: DIS_RX_DAT_OVF description: Disable UART Rx data overflow detect. bit_offset: 18 bit_size: 1 - name: RX_TOUT_FLOW_DIS description: Set this bit to stop accumulating idle_cnt when hardware flow control works. bit_offset: 19 bit_size: 1 - name: RX_FLOW_EN description: This is the flow enable bit for UART receiver. bit_offset: 20 bit_size: 1 - name: RX_TOUT_EN description: This is the enble bit for uart receiver's timeout function. bit_offset: 21 bit_size: 1 fieldset/DATE: description: UART Version register. fields: - name: DATE description: This is the version register. bit_offset: 0 bit_size: 32 fieldset/FIFO: description: FIFO data register. fields: - name: RXFIFO_RD_BYTE description: UART 0 accesses FIFO via this register. bit_offset: 0 bit_size: 8 fieldset/FLOW_CONF: description: Software flow-control configuration. fields: - name: SW_FLOW_CON_EN description: Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. bit_offset: 0 bit_size: 1 - name: XONOFF_DEL description: Set this bit to remove flow control char from the received data. bit_offset: 1 bit_size: 1 - name: FORCE_XON description: Set this bit to enable the transmitter to go on sending data. bit_offset: 2 bit_size: 1 - name: FORCE_XOFF description: Set this bit to stop the transmitter from sending data. bit_offset: 3 bit_size: 1 - name: SEND_XON description: Set this bit to send Xon char. It is cleared by hardware automatically. bit_offset: 4 bit_size: 1 - name: SEND_XOFF description: Set this bit to send Xoff char. It is cleared by hardware automatically. bit_offset: 5 bit_size: 1 fieldset/FSM_STATUS: description: UART transmit and receive status. fields: - name: ST_URX_OUT description: This is the status register of receiver. bit_offset: 0 bit_size: 4 - name: ST_UTX_OUT description: This is the status register of transmitter. bit_offset: 4 bit_size: 4 fieldset/HIGHPULSE: description: Autobaud minimum high pulse duration register. fields: - name: MIN_CNT description: This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. bit_offset: 0 bit_size: 12 fieldset/ID: description: UART ID register. fields: - name: ID description: This register is used to configure the uart_id. bit_offset: 0 bit_size: 30 - name: HIGH_SPEED description: 'This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers.' bit_offset: 30 bit_size: 1 - name: REG_UPDATE description: Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. bit_offset: 31 bit_size: 1 fieldset/IDLE_CONF: description: Frame-end idle configuration. fields: - name: RX_IDLE_THRHD description: It will produce frame end signal when receiver takes more time to receive one byte data than this register value. bit_offset: 0 bit_size: 10 - name: TX_IDLE_NUM description: This register is used to configure the duration time between transfers. bit_offset: 10 bit_size: 10 fieldset/INT_CLR: description: Interrupt clear bits. fields: - name: RXFIFO_FULL_INT_CLR description: Set this bit to clear the rxfifo_full_int_raw interrupt. bit_offset: 0 bit_size: 1 - name: TXFIFO_EMPTY_INT_CLR description: Set this bit to clear txfifo_empty_int_raw interrupt. bit_offset: 1 bit_size: 1 - name: PARITY_ERR_INT_CLR description: Set this bit to clear parity_err_int_raw interrupt. bit_offset: 2 bit_size: 1 - name: FRM_ERR_INT_CLR description: Set this bit to clear frm_err_int_raw interrupt. bit_offset: 3 bit_size: 1 - name: RXFIFO_OVF_INT_CLR description: Set this bit to clear rxfifo_ovf_int_raw interrupt. bit_offset: 4 bit_size: 1 - name: DSR_CHG_INT_CLR description: Set this bit to clear the dsr_chg_int_raw interrupt. bit_offset: 5 bit_size: 1 - name: CTS_CHG_INT_CLR description: Set this bit to clear the cts_chg_int_raw interrupt. bit_offset: 6 bit_size: 1 - name: BRK_DET_INT_CLR description: Set this bit to clear the brk_det_int_raw interrupt. bit_offset: 7 bit_size: 1 - name: RXFIFO_TOUT_INT_CLR description: Set this bit to clear the rxfifo_tout_int_raw interrupt. bit_offset: 8 bit_size: 1 - name: SW_XON_INT_CLR description: Set this bit to clear the sw_xon_int_raw interrupt. bit_offset: 9 bit_size: 1 - name: SW_XOFF_INT_CLR description: Set this bit to clear the sw_xoff_int_raw interrupt. bit_offset: 10 bit_size: 1 - name: GLITCH_DET_INT_CLR description: Set this bit to clear the glitch_det_int_raw interrupt. bit_offset: 11 bit_size: 1 - name: TX_BRK_DONE_INT_CLR description: Set this bit to clear the tx_brk_done_int_raw interrupt.. bit_offset: 12 bit_size: 1 - name: TX_BRK_IDLE_DONE_INT_CLR description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt. bit_offset: 13 bit_size: 1 - name: TX_DONE_INT_CLR description: Set this bit to clear the tx_done_int_raw interrupt. bit_offset: 14 bit_size: 1 - name: RS485_PARITY_ERR_INT_CLR description: Set this bit to clear the rs485_parity_err_int_raw interrupt. bit_offset: 15 bit_size: 1 - name: RS485_FRM_ERR_INT_CLR description: Set this bit to clear the rs485_frm_err_int_raw interrupt. bit_offset: 16 bit_size: 1 - name: RS485_CLASH_INT_CLR description: Set this bit to clear the rs485_clash_int_raw interrupt. bit_offset: 17 bit_size: 1 - name: AT_CMD_CHAR_DET_INT_CLR description: Set this bit to clear the at_cmd_char_det_int_raw interrupt. bit_offset: 18 bit_size: 1 - name: WAKEUP_INT_CLR description: Set this bit to clear the uart_wakeup_int_raw interrupt. bit_offset: 19 bit_size: 1 fieldset/INT_ENA: description: Interrupt enable bits. fields: - name: RXFIFO_FULL_INT_ENA description: This is the enable bit for rxfifo_full_int_st register. bit_offset: 0 bit_size: 1 - name: TXFIFO_EMPTY_INT_ENA description: This is the enable bit for txfifo_empty_int_st register. bit_offset: 1 bit_size: 1 - name: PARITY_ERR_INT_ENA description: This is the enable bit for parity_err_int_st register. bit_offset: 2 bit_size: 1 - name: FRM_ERR_INT_ENA description: This is the enable bit for frm_err_int_st register. bit_offset: 3 bit_size: 1 - name: RXFIFO_OVF_INT_ENA description: This is the enable bit for rxfifo_ovf_int_st register. bit_offset: 4 bit_size: 1 - name: DSR_CHG_INT_ENA description: This is the enable bit for dsr_chg_int_st register. bit_offset: 5 bit_size: 1 - name: CTS_CHG_INT_ENA description: This is the enable bit for cts_chg_int_st register. bit_offset: 6 bit_size: 1 - name: BRK_DET_INT_ENA description: This is the enable bit for brk_det_int_st register. bit_offset: 7 bit_size: 1 - name: RXFIFO_TOUT_INT_ENA description: This is the enable bit for rxfifo_tout_int_st register. bit_offset: 8 bit_size: 1 - name: SW_XON_INT_ENA description: This is the enable bit for sw_xon_int_st register. bit_offset: 9 bit_size: 1 - name: SW_XOFF_INT_ENA description: This is the enable bit for sw_xoff_int_st register. bit_offset: 10 bit_size: 1 - name: GLITCH_DET_INT_ENA description: This is the enable bit for glitch_det_int_st register. bit_offset: 11 bit_size: 1 - name: TX_BRK_DONE_INT_ENA description: This is the enable bit for tx_brk_done_int_st register. bit_offset: 12 bit_size: 1 - name: TX_BRK_IDLE_DONE_INT_ENA description: This is the enable bit for tx_brk_idle_done_int_st register. bit_offset: 13 bit_size: 1 - name: TX_DONE_INT_ENA description: This is the enable bit for tx_done_int_st register. bit_offset: 14 bit_size: 1 - name: RS485_PARITY_ERR_INT_ENA description: This is the enable bit for rs485_parity_err_int_st register. bit_offset: 15 bit_size: 1 - name: RS485_FRM_ERR_INT_ENA description: This is the enable bit for rs485_parity_err_int_st register. bit_offset: 16 bit_size: 1 - name: RS485_CLASH_INT_ENA description: This is the enable bit for rs485_clash_int_st register. bit_offset: 17 bit_size: 1 - name: AT_CMD_CHAR_DET_INT_ENA description: This is the enable bit for at_cmd_char_det_int_st register. bit_offset: 18 bit_size: 1 - name: WAKEUP_INT_ENA description: This is the enable bit for uart_wakeup_int_st register. bit_offset: 19 bit_size: 1 fieldset/INT_RAW: description: Raw interrupt status. fields: - name: RXFIFO_FULL_INT_RAW description: This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. bit_offset: 0 bit_size: 1 - name: TXFIFO_EMPTY_INT_RAW description: This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies. bit_offset: 1 bit_size: 1 - name: PARITY_ERR_INT_RAW description: This interrupt raw bit turns to high level when receiver detects a parity error in the data. bit_offset: 2 bit_size: 1 - name: FRM_ERR_INT_RAW description: This interrupt raw bit turns to high level when receiver detects a data frame error. bit_offset: 3 bit_size: 1 - name: RXFIFO_OVF_INT_RAW description: This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. bit_offset: 4 bit_size: 1 - name: DSR_CHG_INT_RAW description: This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. bit_offset: 5 bit_size: 1 - name: CTS_CHG_INT_RAW description: This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. bit_offset: 6 bit_size: 1 - name: BRK_DET_INT_RAW description: This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. bit_offset: 7 bit_size: 1 - name: RXFIFO_TOUT_INT_RAW description: This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. bit_offset: 8 bit_size: 1 - name: SW_XON_INT_RAW description: This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. bit_offset: 9 bit_size: 1 - name: SW_XOFF_INT_RAW description: This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. bit_offset: 10 bit_size: 1 - name: GLITCH_DET_INT_RAW description: This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. bit_offset: 11 bit_size: 1 - name: TX_BRK_DONE_INT_RAW description: This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent. bit_offset: 12 bit_size: 1 - name: TX_BRK_IDLE_DONE_INT_RAW description: This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. bit_offset: 13 bit_size: 1 - name: TX_DONE_INT_RAW description: This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. bit_offset: 14 bit_size: 1 - name: RS485_PARITY_ERR_INT_RAW description: This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. bit_offset: 15 bit_size: 1 - name: RS485_FRM_ERR_INT_RAW description: This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. bit_offset: 16 bit_size: 1 - name: RS485_CLASH_INT_RAW description: This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. bit_offset: 17 bit_size: 1 - name: AT_CMD_CHAR_DET_INT_RAW description: This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. bit_offset: 18 bit_size: 1 - name: WAKEUP_INT_RAW description: This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. bit_offset: 19 bit_size: 1 fieldset/INT_ST: description: Masked interrupt status. fields: - name: RXFIFO_FULL_INT_ST description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. bit_offset: 0 bit_size: 1 - name: TXFIFO_EMPTY_INT_ST description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. bit_offset: 1 bit_size: 1 - name: PARITY_ERR_INT_ST description: This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. bit_offset: 2 bit_size: 1 - name: FRM_ERR_INT_ST description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. bit_offset: 3 bit_size: 1 - name: RXFIFO_OVF_INT_ST description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. bit_offset: 4 bit_size: 1 - name: DSR_CHG_INT_ST description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. bit_offset: 5 bit_size: 1 - name: CTS_CHG_INT_ST description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. bit_offset: 6 bit_size: 1 - name: BRK_DET_INT_ST description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. bit_offset: 7 bit_size: 1 - name: RXFIFO_TOUT_INT_ST description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. bit_offset: 8 bit_size: 1 - name: SW_XON_INT_ST description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. bit_offset: 9 bit_size: 1 - name: SW_XOFF_INT_ST description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. bit_offset: 10 bit_size: 1 - name: GLITCH_DET_INT_ST description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. bit_offset: 11 bit_size: 1 - name: TX_BRK_DONE_INT_ST description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. bit_offset: 12 bit_size: 1 - name: TX_BRK_IDLE_DONE_INT_ST description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. bit_offset: 13 bit_size: 1 - name: TX_DONE_INT_ST description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. bit_offset: 14 bit_size: 1 - name: RS485_PARITY_ERR_INT_ST description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. bit_offset: 15 bit_size: 1 - name: RS485_FRM_ERR_INT_ST description: This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. bit_offset: 16 bit_size: 1 - name: RS485_CLASH_INT_ST description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. bit_offset: 17 bit_size: 1 - name: AT_CMD_CHAR_DET_INT_ST description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. bit_offset: 18 bit_size: 1 - name: WAKEUP_INT_ST description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. bit_offset: 19 bit_size: 1 fieldset/LOWPULSE: description: Autobaud minimum low pulse duration register. fields: - name: MIN_CNT description: This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. bit_offset: 0 bit_size: 12 fieldset/MEM_CONF: description: UART threshold and allocation configuration. fields: - name: RX_SIZE description: This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes. bit_offset: 1 bit_size: 3 - name: TX_SIZE description: This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes. bit_offset: 4 bit_size: 3 - name: RX_FLOW_THRHD description: This register is used to configure the maximum amount of data that can be received when hardware flow control works. bit_offset: 7 bit_size: 9 - name: RX_TOUT_THRHD description: This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. bit_offset: 16 bit_size: 10 - name: MEM_FORCE_PD description: Set this bit to force power down UART memory. bit_offset: 26 bit_size: 1 - name: MEM_FORCE_PU description: Set this bit to force power up UART memory. bit_offset: 27 bit_size: 1 fieldset/MEM_RX_STATUS: description: Rx-FIFO write and read offset address. fields: - name: APB_RX_RADDR description: This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180. bit_offset: 0 bit_size: 10 - name: RX_WADDR description: This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180. bit_offset: 11 bit_size: 10 fieldset/MEM_TX_STATUS: description: Tx-FIFO write and read offset address. fields: - name: APB_TX_WADDR description: This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB. bit_offset: 0 bit_size: 10 - name: TX_RADDR description: This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl. bit_offset: 11 bit_size: 10 fieldset/NEGPULSE: description: Autobaud low pulse register. fields: - name: NEGEDGE_MIN_CNT description: This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. bit_offset: 0 bit_size: 12 fieldset/POSPULSE: description: Autobaud high pulse register. fields: - name: POSEDGE_MIN_CNT description: This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. bit_offset: 0 bit_size: 12 fieldset/RS485_CONF: description: RS485 mode configuration. fields: - name: RS485_EN description: Set this bit to choose the rs485 mode. bit_offset: 0 bit_size: 1 - name: DL0_EN description: Set this bit to delay the stop bit by 1 bit. bit_offset: 1 bit_size: 1 - name: DL1_EN description: Set this bit to delay the stop bit by 1 bit. bit_offset: 2 bit_size: 1 - name: RS485TX_RX_EN description: Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. bit_offset: 3 bit_size: 1 - name: RS485RXBY_TX_EN description: '1''h1: enable rs485 transmitter to send data when rs485 receiver line is busy.' bit_offset: 4 bit_size: 1 - name: RS485_RX_DLY_NUM description: This register is used to delay the receiver's internal data signal. bit_offset: 5 bit_size: 1 - name: RS485_TX_DLY_NUM description: This register is used to delay the transmitter's internal data signal. bit_offset: 6 bit_size: 4 fieldset/RXD_CNT: description: Autobaud edge change count register. fields: - name: RXD_EDGE_CNT description: This register stores the count of rxd edge change. It is used in baud rate-detect process. bit_offset: 0 bit_size: 10 fieldset/RX_FILT: description: Rx Filter configuration. fields: - name: GLITCH_FILT description: when input pulse width is lower than this value, the pulse is ignored. bit_offset: 0 bit_size: 8 - name: GLITCH_FILT_EN description: Set this bit to enable Rx signal filter. bit_offset: 8 bit_size: 1 fieldset/SLEEP_CONF: description: Sleep-mode configuration. fields: - name: ACTIVE_THRESHOLD description: The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. bit_offset: 0 bit_size: 10 fieldset/STATUS: description: UART status register. fields: - name: RXFIFO_CNT description: Stores the byte number of valid data in Rx-FIFO. bit_offset: 0 bit_size: 10 - name: DSRN description: The register represent the level value of the internal uart dsr signal. bit_offset: 13 bit_size: 1 - name: CTSN description: This register represent the level value of the internal uart cts signal. bit_offset: 14 bit_size: 1 - name: RXD description: This register represent the level value of the internal uart rxd signal. bit_offset: 15 bit_size: 1 - name: TXFIFO_CNT description: Stores the byte number of data in Tx-FIFO. bit_offset: 16 bit_size: 10 - name: DTRN description: This bit represents the level of the internal uart dtr signal. bit_offset: 29 bit_size: 1 - name: RTSN description: This bit represents the level of the internal uart rts signal. bit_offset: 30 bit_size: 1 - name: TXD description: This bit represents the level of the internal uart txd signal. bit_offset: 31 bit_size: 1 fieldset/SWFC_CONF0: description: Software flow-control character configuration. fields: - name: XOFF_THRESHOLD description: When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char. bit_offset: 0 bit_size: 9 - name: XOFF_CHAR description: This register stores the Xoff flow control char. bit_offset: 9 bit_size: 8 fieldset/SWFC_CONF1: description: Software flow-control character configuration. fields: - name: XON_THRESHOLD description: When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char. bit_offset: 0 bit_size: 9 - name: XON_CHAR description: This register stores the Xon flow control char. bit_offset: 9 bit_size: 8 fieldset/TXBRK_CONF: description: Tx Break character configuration. fields: - name: TX_BRK_NUM description: This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. bit_offset: 0 bit_size: 8