block/SPI2:
  description: SPI (Serial Peripheral Interface) Controller 2.
  items:
  - name: CMD
    description: Command control register.
    byte_offset: 0
    fieldset: CMD
  - name: ADDR
    description: Address value register.
    byte_offset: 4
    fieldset: ADDR
  - name: CTRL
    description: SPI control register.
    byte_offset: 8
    fieldset: CTRL
  - name: CLOCK
    description: SPI clock control register.
    byte_offset: 12
    fieldset: CLOCK
  - name: USER
    description: SPI USER control register.
    byte_offset: 16
    fieldset: USER
  - name: USER1
    description: SPI USER control register 1.
    byte_offset: 20
    fieldset: USER1
  - name: USER2
    description: SPI USER control register 2.
    byte_offset: 24
    fieldset: USER2
  - name: MS_DLEN
    description: SPI data bit length control register.
    byte_offset: 28
    fieldset: MS_DLEN
  - name: MISC
    description: SPI misc register.
    byte_offset: 32
    fieldset: MISC
  - name: DIN_MODE
    description: SPI input delay mode configuration.
    byte_offset: 36
    fieldset: DIN_MODE
  - name: DIN_NUM
    description: SPI input delay number configuration.
    byte_offset: 40
    fieldset: DIN_NUM
  - name: DOUT_MODE
    description: SPI output delay mode configuration.
    byte_offset: 44
    fieldset: DOUT_MODE
  - name: DMA_CONF
    description: SPI DMA control register.
    byte_offset: 48
    fieldset: DMA_CONF
  - name: DMA_INT_ENA
    description: SPI DMA interrupt enable register.
    byte_offset: 52
    fieldset: DMA_INT_ENA
  - name: DMA_INT_CLR
    description: SPI DMA interrupt clear register.
    byte_offset: 56
    fieldset: DMA_INT_CLR
  - name: DMA_INT_RAW
    description: SPI DMA interrupt raw register.
    byte_offset: 60
    fieldset: DMA_INT_RAW
  - name: DMA_INT_ST
    description: SPI DMA interrupt status register.
    byte_offset: 64
    fieldset: DMA_INT_ST
  - name: W0
    description: SPI CPU-controlled buffer0.
    byte_offset: 152
    fieldset: W0
  - name: W1
    description: SPI CPU-controlled buffer1.
    byte_offset: 156
    fieldset: W1
  - name: W2
    description: SPI CPU-controlled buffer2.
    byte_offset: 160
    fieldset: W2
  - name: W3
    description: SPI CPU-controlled buffer3.
    byte_offset: 164
    fieldset: W3
  - name: W4
    description: SPI CPU-controlled buffer4.
    byte_offset: 168
    fieldset: W4
  - name: W5
    description: SPI CPU-controlled buffer5.
    byte_offset: 172
    fieldset: W5
  - name: W6
    description: SPI CPU-controlled buffer6.
    byte_offset: 176
    fieldset: W6
  - name: W7
    description: SPI CPU-controlled buffer7.
    byte_offset: 180
    fieldset: W7
  - name: W8
    description: SPI CPU-controlled buffer8.
    byte_offset: 184
    fieldset: W8
  - name: W9
    description: SPI CPU-controlled buffer9.
    byte_offset: 188
    fieldset: W9
  - name: W10
    description: SPI CPU-controlled buffer10.
    byte_offset: 192
    fieldset: W10
  - name: W11
    description: SPI CPU-controlled buffer11.
    byte_offset: 196
    fieldset: W11
  - name: W12
    description: SPI CPU-controlled buffer12.
    byte_offset: 200
    fieldset: W12
  - name: W13
    description: SPI CPU-controlled buffer13.
    byte_offset: 204
    fieldset: W13
  - name: W14
    description: SPI CPU-controlled buffer14.
    byte_offset: 208
    fieldset: W14
  - name: W15
    description: SPI CPU-controlled buffer15.
    byte_offset: 212
    fieldset: W15
  - name: SLAVE
    description: SPI slave control register.
    byte_offset: 224
    fieldset: SLAVE
  - name: SLAVE1
    description: SPI slave control register 1.
    byte_offset: 228
    fieldset: SLAVE1
  - name: CLK_GATE
    description: SPI module clock and register clock control.
    byte_offset: 232
    fieldset: CLK_GATE
  - name: DATE
    description: Version control.
    byte_offset: 240
    fieldset: DATE
fieldset/ADDR:
  description: Address value register.
  fields:
  - name: USR_ADDR_VALUE
    description: Address to slave. Can be configured in CONF state.
    bit_offset: 0
    bit_size: 32
fieldset/CLK_GATE:
  description: SPI module clock and register clock control.
  fields:
  - name: CLK_EN
    description: Set this bit to enable clk gate.
    bit_offset: 0
    bit_size: 1
  - name: MST_CLK_ACTIVE
    description: Set this bit to power on the SPI module clock.
    bit_offset: 1
    bit_size: 1
  - name: MST_CLK_SEL
    description: 'This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.'
    bit_offset: 2
    bit_size: 1
fieldset/CLOCK:
  description: SPI clock control register.
  fields:
  - name: CLKCNT_L
    description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.
    bit_offset: 0
    bit_size: 6
  - name: CLKCNT_H
    description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.
    bit_offset: 6
    bit_size: 6
  - name: CLKCNT_N
    description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
    bit_offset: 12
    bit_size: 6
  - name: CLKDIV_PRE
    description: In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.
    bit_offset: 18
    bit_size: 4
  - name: CLK_EQU_SYSCLK
    description: 'In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.'
    bit_offset: 31
    bit_size: 1
fieldset/CMD:
  description: Command control register.
  fields:
  - name: CONF_BITLEN
    description: Define the APB cycles of SPI_CONF state. Can be configured in CONF state.
    bit_offset: 0
    bit_size: 18
  - name: UPDATE
    description: Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.
    bit_offset: 23
    bit_size: 1
  - name: USR
    description: 'User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.'
    bit_offset: 24
    bit_size: 1
fieldset/CTRL:
  description: SPI control register.
  fields:
  - name: DUMMY_OUT
    description: In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.
    bit_offset: 3
    bit_size: 1
  - name: FADDR_DUAL
    description: 'Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.'
    bit_offset: 5
    bit_size: 1
  - name: FADDR_QUAD
    description: 'Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.'
    bit_offset: 6
    bit_size: 1
  - name: FCMD_DUAL
    description: 'Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.'
    bit_offset: 8
    bit_size: 1
  - name: FCMD_QUAD
    description: 'Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.'
    bit_offset: 9
    bit_size: 1
  - name: FREAD_DUAL
    description: 'In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.'
    bit_offset: 14
    bit_size: 1
  - name: FREAD_QUAD
    description: 'In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.'
    bit_offset: 15
    bit_size: 1
  - name: Q_POL
    description: 'The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.'
    bit_offset: 18
    bit_size: 1
  - name: D_POL
    description: 'The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.'
    bit_offset: 19
    bit_size: 1
  - name: HOLD_POL
    description: 'SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.'
    bit_offset: 20
    bit_size: 1
  - name: WP_POL
    description: 'Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.'
    bit_offset: 21
    bit_size: 1
  - name: RD_BIT_ORDER
    description: 'In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.'
    bit_offset: 25
    bit_size: 1
  - name: WR_BIT_ORDER
    description: 'In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.'
    bit_offset: 26
    bit_size: 1
fieldset/DATE:
  description: Version control.
  fields:
  - name: DATE
    description: SPI register version.
    bit_offset: 0
    bit_size: 28
fieldset/DIN_MODE:
  description: SPI input delay mode configuration.
  fields:
  - name: DIN0_MODE
    description: 'the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.'
    bit_offset: 0
    bit_size: 2
  - name: DIN1_MODE
    description: 'the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.'
    bit_offset: 2
    bit_size: 2
  - name: DIN2_MODE
    description: 'the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.'
    bit_offset: 4
    bit_size: 2
  - name: DIN3_MODE
    description: 'the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.'
    bit_offset: 6
    bit_size: 2
  - name: TIMING_HCLK_ACTIVE
    description: '1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.'
    bit_offset: 16
    bit_size: 1
fieldset/DIN_NUM:
  description: SPI input delay number configuration.
  fields:
  - name: DIN0_NUM
    description: 'the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.'
    bit_offset: 0
    bit_size: 2
  - name: DIN1_NUM
    description: 'the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.'
    bit_offset: 2
    bit_size: 2
  - name: DIN2_NUM
    description: 'the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.'
    bit_offset: 4
    bit_size: 2
  - name: DIN3_NUM
    description: 'the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.'
    bit_offset: 6
    bit_size: 2
fieldset/DMA_CONF:
  description: SPI DMA control register.
  fields:
  - name: DMA_SLV_SEG_TRANS_EN
    description: 'Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.'
    bit_offset: 18
    bit_size: 1
  - name: SLV_RX_SEG_TRANS_CLR_EN
    description: '1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.'
    bit_offset: 19
    bit_size: 1
  - name: SLV_TX_SEG_TRANS_CLR_EN
    description: '1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.'
    bit_offset: 20
    bit_size: 1
  - name: RX_EOF_EN
    description: '1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.'
    bit_offset: 21
    bit_size: 1
  - name: DMA_RX_ENA
    description: Set this bit to enable SPI DMA controlled receive data mode.
    bit_offset: 27
    bit_size: 1
  - name: DMA_TX_ENA
    description: Set this bit to enable SPI DMA controlled send data mode.
    bit_offset: 28
    bit_size: 1
  - name: RX_AFIFO_RST
    description: Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.
    bit_offset: 29
    bit_size: 1
  - name: BUF_AFIFO_RST
    description: Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.
    bit_offset: 30
    bit_size: 1
  - name: DMA_AFIFO_RST
    description: Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.
    bit_offset: 31
    bit_size: 1
fieldset/DMA_INT_CLR:
  description: SPI DMA interrupt clear register.
  fields:
  - name: DMA_INFIFO_FULL_ERR_INT_CLR
    description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
    bit_offset: 0
    bit_size: 1
  - name: DMA_OUTFIFO_EMPTY_ERR_INT_CLR
    description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
    bit_offset: 1
    bit_size: 1
  - name: SLV_EX_QPI_INT_CLR
    description: The clear bit for SPI slave Ex_QPI interrupt.
    bit_offset: 2
    bit_size: 1
  - name: SLV_EN_QPI_INT_CLR
    description: The clear bit for SPI slave En_QPI interrupt.
    bit_offset: 3
    bit_size: 1
  - name: SLV_CMD7_INT_CLR
    description: The clear bit for SPI slave CMD7 interrupt.
    bit_offset: 4
    bit_size: 1
  - name: SLV_CMD8_INT_CLR
    description: The clear bit for SPI slave CMD8 interrupt.
    bit_offset: 5
    bit_size: 1
  - name: SLV_CMD9_INT_CLR
    description: The clear bit for SPI slave CMD9 interrupt.
    bit_offset: 6
    bit_size: 1
  - name: SLV_CMDA_INT_CLR
    description: The clear bit for SPI slave CMDA interrupt.
    bit_offset: 7
    bit_size: 1
  - name: SLV_RD_DMA_DONE_INT_CLR
    description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
    bit_offset: 8
    bit_size: 1
  - name: SLV_WR_DMA_DONE_INT_CLR
    description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
    bit_offset: 9
    bit_size: 1
  - name: SLV_RD_BUF_DONE_INT_CLR
    description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
    bit_offset: 10
    bit_size: 1
  - name: SLV_WR_BUF_DONE_INT_CLR
    description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
    bit_offset: 11
    bit_size: 1
  - name: TRANS_DONE_INT_CLR
    description: The clear bit for SPI_TRANS_DONE_INT interrupt.
    bit_offset: 12
    bit_size: 1
  - name: DMA_SEG_TRANS_DONE_INT_CLR
    description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
    bit_offset: 13
    bit_size: 1
  - name: SEG_MAGIC_ERR_INT_CLR
    description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
    bit_offset: 14
    bit_size: 1
  - name: SLV_BUF_ADDR_ERR_INT_CLR
    description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
    bit_offset: 15
    bit_size: 1
  - name: SLV_CMD_ERR_INT_CLR
    description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
    bit_offset: 16
    bit_size: 1
  - name: MST_RX_AFIFO_WFULL_ERR_INT_CLR
    description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
    bit_offset: 17
    bit_size: 1
  - name: MST_TX_AFIFO_REMPTY_ERR_INT_CLR
    description: The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
    bit_offset: 18
    bit_size: 1
  - name: APP2_INT_CLR
    description: The clear bit for SPI_APP2_INT interrupt.
    bit_offset: 19
    bit_size: 1
  - name: APP1_INT_CLR
    description: The clear bit for SPI_APP1_INT interrupt.
    bit_offset: 20
    bit_size: 1
fieldset/DMA_INT_ENA:
  description: SPI DMA interrupt enable register.
  fields:
  - name: DMA_INFIFO_FULL_ERR_INT_ENA
    description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
    bit_offset: 0
    bit_size: 1
  - name: DMA_OUTFIFO_EMPTY_ERR_INT_ENA
    description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
    bit_offset: 1
    bit_size: 1
  - name: SLV_EX_QPI_INT_ENA
    description: The enable bit for SPI slave Ex_QPI interrupt.
    bit_offset: 2
    bit_size: 1
  - name: SLV_EN_QPI_INT_ENA
    description: The enable bit for SPI slave En_QPI interrupt.
    bit_offset: 3
    bit_size: 1
  - name: SLV_CMD7_INT_ENA
    description: The enable bit for SPI slave CMD7 interrupt.
    bit_offset: 4
    bit_size: 1
  - name: SLV_CMD8_INT_ENA
    description: The enable bit for SPI slave CMD8 interrupt.
    bit_offset: 5
    bit_size: 1
  - name: SLV_CMD9_INT_ENA
    description: The enable bit for SPI slave CMD9 interrupt.
    bit_offset: 6
    bit_size: 1
  - name: SLV_CMDA_INT_ENA
    description: The enable bit for SPI slave CMDA interrupt.
    bit_offset: 7
    bit_size: 1
  - name: SLV_RD_DMA_DONE_INT_ENA
    description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
    bit_offset: 8
    bit_size: 1
  - name: SLV_WR_DMA_DONE_INT_ENA
    description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
    bit_offset: 9
    bit_size: 1
  - name: SLV_RD_BUF_DONE_INT_ENA
    description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
    bit_offset: 10
    bit_size: 1
  - name: SLV_WR_BUF_DONE_INT_ENA
    description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
    bit_offset: 11
    bit_size: 1
  - name: TRANS_DONE_INT_ENA
    description: The enable bit for SPI_TRANS_DONE_INT interrupt.
    bit_offset: 12
    bit_size: 1
  - name: DMA_SEG_TRANS_DONE_INT_ENA
    description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
    bit_offset: 13
    bit_size: 1
  - name: SEG_MAGIC_ERR_INT_ENA
    description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
    bit_offset: 14
    bit_size: 1
  - name: SLV_BUF_ADDR_ERR_INT_ENA
    description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
    bit_offset: 15
    bit_size: 1
  - name: SLV_CMD_ERR_INT_ENA
    description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
    bit_offset: 16
    bit_size: 1
  - name: MST_RX_AFIFO_WFULL_ERR_INT_ENA
    description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
    bit_offset: 17
    bit_size: 1
  - name: MST_TX_AFIFO_REMPTY_ERR_INT_ENA
    description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
    bit_offset: 18
    bit_size: 1
  - name: APP2_INT_ENA
    description: The enable bit for SPI_APP2_INT interrupt.
    bit_offset: 19
    bit_size: 1
  - name: APP1_INT_ENA
    description: The enable bit for SPI_APP1_INT interrupt.
    bit_offset: 20
    bit_size: 1
fieldset/DMA_INT_RAW:
  description: SPI DMA interrupt raw register.
  fields:
  - name: DMA_INFIFO_FULL_ERR_INT_RAW
    description: '1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others.'
    bit_offset: 0
    bit_size: 1
  - name: DMA_OUTFIFO_EMPTY_ERR_INT_RAW
    description: '1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others.'
    bit_offset: 1
    bit_size: 1
  - name: SLV_EX_QPI_INT_RAW
    description: 'The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.'
    bit_offset: 2
    bit_size: 1
  - name: SLV_EN_QPI_INT_RAW
    description: 'The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.'
    bit_offset: 3
    bit_size: 1
  - name: SLV_CMD7_INT_RAW
    description: 'The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.'
    bit_offset: 4
    bit_size: 1
  - name: SLV_CMD8_INT_RAW
    description: 'The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.'
    bit_offset: 5
    bit_size: 1
  - name: SLV_CMD9_INT_RAW
    description: 'The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.'
    bit_offset: 6
    bit_size: 1
  - name: SLV_CMDA_INT_RAW
    description: 'The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.'
    bit_offset: 7
    bit_size: 1
  - name: SLV_RD_DMA_DONE_INT_RAW
    description: 'The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.'
    bit_offset: 8
    bit_size: 1
  - name: SLV_WR_DMA_DONE_INT_RAW
    description: 'The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.'
    bit_offset: 9
    bit_size: 1
  - name: SLV_RD_BUF_DONE_INT_RAW
    description: 'The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.'
    bit_offset: 10
    bit_size: 1
  - name: SLV_WR_BUF_DONE_INT_RAW
    description: 'The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.'
    bit_offset: 11
    bit_size: 1
  - name: TRANS_DONE_INT_RAW
    description: 'The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.'
    bit_offset: 12
    bit_size: 1
  - name: DMA_SEG_TRANS_DONE_INT_RAW
    description: 'The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred.'
    bit_offset: 13
    bit_size: 1
  - name: SEG_MAGIC_ERR_INT_RAW
    description: 'The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.'
    bit_offset: 14
    bit_size: 1
  - name: SLV_BUF_ADDR_ERR_INT_RAW
    description: 'The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.'
    bit_offset: 15
    bit_size: 1
  - name: SLV_CMD_ERR_INT_RAW
    description: 'The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.'
    bit_offset: 16
    bit_size: 1
  - name: MST_RX_AFIFO_WFULL_ERR_INT_RAW
    description: 'The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.'
    bit_offset: 17
    bit_size: 1
  - name: MST_TX_AFIFO_REMPTY_ERR_INT_RAW
    description: 'The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.'
    bit_offset: 18
    bit_size: 1
  - name: APP2_INT_RAW
    description: The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.
    bit_offset: 19
    bit_size: 1
  - name: APP1_INT_RAW
    description: The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.
    bit_offset: 20
    bit_size: 1
fieldset/DMA_INT_ST:
  description: SPI DMA interrupt status register.
  fields:
  - name: DMA_INFIFO_FULL_ERR_INT_ST
    description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
    bit_offset: 0
    bit_size: 1
  - name: DMA_OUTFIFO_EMPTY_ERR_INT_ST
    description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
    bit_offset: 1
    bit_size: 1
  - name: SLV_EX_QPI_INT_ST
    description: The status bit for SPI slave Ex_QPI interrupt.
    bit_offset: 2
    bit_size: 1
  - name: SLV_EN_QPI_INT_ST
    description: The status bit for SPI slave En_QPI interrupt.
    bit_offset: 3
    bit_size: 1
  - name: SLV_CMD7_INT_ST
    description: The status bit for SPI slave CMD7 interrupt.
    bit_offset: 4
    bit_size: 1
  - name: SLV_CMD8_INT_ST
    description: The status bit for SPI slave CMD8 interrupt.
    bit_offset: 5
    bit_size: 1
  - name: SLV_CMD9_INT_ST
    description: The status bit for SPI slave CMD9 interrupt.
    bit_offset: 6
    bit_size: 1
  - name: SLV_CMDA_INT_ST
    description: The status bit for SPI slave CMDA interrupt.
    bit_offset: 7
    bit_size: 1
  - name: SLV_RD_DMA_DONE_INT_ST
    description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
    bit_offset: 8
    bit_size: 1
  - name: SLV_WR_DMA_DONE_INT_ST
    description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
    bit_offset: 9
    bit_size: 1
  - name: SLV_RD_BUF_DONE_INT_ST
    description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
    bit_offset: 10
    bit_size: 1
  - name: SLV_WR_BUF_DONE_INT_ST
    description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
    bit_offset: 11
    bit_size: 1
  - name: TRANS_DONE_INT_ST
    description: The status bit for SPI_TRANS_DONE_INT interrupt.
    bit_offset: 12
    bit_size: 1
  - name: DMA_SEG_TRANS_DONE_INT_ST
    description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
    bit_offset: 13
    bit_size: 1
  - name: SEG_MAGIC_ERR_INT_ST
    description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
    bit_offset: 14
    bit_size: 1
  - name: SLV_BUF_ADDR_ERR_INT_ST
    description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
    bit_offset: 15
    bit_size: 1
  - name: SLV_CMD_ERR_INT_ST
    description: The status bit for SPI_SLV_CMD_ERR_INT interrupt.
    bit_offset: 16
    bit_size: 1
  - name: MST_RX_AFIFO_WFULL_ERR_INT_ST
    description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
    bit_offset: 17
    bit_size: 1
  - name: MST_TX_AFIFO_REMPTY_ERR_INT_ST
    description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
    bit_offset: 18
    bit_size: 1
  - name: APP2_INT_ST
    description: The status bit for SPI_APP2_INT interrupt.
    bit_offset: 19
    bit_size: 1
  - name: APP1_INT_ST
    description: The status bit for SPI_APP1_INT interrupt.
    bit_offset: 20
    bit_size: 1
fieldset/DOUT_MODE:
  description: SPI output delay mode configuration.
  fields:
  - name: DOUT0_MODE
    description: 'The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.'
    bit_offset: 0
    bit_size: 1
  - name: DOUT1_MODE
    description: 'The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.'
    bit_offset: 1
    bit_size: 1
  - name: DOUT2_MODE
    description: 'The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.'
    bit_offset: 2
    bit_size: 1
  - name: DOUT3_MODE
    description: 'The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.'
    bit_offset: 3
    bit_size: 1
fieldset/MISC:
  description: SPI misc register.
  fields:
  - name: CS0_DIS
    description: 'SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.'
    bit_offset: 0
    bit_size: 1
  - name: CS1_DIS
    description: 'SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.'
    bit_offset: 1
    bit_size: 1
  - name: CS2_DIS
    description: 'SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.'
    bit_offset: 2
    bit_size: 1
  - name: CS3_DIS
    description: 'SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.'
    bit_offset: 3
    bit_size: 1
  - name: CS4_DIS
    description: 'SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.'
    bit_offset: 4
    bit_size: 1
  - name: CS5_DIS
    description: 'SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.'
    bit_offset: 5
    bit_size: 1
  - name: CK_DIS
    description: '1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.'
    bit_offset: 6
    bit_size: 1
  - name: MASTER_CS_POL
    description: In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
    bit_offset: 7
    bit_size: 6
  - name: SLAVE_CS_POL
    description: 'spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.'
    bit_offset: 23
    bit_size: 1
  - name: CK_IDLE_EDGE
    description: '1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.'
    bit_offset: 29
    bit_size: 1
  - name: CS_KEEP_ACTIVE
    description: spi cs line keep low when the bit is set. Can be configured in CONF state.
    bit_offset: 30
    bit_size: 1
  - name: QUAD_DIN_PIN_SWAP
    description: '1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state.'
    bit_offset: 31
    bit_size: 1
fieldset/MS_DLEN:
  description: SPI data bit length control register.
  fields:
  - name: MS_DATA_BITLEN
    description: The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.
    bit_offset: 0
    bit_size: 18
fieldset/SLAVE:
  description: SPI slave control register.
  fields:
  - name: CLK_MODE
    description: 'SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.'
    bit_offset: 0
    bit_size: 2
  - name: CLK_MODE_13
    description: '{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].'
    bit_offset: 2
    bit_size: 1
  - name: RSCK_DATA_OUT
    description: 'It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge.'
    bit_offset: 3
    bit_size: 1
  - name: SLV_RDDMA_BITLEN_EN
    description: '1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others.'
    bit_offset: 8
    bit_size: 1
  - name: SLV_WRDMA_BITLEN_EN
    description: '1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others.'
    bit_offset: 9
    bit_size: 1
  - name: SLV_RDBUF_BITLEN_EN
    description: '1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others.'
    bit_offset: 10
    bit_size: 1
  - name: SLV_WRBUF_BITLEN_EN
    description: '1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others.'
    bit_offset: 11
    bit_size: 1
  - name: DMA_SEG_MAGIC_VALUE
    description: The magic value of BM table in master DMA seg-trans.
    bit_offset: 22
    bit_size: 4
  - name: MODE
    description: 'Set SPI work mode. 1: slave mode 0: master mode.'
    bit_offset: 26
    bit_size: 1
  - name: SOFT_RESET
    description: Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.
    bit_offset: 27
    bit_size: 1
  - name: USR_CONF
    description: '1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.'
    bit_offset: 28
    bit_size: 1
fieldset/SLAVE1:
  description: SPI slave control register 1.
  fields:
  - name: SLV_DATA_BITLEN
    description: The transferred data bit length in SPI slave FD and HD mode.
    bit_offset: 0
    bit_size: 18
  - name: SLV_LAST_COMMAND
    description: In the slave mode it is the value of command.
    bit_offset: 18
    bit_size: 8
  - name: SLV_LAST_ADDR
    description: In the slave mode it is the value of address.
    bit_offset: 26
    bit_size: 6
fieldset/USER:
  description: SPI USER control register.
  fields:
  - name: DOUTDIN
    description: 'Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.'
    bit_offset: 0
    bit_size: 1
  - name: QPI_MODE
    description: 'Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.'
    bit_offset: 3
    bit_size: 1
  - name: TSCK_I_EDGE
    description: 'In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.'
    bit_offset: 5
    bit_size: 1
  - name: CS_HOLD
    description: 'spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.'
    bit_offset: 6
    bit_size: 1
  - name: CS_SETUP
    description: 'spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.'
    bit_offset: 7
    bit_size: 1
  - name: RSCK_I_EDGE
    description: 'In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.'
    bit_offset: 8
    bit_size: 1
  - name: CK_OUT_EDGE
    description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.
    bit_offset: 9
    bit_size: 1
  - name: FWRITE_DUAL
    description: In the write operations read-data phase apply 2 signals. Can be configured in CONF state.
    bit_offset: 12
    bit_size: 1
  - name: FWRITE_QUAD
    description: In the write operations read-data phase apply 4 signals. Can be configured in CONF state.
    bit_offset: 13
    bit_size: 1
  - name: USR_CONF_NXT
    description: '1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.'
    bit_offset: 15
    bit_size: 1
  - name: SIO
    description: 'Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.'
    bit_offset: 17
    bit_size: 1
  - name: USR_MISO_HIGHPART
    description: 'read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.'
    bit_offset: 24
    bit_size: 1
  - name: USR_MOSI_HIGHPART
    description: 'write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.'
    bit_offset: 25
    bit_size: 1
  - name: USR_DUMMY_IDLE
    description: spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.
    bit_offset: 26
    bit_size: 1
  - name: USR_MOSI
    description: This bit enable the write-data phase of an operation. Can be configured in CONF state.
    bit_offset: 27
    bit_size: 1
  - name: USR_MISO
    description: This bit enable the read-data phase of an operation. Can be configured in CONF state.
    bit_offset: 28
    bit_size: 1
  - name: USR_DUMMY
    description: This bit enable the dummy phase of an operation. Can be configured in CONF state.
    bit_offset: 29
    bit_size: 1
  - name: USR_ADDR
    description: This bit enable the address phase of an operation. Can be configured in CONF state.
    bit_offset: 30
    bit_size: 1
  - name: USR_COMMAND
    description: This bit enable the command phase of an operation. Can be configured in CONF state.
    bit_offset: 31
    bit_size: 1
fieldset/USER1:
  description: SPI USER control register 1.
  fields:
  - name: USR_DUMMY_CYCLELEN
    description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.
    bit_offset: 0
    bit_size: 8
  - name: MST_WFULL_ERR_END_EN
    description: '1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.'
    bit_offset: 16
    bit_size: 1
  - name: CS_SETUP_TIME
    description: (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.
    bit_offset: 17
    bit_size: 5
  - name: CS_HOLD_TIME
    description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.
    bit_offset: 22
    bit_size: 5
  - name: USR_ADDR_BITLEN
    description: The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.
    bit_offset: 27
    bit_size: 5
fieldset/USER2:
  description: SPI USER control register 2.
  fields:
  - name: USR_COMMAND_VALUE
    description: The value of command. Can be configured in CONF state.
    bit_offset: 0
    bit_size: 16
  - name: MST_REMPTY_ERR_END_EN
    description: '1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.'
    bit_offset: 27
    bit_size: 1
  - name: USR_COMMAND_BITLEN
    description: The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.
    bit_offset: 28
    bit_size: 4
fieldset/W0:
  description: SPI CPU-controlled buffer0.
  fields:
  - name: BUF0
    description: data buffer.
    bit_offset: 0
    bit_size: 32
fieldset/W1:
  description: SPI CPU-controlled buffer1.
  fields:
  - name: BUF1
    description: data buffer.
    bit_offset: 0
    bit_size: 32
fieldset/W10:
  description: SPI CPU-controlled buffer10.
  fields:
  - name: BUF10
    description: data buffer.
    bit_offset: 0
    bit_size: 32
fieldset/W11:
  description: SPI CPU-controlled buffer11.
  fields:
  - name: BUF11
    description: data buffer.
    bit_offset: 0
    bit_size: 32
fieldset/W12:
  description: SPI CPU-controlled buffer12.
  fields:
  - name: BUF12
    description: data buffer.
    bit_offset: 0
    bit_size: 32
fieldset/W13:
  description: SPI CPU-controlled buffer13.
  fields:
  - name: BUF13
    description: data buffer.
    bit_offset: 0
    bit_size: 32
fieldset/W14:
  description: SPI CPU-controlled buffer14.
  fields:
  - name: BUF14
    description: data buffer.
    bit_offset: 0
    bit_size: 32
fieldset/W15:
  description: SPI CPU-controlled buffer15.
  fields:
  - name: BUF15
    description: data buffer.
    bit_offset: 0
    bit_size: 32
fieldset/W2:
  description: SPI CPU-controlled buffer2.
  fields:
  - name: BUF2
    description: data buffer.
    bit_offset: 0
    bit_size: 32
fieldset/W3:
  description: SPI CPU-controlled buffer3.
  fields:
  - name: BUF3
    description: data buffer.
    bit_offset: 0
    bit_size: 32
fieldset/W4:
  description: SPI CPU-controlled buffer4.
  fields:
  - name: BUF4
    description: data buffer.
    bit_offset: 0
    bit_size: 32
fieldset/W5:
  description: SPI CPU-controlled buffer5.
  fields:
  - name: BUF5
    description: data buffer.
    bit_offset: 0
    bit_size: 32
fieldset/W6:
  description: SPI CPU-controlled buffer6.
  fields:
  - name: BUF6
    description: data buffer.
    bit_offset: 0
    bit_size: 32
fieldset/W7:
  description: SPI CPU-controlled buffer7.
  fields:
  - name: BUF7
    description: data buffer.
    bit_offset: 0
    bit_size: 32
fieldset/W8:
  description: SPI CPU-controlled buffer8.
  fields:
  - name: BUF8
    description: data buffer.
    bit_offset: 0
    bit_size: 32
fieldset/W9:
  description: SPI CPU-controlled buffer9.
  fields:
  - name: BUF9
    description: data buffer.
    bit_offset: 0
    bit_size: 32