block/SPI0:
  description: SPI (Serial Peripheral Interface) Controller 0.
  items:
  - name: CTRL
    description: SPI0 control register.
    byte_offset: 8
    fieldset: CTRL
  - name: CTRL1
    description: SPI0 control1 register.
    byte_offset: 12
    fieldset: CTRL1
  - name: CTRL2
    description: SPI0 control2 register.
    byte_offset: 16
    fieldset: CTRL2
  - name: CLOCK
    description: SPI clock division control register.
    byte_offset: 20
    fieldset: CLOCK
  - name: USER
    description: SPI0 user register.
    byte_offset: 24
    fieldset: USER
  - name: USER1
    description: SPI0 user1 register.
    byte_offset: 28
    fieldset: USER1
  - name: USER2
    description: SPI0 user2 register.
    byte_offset: 32
    fieldset: USER2
  - name: RD_STATUS
    description: SPI0 read control register.
    byte_offset: 44
    fieldset: RD_STATUS
  - name: MISC
    description: SPI0 misc register.
    byte_offset: 52
    fieldset: MISC
  - name: CACHE_FCTRL
    description: SPI0 bit mode control register.
    byte_offset: 60
    fieldset: CACHE_FCTRL
  - name: FSM
    description: SPI0 FSM status register.
    byte_offset: 84
    fieldset: FSM
  - name: TIMING_CALI
    description: SPI0 timing calibration register.
    byte_offset: 168
    fieldset: TIMING_CALI
  - name: DIN_MODE
    description: SPI0 input delay mode control register.
    byte_offset: 172
    fieldset: DIN_MODE
  - name: DIN_NUM
    description: SPI0 input delay number control register.
    byte_offset: 176
    fieldset: DIN_NUM
  - name: DOUT_MODE
    description: SPI0 output delay mode control register.
    byte_offset: 180
    fieldset: DOUT_MODE
  - name: CLOCK_GATE
    description: SPI0 clk_gate register.
    byte_offset: 220
    fieldset: CLOCK_GATE
  - name: CORE_CLK_SEL
    description: SPI0 module clock select register.
    byte_offset: 224
    fieldset: CORE_CLK_SEL
  - name: DATE
    description: Version control register.
    byte_offset: 1020
    fieldset: DATE
fieldset/CACHE_FCTRL:
  description: SPI0 bit mode control register.
  fields:
  - name: CACHE_REQ_EN
    description: 'For SPI0, Cache access enable, 1: enable, 0:disable.'
    bit_offset: 0
    bit_size: 1
  - name: CACHE_USR_ADDR_4BYTE
    description: 'For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.'
    bit_offset: 1
    bit_size: 1
  - name: CACHE_FLASH_USR_CMD
    description: 'For SPI0, cache read flash for user define command, 1: enable, 0:disable.'
    bit_offset: 2
    bit_size: 1
  - name: FDIN_DUAL
    description: 'For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.'
    bit_offset: 3
    bit_size: 1
  - name: FDOUT_DUAL
    description: 'For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.'
    bit_offset: 4
    bit_size: 1
  - name: FADDR_DUAL
    description: 'For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.'
    bit_offset: 5
    bit_size: 1
  - name: FDIN_QUAD
    description: 'For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.'
    bit_offset: 6
    bit_size: 1
  - name: FDOUT_QUAD
    description: 'For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.'
    bit_offset: 7
    bit_size: 1
  - name: FADDR_QUAD
    description: 'For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.'
    bit_offset: 8
    bit_size: 1
fieldset/CLOCK:
  description: SPI clock division control register.
  fields:
  - name: CLKCNT_L
    description: In the master mode it must be equal to spi_mem_clkcnt_N.
    bit_offset: 0
    bit_size: 8
  - name: CLKCNT_H
    description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
    bit_offset: 8
    bit_size: 8
  - name: CLKCNT_N
    description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1).
    bit_offset: 16
    bit_size: 8
  - name: CLK_EQU_SYSCLK
    description: Set this bit in 1-division mode.
    bit_offset: 31
    bit_size: 1
fieldset/CLOCK_GATE:
  description: SPI0 clk_gate register.
  fields:
  - name: CLK_EN
    description: 'Register clock gate enable signal. 1: Enable. 0: Disable.'
    bit_offset: 0
    bit_size: 1
fieldset/CORE_CLK_SEL:
  description: SPI0 module clock select register.
  fields:
  - name: SPI01_CLK_SEL
    description: 'When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.'
    bit_offset: 0
    bit_size: 2
fieldset/CTRL:
  description: SPI0 control register.
  fields:
  - name: FDUMMY_OUT
    description: In the dummy phase the signal level of spi is output by the spi controller.
    bit_offset: 3
    bit_size: 1
  - name: FCMD_DUAL
    description: 'Apply 2 signals during command phase 1:enable 0: disable.'
    bit_offset: 7
    bit_size: 1
  - name: FCMD_QUAD
    description: 'Apply 4 signals during command phase 1:enable 0: disable.'
    bit_offset: 8
    bit_size: 1
  - name: FASTRD_MODE
    description: 'This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.'
    bit_offset: 13
    bit_size: 1
  - name: FREAD_DUAL
    description: 'In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.'
    bit_offset: 14
    bit_size: 1
  - name: Q_POL
    description: 'The bit is used to set MISO line polarity, 1: high 0, low.'
    bit_offset: 18
    bit_size: 1
  - name: D_POL
    description: 'The bit is used to set MOSI line polarity, 1: high 0, low.'
    bit_offset: 19
    bit_size: 1
  - name: FREAD_QUAD
    description: 'In the read operations read-data phase apply 4 signals. 1: enable 0: disable.'
    bit_offset: 20
    bit_size: 1
  - name: WP
    description: 'Write protect signal output when SPI is idle. 1: output high, 0: output low.'
    bit_offset: 21
    bit_size: 1
  - name: FREAD_DIO
    description: 'In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.'
    bit_offset: 23
    bit_size: 1
  - name: FREAD_QIO
    description: 'In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.'
    bit_offset: 24
    bit_size: 1
fieldset/CTRL1:
  description: SPI0 control1 register.
  fields:
  - name: CLK_MODE
    description: 'SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.'
    bit_offset: 0
    bit_size: 2
  - name: RXFIFO_RST
    description: SPI0 RX FIFO reset signal.
    bit_offset: 30
    bit_size: 1
fieldset/CTRL2:
  description: SPI0 control2 register.
  fields:
  - name: CS_SETUP_TIME
    description: (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.
    bit_offset: 0
    bit_size: 5
  - name: CS_HOLD_TIME
    description: Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.
    bit_offset: 5
    bit_size: 5
  - name: CS_HOLD_DELAY
    description: These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.
    bit_offset: 25
    bit_size: 6
  - name: SYNC_RESET
    description: The FSM will be reset.
    bit_offset: 31
    bit_size: 1
fieldset/DATE:
  description: Version control register.
  fields:
  - name: DATE
    description: SPI register version.
    bit_offset: 0
    bit_size: 28
fieldset/DIN_MODE:
  description: SPI0 input delay mode control register.
  fields:
  - name: DIN0_MODE
    description: 'the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge.'
    bit_offset: 0
    bit_size: 2
  - name: DIN1_MODE
    description: 'the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge.'
    bit_offset: 2
    bit_size: 2
  - name: DIN2_MODE
    description: 'the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge.'
    bit_offset: 4
    bit_size: 2
  - name: DIN3_MODE
    description: 'the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge.'
    bit_offset: 6
    bit_size: 2
fieldset/DIN_NUM:
  description: SPI0 input delay number control register.
  fields:
  - name: DIN0_NUM
    description: 'the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...'
    bit_offset: 0
    bit_size: 2
  - name: DIN1_NUM
    description: 'the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...'
    bit_offset: 2
    bit_size: 2
  - name: DIN2_NUM
    description: 'the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...'
    bit_offset: 4
    bit_size: 2
  - name: DIN3_NUM
    description: 'the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...'
    bit_offset: 6
    bit_size: 2
fieldset/DOUT_MODE:
  description: SPI0 output delay mode control register.
  fields:
  - name: DOUT0_MODE
    description: 'the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge.'
    bit_offset: 0
    bit_size: 1
  - name: DOUT1_MODE
    description: 'the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge.'
    bit_offset: 1
    bit_size: 1
  - name: DOUT2_MODE
    description: 'the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge.'
    bit_offset: 2
    bit_size: 1
  - name: DOUT3_MODE
    description: 'the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge.'
    bit_offset: 3
    bit_size: 1
fieldset/FSM:
  description: SPI0 FSM status register.
  fields:
  - name: CSPI_ST
    description: 'The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.'
    bit_offset: 0
    bit_size: 4
  - name: EM_ST
    description: 'The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.'
    bit_offset: 4
    bit_size: 3
  - name: CSPI_LOCK_DELAY_TIME
    description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
    bit_offset: 7
    bit_size: 5
fieldset/MISC:
  description: SPI0 misc register.
  fields:
  - name: TRANS_END
    description: The bit is used to indicate the spi0_mst_st controlled transmitting is done.
    bit_offset: 3
    bit_size: 1
  - name: TRANS_END_INT_ENA
    description: The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done.
    bit_offset: 4
    bit_size: 1
  - name: CSPI_ST_TRANS_END
    description: The bit is used to indicate the spi0_slv_st controlled transmitting is done.
    bit_offset: 5
    bit_size: 1
  - name: CSPI_ST_TRANS_END_INT_ENA
    description: The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.
    bit_offset: 6
    bit_size: 1
  - name: CK_IDLE_EDGE
    description: '1: spi clk line is high when idle 0: spi clk line is low when idle.'
    bit_offset: 9
    bit_size: 1
  - name: CS_KEEP_ACTIVE
    description: spi cs line keep low when the bit is set.
    bit_offset: 10
    bit_size: 1
fieldset/RD_STATUS:
  description: SPI0 read control register.
  fields:
  - name: WB_MODE
    description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.
    bit_offset: 16
    bit_size: 8
fieldset/TIMING_CALI:
  description: SPI0 timing calibration register.
  fields:
  - name: TIMING_CLK_ENA
    description: The bit is used to enable timing adjust clock for all reading operations.
    bit_offset: 0
    bit_size: 1
  - name: TIMING_CALI
    description: The bit is used to enable timing auto-calibration for all reading operations.
    bit_offset: 1
    bit_size: 1
  - name: EXTRA_DUMMY_CYCLELEN
    description: add extra dummy spi clock cycle length for spi clock calibration.
    bit_offset: 2
    bit_size: 3
fieldset/USER:
  description: SPI0 user register.
  fields:
  - name: CS_HOLD
    description: 'spi cs keep low when spi is in done phase. 1: enable 0: disable.'
    bit_offset: 6
    bit_size: 1
  - name: CS_SETUP
    description: 'spi cs is enable when spi is in prepare phase. 1: enable 0: disable.'
    bit_offset: 7
    bit_size: 1
  - name: CK_OUT_EDGE
    description: the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
    bit_offset: 9
    bit_size: 1
  - name: USR_DUMMY_IDLE
    description: spi clock is disable in dummy phase when the bit is enable.
    bit_offset: 26
    bit_size: 1
  - name: USR_DUMMY
    description: This bit enable the dummy phase of an operation.
    bit_offset: 29
    bit_size: 1
fieldset/USER1:
  description: SPI0 user1 register.
  fields:
  - name: USR_DUMMY_CYCLELEN
    description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).
    bit_offset: 0
    bit_size: 6
  - name: USR_ADDR_BITLEN
    description: The length in bits of address phase. The register value shall be (bit_num-1).
    bit_offset: 26
    bit_size: 6
fieldset/USER2:
  description: SPI0 user2 register.
  fields:
  - name: USR_COMMAND_VALUE
    description: The value of command.
    bit_offset: 0
    bit_size: 16
  - name: USR_COMMAND_BITLEN
    description: The length in bits of command phase. The register value shall be (bit_num-1).
    bit_offset: 28
    bit_size: 4