block/DMA: description: DMA (Direct Memory Access) Controller. items: - name: INT_RAW_CH description: DMA_INT_RAW_CH%s_REG. array: len: 3 stride: 16 byte_offset: 0 fieldset: INT_RAW_CH - name: INT_ST_CH0 description: DMA_INT_ST_CH0_REG. byte_offset: 4 fieldset: INT_ST_CH0 - name: INT_ENA_CH description: DMA_INT_ENA_CH%s_REG. array: len: 3 stride: 16 byte_offset: 8 fieldset: INT_ENA_CH - name: INT_CLR_CH description: DMA_INT_CLR_CH%s_REG. array: len: 3 stride: 16 byte_offset: 12 fieldset: INT_CLR_CH - name: INT_ST_CH1 description: DMA_INT_ST_CH1_REG. byte_offset: 20 fieldset: INT_ST_CH1 - name: INT_ST_CH2 description: DMA_INT_ST_CH2_REG. byte_offset: 36 fieldset: INT_ST_CH2 - name: AHB_TEST description: DMA_AHB_TEST_REG. byte_offset: 64 fieldset: AHB_TEST - name: MISC_CONF description: DMA_MISC_CONF_REG. byte_offset: 68 fieldset: MISC_CONF - name: DATE description: DMA_DATE_REG. byte_offset: 72 fieldset: DATE - name: IN_CONF0_CH description: DMA_IN_CONF%s_CH%s_REG. array: len: 3 stride: 192 byte_offset: 112 fieldset: IN_CONF0_CH - name: IN_CONF1_CH0 description: DMA_IN_CONF1_CH0_REG. byte_offset: 116 fieldset: IN_CONF1_CH0 - name: INFIFO_STATUS_CH0 description: DMA_INFIFO_STATUS_CH0_REG. byte_offset: 120 fieldset: INFIFO_STATUS_CH0 - name: IN_POP_CH0 description: DMA_IN_POP_CH0_REG. byte_offset: 124 fieldset: IN_POP_CH0 - name: IN_LINK_CH description: DMA_IN_LINK_CH%s_REG. array: len: 3 stride: 192 byte_offset: 128 fieldset: IN_LINK_CH - name: IN_STATE_CH0 description: DMA_IN_STATE_CH0_REG. byte_offset: 132 fieldset: IN_STATE_CH0 - name: IN_SUC_EOF_DES_ADDR_CH0 description: DMA_IN_SUC_EOF_DES_ADDR_CH0_REG. byte_offset: 136 fieldset: IN_SUC_EOF_DES_ADDR_CH0 - name: IN_ERR_EOF_DES_ADDR_CH0 description: DMA_IN_ERR_EOF_DES_ADDR_CH0_REG. byte_offset: 140 fieldset: IN_ERR_EOF_DES_ADDR_CH0 - name: IN_DSCR_CH0 description: DMA_IN_DSCR_CH0_REG. byte_offset: 144 fieldset: IN_DSCR_CH0 - name: IN_DSCR_BF0_CH description: DMA_IN_DSCR_BF%s_CH%s_REG. array: len: 3 stride: 192 byte_offset: 148 fieldset: IN_DSCR_BF0_CH - name: IN_DSCR_BF1_CH0 description: DMA_IN_DSCR_BF1_CH0_REG. byte_offset: 152 fieldset: IN_DSCR_BF1_CH0 - name: IN_PRI_CH description: DMA_IN_PRI_CH%s_REG. array: len: 3 stride: 192 byte_offset: 156 fieldset: IN_PRI_CH - name: IN_PERI_SEL_CH description: DMA_IN_PERI_SEL_CH%s_REG. array: len: 3 stride: 192 byte_offset: 160 fieldset: IN_PERI_SEL_CH - name: OUT_CONF0_CH description: DMA_OUT_CONF%s_CH%s_REG. array: len: 3 stride: 192 byte_offset: 208 fieldset: OUT_CONF0_CH - name: OUT_CONF1_CH description: DMA_OUT_CONF1_CH%s_REG. array: len: 3 stride: 192 byte_offset: 212 fieldset: OUT_CONF1_CH - name: OUTFIFO_STATUS_CH0 description: DMA_OUTFIFO_STATUS_CH0_REG. byte_offset: 216 fieldset: OUTFIFO_STATUS_CH0 - name: OUT_PUSH_CH0 description: DMA_OUT_PUSH_CH0_REG. byte_offset: 220 fieldset: OUT_PUSH_CH0 - name: OUT_LINK_CH description: DMA_OUT_LINK_CH%s_REG. array: len: 3 stride: 192 byte_offset: 224 fieldset: OUT_LINK_CH - name: OUT_STATE_CH0 description: DMA_OUT_STATE_CH0_REG. byte_offset: 228 fieldset: OUT_STATE_CH0 - name: OUT_EOF_DES_ADDR_CH description: DMA_OUT_EOF_DES_ADDR_CH%s_REG. array: len: 3 stride: 192 byte_offset: 232 fieldset: OUT_EOF_DES_ADDR_CH - name: OUT_EOF_BFR_DES_ADDR_CH0 description: DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG. byte_offset: 236 fieldset: OUT_EOF_BFR_DES_ADDR_CH0 - name: OUT_DSCR_CH0 description: DMA_OUT_DSCR_CH0_REG. byte_offset: 240 fieldset: OUT_DSCR_CH0 - name: OUT_DSCR_BF0_CH0 description: DMA_OUT_DSCR_BF0_CH0_REG. byte_offset: 244 fieldset: OUT_DSCR_BF0_CH0 - name: OUT_DSCR_BF1_CH0 description: DMA_OUT_DSCR_BF1_CH0_REG. byte_offset: 248 fieldset: OUT_DSCR_BF1_CH0 - name: OUT_PRI_CH description: DMA_OUT_PRI_CH%s_REG. array: len: 3 stride: 192 byte_offset: 252 fieldset: OUT_PRI_CH - name: OUT_PERI_SEL_CH description: DMA_OUT_PERI_SEL_CH%s_REG. array: len: 3 stride: 192 byte_offset: 256 fieldset: OUT_PERI_SEL_CH - name: IN_CONF1_CH1 description: DMA_IN_CONF1_CH1_REG. byte_offset: 308 fieldset: IN_CONF1_CH1 - name: INFIFO_STATUS_CH1 description: DMA_INFIFO_STATUS_CH1_REG. byte_offset: 312 fieldset: INFIFO_STATUS_CH1 - name: IN_POP_CH1 description: DMA_IN_POP_CH1_REG. byte_offset: 316 fieldset: IN_POP_CH1 - name: IN_STATE_CH1 description: DMA_IN_STATE_CH1_REG. byte_offset: 324 fieldset: IN_STATE_CH1 - name: IN_SUC_EOF_DES_ADDR_CH1 description: DMA_IN_SUC_EOF_DES_ADDR_CH1_REG. byte_offset: 328 fieldset: IN_SUC_EOF_DES_ADDR_CH1 - name: IN_ERR_EOF_DES_ADDR_CH1 description: DMA_IN_ERR_EOF_DES_ADDR_CH1_REG. byte_offset: 332 fieldset: IN_ERR_EOF_DES_ADDR_CH1 - name: IN_DSCR_CH1 description: DMA_IN_DSCR_CH1_REG. byte_offset: 336 fieldset: IN_DSCR_CH1 - name: IN_DSCR_BF1_CH1 description: DMA_IN_DSCR_BF1_CH1_REG. byte_offset: 344 fieldset: IN_DSCR_BF1_CH1 - name: OUTFIFO_STATUS_CH1 description: DMA_OUTFIFO_STATUS_CH1_REG. byte_offset: 408 fieldset: OUTFIFO_STATUS_CH1 - name: OUT_PUSH_CH1 description: DMA_OUT_PUSH_CH1_REG. byte_offset: 412 fieldset: OUT_PUSH_CH1 - name: OUT_STATE_CH1 description: DMA_OUT_STATE_CH1_REG. byte_offset: 420 fieldset: OUT_STATE_CH1 - name: OUT_EOF_BFR_DES_ADDR_CH1 description: DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG. byte_offset: 428 fieldset: OUT_EOF_BFR_DES_ADDR_CH1 - name: OUT_DSCR_CH1 description: DMA_OUT_DSCR_CH1_REG. byte_offset: 432 fieldset: OUT_DSCR_CH1 - name: OUT_DSCR_BF0_CH1 description: DMA_OUT_DSCR_BF0_CH1_REG. byte_offset: 436 fieldset: OUT_DSCR_BF0_CH1 - name: OUT_DSCR_BF1_CH1 description: DMA_OUT_DSCR_BF1_CH1_REG. byte_offset: 440 fieldset: OUT_DSCR_BF1_CH1 - name: IN_CONF1_CH2 description: DMA_IN_CONF1_CH2_REG. byte_offset: 500 fieldset: IN_CONF1_CH2 - name: INFIFO_STATUS_CH2 description: DMA_INFIFO_STATUS_CH2_REG. byte_offset: 504 fieldset: INFIFO_STATUS_CH2 - name: IN_POP_CH2 description: DMA_IN_POP_CH2_REG. byte_offset: 508 fieldset: IN_POP_CH2 - name: IN_STATE_CH2 description: DMA_IN_STATE_CH2_REG. byte_offset: 516 fieldset: IN_STATE_CH2 - name: IN_SUC_EOF_DES_ADDR_CH2 description: DMA_IN_SUC_EOF_DES_ADDR_CH2_REG. byte_offset: 520 fieldset: IN_SUC_EOF_DES_ADDR_CH2 - name: IN_ERR_EOF_DES_ADDR_CH2 description: DMA_IN_ERR_EOF_DES_ADDR_CH2_REG. byte_offset: 524 fieldset: IN_ERR_EOF_DES_ADDR_CH2 - name: IN_DSCR_CH2 description: DMA_IN_DSCR_CH2_REG. byte_offset: 528 fieldset: IN_DSCR_CH2 - name: IN_DSCR_BF1_CH2 description: DMA_IN_DSCR_BF1_CH2_REG. byte_offset: 536 fieldset: IN_DSCR_BF1_CH2 - name: OUTFIFO_STATUS_CH2 description: DMA_OUTFIFO_STATUS_CH2_REG. byte_offset: 600 fieldset: OUTFIFO_STATUS_CH2 - name: OUT_PUSH_CH2 description: DMA_OUT_PUSH_CH2_REG. byte_offset: 604 fieldset: OUT_PUSH_CH2 - name: OUT_STATE_CH2 description: DMA_OUT_STATE_CH2_REG. byte_offset: 612 fieldset: OUT_STATE_CH2 - name: OUT_EOF_BFR_DES_ADDR_CH2 description: DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG. byte_offset: 620 fieldset: OUT_EOF_BFR_DES_ADDR_CH2 - name: OUT_DSCR_CH2 description: DMA_OUT_DSCR_CH2_REG. byte_offset: 624 fieldset: OUT_DSCR_CH2 - name: OUT_DSCR_BF0_CH2 description: DMA_OUT_DSCR_BF0_CH2_REG. byte_offset: 628 fieldset: OUT_DSCR_BF0_CH2 - name: OUT_DSCR_BF1_CH2 description: DMA_OUT_DSCR_BF1_CH2_REG. byte_offset: 632 fieldset: OUT_DSCR_BF1_CH2 fieldset/AHB_TEST: description: DMA_AHB_TEST_REG. fields: - name: AHB_TESTMODE description: reserved. bit_offset: 0 bit_size: 3 - name: AHB_TESTADDR description: reserved. bit_offset: 4 bit_size: 2 fieldset/DATE: description: DMA_DATE_REG. fields: - name: DATE description: register version. bit_offset: 0 bit_size: 32 fieldset/INFIFO_STATUS_CH0: description: DMA_INFIFO_STATUS_CH0_REG. fields: - name: INFIFO_FULL description: L1 Rx FIFO full signal for Rx channel 0. bit_offset: 0 bit_size: 1 - name: INFIFO_EMPTY description: L1 Rx FIFO empty signal for Rx channel 0. bit_offset: 1 bit_size: 1 - name: INFIFO_CNT description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. bit_offset: 2 bit_size: 6 - name: IN_REMAIN_UNDER_1B description: reserved. bit_offset: 23 bit_size: 1 - name: IN_REMAIN_UNDER_2B description: reserved. bit_offset: 24 bit_size: 1 - name: IN_REMAIN_UNDER_3B description: reserved. bit_offset: 25 bit_size: 1 - name: IN_REMAIN_UNDER_4B description: reserved. bit_offset: 26 bit_size: 1 - name: IN_BUF_HUNGRY description: reserved. bit_offset: 27 bit_size: 1 fieldset/INFIFO_STATUS_CH1: description: DMA_INFIFO_STATUS_CH1_REG. fields: - name: INFIFO_FULL description: L1 Rx FIFO full signal for Rx channel 1. bit_offset: 0 bit_size: 1 - name: INFIFO_EMPTY description: L1 Rx FIFO empty signal for Rx channel 1. bit_offset: 1 bit_size: 1 - name: INFIFO_CNT description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1. bit_offset: 2 bit_size: 6 - name: IN_REMAIN_UNDER_1B description: reserved. bit_offset: 23 bit_size: 1 - name: IN_REMAIN_UNDER_2B description: reserved. bit_offset: 24 bit_size: 1 - name: IN_REMAIN_UNDER_3B description: reserved. bit_offset: 25 bit_size: 1 - name: IN_REMAIN_UNDER_4B description: reserved. bit_offset: 26 bit_size: 1 - name: IN_BUF_HUNGRY description: reserved. bit_offset: 27 bit_size: 1 fieldset/INFIFO_STATUS_CH2: description: DMA_INFIFO_STATUS_CH2_REG. fields: - name: INFIFO_FULL description: L1 Rx FIFO full signal for Rx channel 2. bit_offset: 0 bit_size: 1 - name: INFIFO_EMPTY description: L1 Rx FIFO empty signal for Rx channel 2. bit_offset: 1 bit_size: 1 - name: INFIFO_CNT description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2. bit_offset: 2 bit_size: 6 - name: IN_REMAIN_UNDER_1B description: reserved. bit_offset: 23 bit_size: 1 - name: IN_REMAIN_UNDER_2B description: reserved. bit_offset: 24 bit_size: 1 - name: IN_REMAIN_UNDER_3B description: reserved. bit_offset: 25 bit_size: 1 - name: IN_REMAIN_UNDER_4B description: reserved. bit_offset: 26 bit_size: 1 - name: IN_BUF_HUNGRY description: reserved. bit_offset: 27 bit_size: 1 fieldset/INT_CLR_CH: description: DMA_INT_CLR_CH%s_REG. fields: - name: IN_DONE description: Set this bit to clear the IN_DONE_CH_INT interrupt. bit_offset: 0 bit_size: 1 - name: IN_SUC_EOF description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. bit_offset: 1 bit_size: 1 - name: IN_ERR_EOF description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. bit_offset: 2 bit_size: 1 - name: OUT_DONE description: Set this bit to clear the OUT_DONE_CH_INT interrupt. bit_offset: 3 bit_size: 1 - name: OUT_EOF description: Set this bit to clear the OUT_EOF_CH_INT interrupt. bit_offset: 4 bit_size: 1 - name: IN_DSCR_ERR description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. bit_offset: 5 bit_size: 1 - name: OUT_DSCR_ERR description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. bit_offset: 6 bit_size: 1 - name: IN_DSCR_EMPTY description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. bit_offset: 7 bit_size: 1 - name: OUT_TOTAL_EOF description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. bit_offset: 8 bit_size: 1 - name: INFIFO_OVF description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. bit_offset: 9 bit_size: 1 - name: INFIFO_UDF description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. bit_offset: 10 bit_size: 1 - name: OUTFIFO_OVF description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. bit_offset: 11 bit_size: 1 - name: OUTFIFO_UDF description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. bit_offset: 12 bit_size: 1 fieldset/INT_ENA_CH: description: DMA_INT_ENA_CH%s_REG. fields: - name: IN_DONE description: The interrupt enable bit for the IN_DONE_CH_INT interrupt. bit_offset: 0 bit_size: 1 - name: IN_SUC_EOF description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. bit_offset: 1 bit_size: 1 - name: IN_ERR_EOF description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. bit_offset: 2 bit_size: 1 - name: OUT_DONE description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt. bit_offset: 3 bit_size: 1 - name: OUT_EOF description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt. bit_offset: 4 bit_size: 1 - name: IN_DSCR_ERR description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. bit_offset: 5 bit_size: 1 - name: OUT_DSCR_ERR description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. bit_offset: 6 bit_size: 1 - name: IN_DSCR_EMPTY description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. bit_offset: 7 bit_size: 1 - name: OUT_TOTAL_EOF description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. bit_offset: 8 bit_size: 1 - name: INFIFO_OVF description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. bit_offset: 9 bit_size: 1 - name: INFIFO_UDF description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. bit_offset: 10 bit_size: 1 - name: OUTFIFO_OVF description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. bit_offset: 11 bit_size: 1 - name: OUTFIFO_UDF description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. bit_offset: 12 bit_size: 1 fieldset/INT_RAW_CH: description: DMA_INT_RAW_CH%s_REG. fields: - name: IN_DONE description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. bit_offset: 0 bit_size: 1 - name: IN_SUC_EOF description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. bit_offset: 1 bit_size: 1 - name: IN_ERR_EOF description: The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved. bit_offset: 2 bit_size: 1 - name: OUT_DONE description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. bit_offset: 3 bit_size: 1 - name: OUT_EOF description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. bit_offset: 4 bit_size: 1 - name: IN_DSCR_ERR description: The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. bit_offset: 5 bit_size: 1 - name: OUT_DSCR_ERR description: The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. bit_offset: 6 bit_size: 1 - name: IN_DSCR_EMPTY description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0. bit_offset: 7 bit_size: 1 - name: OUT_TOTAL_EOF description: The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. bit_offset: 8 bit_size: 1 - name: INFIFO_OVF description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. bit_offset: 9 bit_size: 1 - name: INFIFO_UDF description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. bit_offset: 10 bit_size: 1 - name: OUTFIFO_OVF description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. bit_offset: 11 bit_size: 1 - name: OUTFIFO_UDF description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. bit_offset: 12 bit_size: 1 fieldset/INT_ST_CH0: description: DMA_INT_ST_CH0_REG. fields: - name: IN_DONE description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt. bit_offset: 0 bit_size: 1 - name: IN_SUC_EOF description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. bit_offset: 1 bit_size: 1 - name: IN_ERR_EOF description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. bit_offset: 2 bit_size: 1 - name: OUT_DONE description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. bit_offset: 3 bit_size: 1 - name: OUT_EOF description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. bit_offset: 4 bit_size: 1 - name: IN_DSCR_ERR description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. bit_offset: 5 bit_size: 1 - name: OUT_DSCR_ERR description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. bit_offset: 6 bit_size: 1 - name: IN_DSCR_EMPTY description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. bit_offset: 7 bit_size: 1 - name: OUT_TOTAL_EOF description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. bit_offset: 8 bit_size: 1 - name: INFIFO_OVF description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. bit_offset: 9 bit_size: 1 - name: INFIFO_UDF description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. bit_offset: 10 bit_size: 1 - name: OUTFIFO_OVF description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. bit_offset: 11 bit_size: 1 - name: OUTFIFO_UDF description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. bit_offset: 12 bit_size: 1 fieldset/INT_ST_CH1: description: DMA_INT_ST_CH1_REG. fields: - name: IN_DONE description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt. bit_offset: 0 bit_size: 1 - name: IN_SUC_EOF description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. bit_offset: 1 bit_size: 1 - name: IN_ERR_EOF description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. bit_offset: 2 bit_size: 1 - name: OUT_DONE description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. bit_offset: 3 bit_size: 1 - name: OUT_EOF description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. bit_offset: 4 bit_size: 1 - name: IN_DSCR_ERR description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. bit_offset: 5 bit_size: 1 - name: OUT_DSCR_ERR description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. bit_offset: 6 bit_size: 1 - name: IN_DSCR_EMPTY description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. bit_offset: 7 bit_size: 1 - name: OUT_TOTAL_EOF description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. bit_offset: 8 bit_size: 1 - name: INFIFO_OVF description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. bit_offset: 9 bit_size: 1 - name: INFIFO_UDF description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. bit_offset: 10 bit_size: 1 - name: OUTFIFO_OVF description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. bit_offset: 11 bit_size: 1 - name: OUTFIFO_UDF description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. bit_offset: 12 bit_size: 1 fieldset/INT_ST_CH2: description: DMA_INT_ST_CH2_REG. fields: - name: IN_DONE description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt. bit_offset: 0 bit_size: 1 - name: IN_SUC_EOF description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. bit_offset: 1 bit_size: 1 - name: IN_ERR_EOF description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. bit_offset: 2 bit_size: 1 - name: OUT_DONE description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. bit_offset: 3 bit_size: 1 - name: OUT_EOF description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. bit_offset: 4 bit_size: 1 - name: IN_DSCR_ERR description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. bit_offset: 5 bit_size: 1 - name: OUT_DSCR_ERR description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. bit_offset: 6 bit_size: 1 - name: IN_DSCR_EMPTY description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. bit_offset: 7 bit_size: 1 - name: OUT_TOTAL_EOF description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. bit_offset: 8 bit_size: 1 - name: INFIFO_OVF description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. bit_offset: 9 bit_size: 1 - name: INFIFO_UDF description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. bit_offset: 10 bit_size: 1 - name: OUTFIFO_OVF description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. bit_offset: 11 bit_size: 1 - name: OUTFIFO_UDF description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. bit_offset: 12 bit_size: 1 fieldset/IN_CONF0_CH: description: DMA_IN_CONF%s_CH%s_REG. fields: - name: IN_RST description: This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. bit_offset: 0 bit_size: 1 - name: IN_LOOP_TEST description: reserved. bit_offset: 1 bit_size: 1 - name: INDSCR_BURST_EN description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. bit_offset: 2 bit_size: 1 - name: IN_DATA_BURST_EN description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. bit_offset: 3 bit_size: 1 - name: MEM_TRANS_EN description: Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. bit_offset: 4 bit_size: 1 fieldset/IN_CONF1_CH0: description: DMA_IN_CONF1_CH0_REG. fields: - name: IN_CHECK_OWNER description: Set this bit to enable checking the owner attribute of the link descriptor. bit_offset: 12 bit_size: 1 fieldset/IN_CONF1_CH1: description: DMA_IN_CONF1_CH1_REG. fields: - name: IN_CHECK_OWNER description: Set this bit to enable checking the owner attribute of the link descriptor. bit_offset: 12 bit_size: 1 fieldset/IN_CONF1_CH2: description: DMA_IN_CONF1_CH2_REG. fields: - name: IN_CHECK_OWNER description: Set this bit to enable checking the owner attribute of the link descriptor. bit_offset: 12 bit_size: 1 fieldset/IN_DSCR_BF0_CH: description: DMA_IN_DSCR_BF%s_CH%s_REG. fields: - name: INLINK_DSCR_BF0 description: The address of the last inlink descriptor x-1. bit_offset: 0 bit_size: 32 fieldset/IN_DSCR_BF1_CH0: description: DMA_IN_DSCR_BF1_CH0_REG. fields: - name: INLINK_DSCR_BF1 description: The address of the second-to-last inlink descriptor x-2. bit_offset: 0 bit_size: 32 fieldset/IN_DSCR_BF1_CH1: description: DMA_IN_DSCR_BF1_CH1_REG. fields: - name: INLINK_DSCR_BF1 description: The address of the second-to-last inlink descriptor x-2. bit_offset: 0 bit_size: 32 fieldset/IN_DSCR_BF1_CH2: description: DMA_IN_DSCR_BF1_CH2_REG. fields: - name: INLINK_DSCR_BF1 description: The address of the second-to-last inlink descriptor x-2. bit_offset: 0 bit_size: 32 fieldset/IN_DSCR_CH0: description: DMA_IN_DSCR_CH0_REG. fields: - name: INLINK_DSCR description: The address of the current inlink descriptor x. bit_offset: 0 bit_size: 32 fieldset/IN_DSCR_CH1: description: DMA_IN_DSCR_CH1_REG. fields: - name: INLINK_DSCR description: The address of the current inlink descriptor x. bit_offset: 0 bit_size: 32 fieldset/IN_DSCR_CH2: description: DMA_IN_DSCR_CH2_REG. fields: - name: INLINK_DSCR description: The address of the current inlink descriptor x. bit_offset: 0 bit_size: 32 fieldset/IN_ERR_EOF_DES_ADDR_CH0: description: DMA_IN_ERR_EOF_DES_ADDR_CH0_REG. fields: - name: IN_ERR_EOF_DES_ADDR description: This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. bit_offset: 0 bit_size: 32 fieldset/IN_ERR_EOF_DES_ADDR_CH1: description: DMA_IN_ERR_EOF_DES_ADDR_CH1_REG. fields: - name: IN_ERR_EOF_DES_ADDR description: This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. bit_offset: 0 bit_size: 32 fieldset/IN_ERR_EOF_DES_ADDR_CH2: description: DMA_IN_ERR_EOF_DES_ADDR_CH2_REG. fields: - name: IN_ERR_EOF_DES_ADDR description: This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. bit_offset: 0 bit_size: 32 fieldset/IN_LINK_CH: description: DMA_IN_LINK_CH%s_REG. fields: - name: INLINK_ADDR description: This register stores the 20 least significant bits of the first inlink descriptor's address. bit_offset: 0 bit_size: 20 - name: INLINK_AUTO_RET description: Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. bit_offset: 20 bit_size: 1 - name: INLINK_STOP description: Set this bit to stop dealing with the inlink descriptors. bit_offset: 21 bit_size: 1 - name: INLINK_START description: Set this bit to start dealing with the inlink descriptors. bit_offset: 22 bit_size: 1 - name: INLINK_RESTART description: Set this bit to mount a new inlink descriptor. bit_offset: 23 bit_size: 1 - name: INLINK_PARK description: '1: the inlink descriptor''s FSM is in idle state. 0: the inlink descriptor''s FSM is working.' bit_offset: 24 bit_size: 1 fieldset/IN_PERI_SEL_CH: description: DMA_IN_PERI_SEL_CH%s_REG. fields: - name: PERI_IN_SEL description: 'This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.' bit_offset: 0 bit_size: 6 fieldset/IN_POP_CH0: description: DMA_IN_POP_CH0_REG. fields: - name: INFIFO_RDATA description: This register stores the data popping from DMA FIFO. bit_offset: 0 bit_size: 12 - name: INFIFO_POP description: Set this bit to pop data from DMA FIFO. bit_offset: 12 bit_size: 1 fieldset/IN_POP_CH1: description: DMA_IN_POP_CH1_REG. fields: - name: INFIFO_RDATA description: This register stores the data popping from DMA FIFO. bit_offset: 0 bit_size: 12 - name: INFIFO_POP description: Set this bit to pop data from DMA FIFO. bit_offset: 12 bit_size: 1 fieldset/IN_POP_CH2: description: DMA_IN_POP_CH2_REG. fields: - name: INFIFO_RDATA description: This register stores the data popping from DMA FIFO. bit_offset: 0 bit_size: 12 - name: INFIFO_POP description: Set this bit to pop data from DMA FIFO. bit_offset: 12 bit_size: 1 fieldset/IN_PRI_CH: description: DMA_IN_PRI_CH%s_REG. fields: - name: RX_PRI description: The priority of Rx channel 0. The larger of the value, the higher of the priority. bit_offset: 0 bit_size: 4 fieldset/IN_STATE_CH0: description: DMA_IN_STATE_CH0_REG. fields: - name: INLINK_DSCR_ADDR description: This register stores the current inlink descriptor's address. bit_offset: 0 bit_size: 18 - name: IN_DSCR_STATE description: reserved. bit_offset: 18 bit_size: 2 - name: IN_STATE description: reserved. bit_offset: 20 bit_size: 3 fieldset/IN_STATE_CH1: description: DMA_IN_STATE_CH1_REG. fields: - name: INLINK_DSCR_ADDR description: This register stores the current inlink descriptor's address. bit_offset: 0 bit_size: 18 - name: IN_DSCR_STATE description: reserved. bit_offset: 18 bit_size: 2 - name: IN_STATE description: reserved. bit_offset: 20 bit_size: 3 fieldset/IN_STATE_CH2: description: DMA_IN_STATE_CH2_REG. fields: - name: INLINK_DSCR_ADDR description: This register stores the current inlink descriptor's address. bit_offset: 0 bit_size: 18 - name: IN_DSCR_STATE description: reserved. bit_offset: 18 bit_size: 2 - name: IN_STATE description: reserved. bit_offset: 20 bit_size: 3 fieldset/IN_SUC_EOF_DES_ADDR_CH0: description: DMA_IN_SUC_EOF_DES_ADDR_CH0_REG. fields: - name: IN_SUC_EOF_DES_ADDR description: This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. bit_offset: 0 bit_size: 32 fieldset/IN_SUC_EOF_DES_ADDR_CH1: description: DMA_IN_SUC_EOF_DES_ADDR_CH1_REG. fields: - name: IN_SUC_EOF_DES_ADDR description: This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. bit_offset: 0 bit_size: 32 fieldset/IN_SUC_EOF_DES_ADDR_CH2: description: DMA_IN_SUC_EOF_DES_ADDR_CH2_REG. fields: - name: IN_SUC_EOF_DES_ADDR description: This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. bit_offset: 0 bit_size: 32 fieldset/MISC_CONF: description: DMA_MISC_CONF_REG. fields: - name: AHBM_RST_INTER description: Set this bit, then clear this bit to reset the internal ahb FSM. bit_offset: 0 bit_size: 1 - name: ARB_PRI_DIS description: Set this bit to disable priority arbitration function. bit_offset: 2 bit_size: 1 - name: CLK_EN description: reg_clk_en. bit_offset: 3 bit_size: 1 fieldset/OUTFIFO_STATUS_CH0: description: DMA_OUTFIFO_STATUS_CH0_REG. fields: - name: OUTFIFO_FULL description: L1 Tx FIFO full signal for Tx channel 0. bit_offset: 0 bit_size: 1 - name: OUTFIFO_EMPTY description: L1 Tx FIFO empty signal for Tx channel 0. bit_offset: 1 bit_size: 1 - name: OUTFIFO_CNT description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. bit_offset: 2 bit_size: 6 - name: OUT_REMAIN_UNDER_1B description: reserved. bit_offset: 23 bit_size: 1 - name: OUT_REMAIN_UNDER_2B description: reserved. bit_offset: 24 bit_size: 1 - name: OUT_REMAIN_UNDER_3B description: reserved. bit_offset: 25 bit_size: 1 - name: OUT_REMAIN_UNDER_4B description: reserved. bit_offset: 26 bit_size: 1 fieldset/OUTFIFO_STATUS_CH1: description: DMA_OUTFIFO_STATUS_CH1_REG. fields: - name: OUTFIFO_FULL description: L1 Tx FIFO full signal for Tx channel 1. bit_offset: 0 bit_size: 1 - name: OUTFIFO_EMPTY description: L1 Tx FIFO empty signal for Tx channel 1. bit_offset: 1 bit_size: 1 - name: OUTFIFO_CNT description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1. bit_offset: 2 bit_size: 6 - name: OUT_REMAIN_UNDER_1B description: reserved. bit_offset: 23 bit_size: 1 - name: OUT_REMAIN_UNDER_2B description: reserved. bit_offset: 24 bit_size: 1 - name: OUT_REMAIN_UNDER_3B description: reserved. bit_offset: 25 bit_size: 1 - name: OUT_REMAIN_UNDER_4B description: reserved. bit_offset: 26 bit_size: 1 fieldset/OUTFIFO_STATUS_CH2: description: DMA_OUTFIFO_STATUS_CH2_REG. fields: - name: OUTFIFO_FULL description: L1 Tx FIFO full signal for Tx channel 2. bit_offset: 0 bit_size: 1 - name: OUTFIFO_EMPTY description: L1 Tx FIFO empty signal for Tx channel 2. bit_offset: 1 bit_size: 1 - name: OUTFIFO_CNT description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2. bit_offset: 2 bit_size: 6 - name: OUT_REMAIN_UNDER_1B description: reserved. bit_offset: 23 bit_size: 1 - name: OUT_REMAIN_UNDER_2B description: reserved. bit_offset: 24 bit_size: 1 - name: OUT_REMAIN_UNDER_3B description: reserved. bit_offset: 25 bit_size: 1 - name: OUT_REMAIN_UNDER_4B description: reserved. bit_offset: 26 bit_size: 1 fieldset/OUT_CONF0_CH: description: DMA_OUT_CONF%s_CH%s_REG. fields: - name: OUT_RST description: This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. bit_offset: 0 bit_size: 1 - name: OUT_LOOP_TEST description: reserved. bit_offset: 1 bit_size: 1 - name: OUT_AUTO_WRBACK description: Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. bit_offset: 2 bit_size: 1 - name: OUT_EOF_MODE description: 'EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA.' bit_offset: 3 bit_size: 1 - name: OUTDSCR_BURST_EN description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. bit_offset: 4 bit_size: 1 - name: OUT_DATA_BURST_EN description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. bit_offset: 5 bit_size: 1 fieldset/OUT_CONF1_CH: description: DMA_OUT_CONF1_CH%s_REG. fields: - name: OUT_CHECK_OWNER description: Set this bit to enable checking the owner attribute of the link descriptor. bit_offset: 12 bit_size: 1 fieldset/OUT_DSCR_BF0_CH0: description: DMA_OUT_DSCR_BF0_CH0_REG. fields: - name: OUTLINK_DSCR_BF0 description: The address of the last outlink descriptor y-1. bit_offset: 0 bit_size: 32 fieldset/OUT_DSCR_BF0_CH1: description: DMA_OUT_DSCR_BF0_CH1_REG. fields: - name: OUTLINK_DSCR_BF0 description: The address of the last outlink descriptor y-1. bit_offset: 0 bit_size: 32 fieldset/OUT_DSCR_BF0_CH2: description: DMA_OUT_DSCR_BF0_CH2_REG. fields: - name: OUTLINK_DSCR_BF0 description: The address of the last outlink descriptor y-1. bit_offset: 0 bit_size: 32 fieldset/OUT_DSCR_BF1_CH0: description: DMA_OUT_DSCR_BF1_CH0_REG. fields: - name: OUTLINK_DSCR_BF1 description: The address of the second-to-last inlink descriptor x-2. bit_offset: 0 bit_size: 32 fieldset/OUT_DSCR_BF1_CH1: description: DMA_OUT_DSCR_BF1_CH1_REG. fields: - name: OUTLINK_DSCR_BF1 description: The address of the second-to-last inlink descriptor x-2. bit_offset: 0 bit_size: 32 fieldset/OUT_DSCR_BF1_CH2: description: DMA_OUT_DSCR_BF1_CH2_REG. fields: - name: OUTLINK_DSCR_BF1 description: The address of the second-to-last inlink descriptor x-2. bit_offset: 0 bit_size: 32 fieldset/OUT_DSCR_CH0: description: DMA_OUT_DSCR_CH0_REG. fields: - name: OUTLINK_DSCR description: The address of the current outlink descriptor y. bit_offset: 0 bit_size: 32 fieldset/OUT_DSCR_CH1: description: DMA_OUT_DSCR_CH1_REG. fields: - name: OUTLINK_DSCR description: The address of the current outlink descriptor y. bit_offset: 0 bit_size: 32 fieldset/OUT_DSCR_CH2: description: DMA_OUT_DSCR_CH2_REG. fields: - name: OUTLINK_DSCR description: The address of the current outlink descriptor y. bit_offset: 0 bit_size: 32 fieldset/OUT_EOF_BFR_DES_ADDR_CH0: description: DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG. fields: - name: OUT_EOF_BFR_DES_ADDR description: This register stores the address of the outlink descriptor before the last outlink descriptor. bit_offset: 0 bit_size: 32 fieldset/OUT_EOF_BFR_DES_ADDR_CH1: description: DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG. fields: - name: OUT_EOF_BFR_DES_ADDR description: This register stores the address of the outlink descriptor before the last outlink descriptor. bit_offset: 0 bit_size: 32 fieldset/OUT_EOF_BFR_DES_ADDR_CH2: description: DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG. fields: - name: OUT_EOF_BFR_DES_ADDR description: This register stores the address of the outlink descriptor before the last outlink descriptor. bit_offset: 0 bit_size: 32 fieldset/OUT_EOF_DES_ADDR_CH: description: DMA_OUT_EOF_DES_ADDR_CH%s_REG. fields: - name: OUT_EOF_DES_ADDR description: This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. bit_offset: 0 bit_size: 32 fieldset/OUT_LINK_CH: description: DMA_OUT_LINK_CH%s_REG. fields: - name: OUTLINK_ADDR description: This register stores the 20 least significant bits of the first outlink descriptor's address. bit_offset: 0 bit_size: 20 - name: OUTLINK_STOP description: Set this bit to stop dealing with the outlink descriptors. bit_offset: 20 bit_size: 1 - name: OUTLINK_START description: Set this bit to start dealing with the outlink descriptors. bit_offset: 21 bit_size: 1 - name: OUTLINK_RESTART description: Set this bit to restart a new outlink from the last address. bit_offset: 22 bit_size: 1 - name: OUTLINK_PARK description: '1: the outlink descriptor''s FSM is in idle state. 0: the outlink descriptor''s FSM is working.' bit_offset: 23 bit_size: 1 fieldset/OUT_PERI_SEL_CH: description: DMA_OUT_PERI_SEL_CH%s_REG. fields: - name: PERI_OUT_SEL description: 'This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.' bit_offset: 0 bit_size: 6 fieldset/OUT_PRI_CH: description: DMA_OUT_PRI_CH%s_REG. fields: - name: TX_PRI description: The priority of Tx channel 0. The larger of the value, the higher of the priority. bit_offset: 0 bit_size: 4 fieldset/OUT_PUSH_CH0: description: DMA_OUT_PUSH_CH0_REG. fields: - name: OUTFIFO_WDATA description: This register stores the data that need to be pushed into DMA FIFO. bit_offset: 0 bit_size: 9 - name: OUTFIFO_PUSH description: Set this bit to push data into DMA FIFO. bit_offset: 9 bit_size: 1 fieldset/OUT_PUSH_CH1: description: DMA_OUT_PUSH_CH1_REG. fields: - name: OUTFIFO_WDATA description: This register stores the data that need to be pushed into DMA FIFO. bit_offset: 0 bit_size: 9 - name: OUTFIFO_PUSH description: Set this bit to push data into DMA FIFO. bit_offset: 9 bit_size: 1 fieldset/OUT_PUSH_CH2: description: DMA_OUT_PUSH_CH2_REG. fields: - name: OUTFIFO_WDATA description: This register stores the data that need to be pushed into DMA FIFO. bit_offset: 0 bit_size: 9 - name: OUTFIFO_PUSH description: Set this bit to push data into DMA FIFO. bit_offset: 9 bit_size: 1 fieldset/OUT_STATE_CH0: description: DMA_OUT_STATE_CH0_REG. fields: - name: OUTLINK_DSCR_ADDR description: This register stores the current outlink descriptor's address. bit_offset: 0 bit_size: 18 - name: OUT_DSCR_STATE description: reserved. bit_offset: 18 bit_size: 2 - name: OUT_STATE description: reserved. bit_offset: 20 bit_size: 3 fieldset/OUT_STATE_CH1: description: DMA_OUT_STATE_CH1_REG. fields: - name: OUTLINK_DSCR_ADDR description: This register stores the current outlink descriptor's address. bit_offset: 0 bit_size: 18 - name: OUT_DSCR_STATE description: reserved. bit_offset: 18 bit_size: 2 - name: OUT_STATE description: reserved. bit_offset: 20 bit_size: 3 fieldset/OUT_STATE_CH2: description: DMA_OUT_STATE_CH2_REG. fields: - name: OUTLINK_DSCR_ADDR description: This register stores the current outlink descriptor's address. bit_offset: 0 bit_size: 18 - name: OUT_DSCR_STATE description: reserved. bit_offset: 18 bit_size: 2 - name: OUT_STATE description: reserved. bit_offset: 20 bit_size: 3