block/UART0: description: UART (Universal Asynchronous Receiver-Transmitter) Controller 0. items: - name: FIFO byte_offset: 0 fieldset: FIFO - name: INT_RAW byte_offset: 4 fieldset: INT_RAW - name: INT_ST byte_offset: 8 fieldset: INT_ST - name: INT_ENA byte_offset: 12 fieldset: INT_ENA - name: INT_CLR byte_offset: 16 fieldset: INT_CLR - name: CLKDIV byte_offset: 20 fieldset: CLKDIV - name: AUTOBAUD byte_offset: 24 fieldset: AUTOBAUD - name: STATUS byte_offset: 28 fieldset: STATUS - name: CONF0 byte_offset: 32 fieldset: CONF0 - name: CONF1 byte_offset: 36 fieldset: CONF1 - name: LOWPULSE byte_offset: 40 fieldset: LOWPULSE - name: HIGHPULSE byte_offset: 44 fieldset: HIGHPULSE - name: RXD_CNT byte_offset: 48 fieldset: RXD_CNT - name: FLOW_CONF byte_offset: 52 fieldset: FLOW_CONF - name: SLEEP_CONF byte_offset: 56 fieldset: SLEEP_CONF - name: SWFC_CONF byte_offset: 60 fieldset: SWFC_CONF - name: IDLE_CONF byte_offset: 64 fieldset: IDLE_CONF - name: RS485_CONF byte_offset: 68 fieldset: RS485_CONF - name: AT_CMD_PRECNT byte_offset: 72 fieldset: AT_CMD_PRECNT - name: AT_CMD_POSTCNT byte_offset: 76 fieldset: AT_CMD_POSTCNT - name: AT_CMD_GAPTOUT byte_offset: 80 fieldset: AT_CMD_GAPTOUT - name: AT_CMD_CHAR byte_offset: 84 fieldset: AT_CMD_CHAR - name: MEM_CONF byte_offset: 88 fieldset: MEM_CONF - name: MEM_TX_STATUS byte_offset: 92 fieldset: MEM_TX_STATUS - name: MEM_RX_STATUS byte_offset: 96 fieldset: MEM_RX_STATUS - name: MEM_CNT_STATUS byte_offset: 100 fieldset: MEM_CNT_STATUS - name: POSPULSE byte_offset: 104 fieldset: POSPULSE - name: NEGPULSE byte_offset: 108 fieldset: NEGPULSE - name: DATE byte_offset: 120 fieldset: DATE - name: ID byte_offset: 124 fieldset: ID fieldset/AT_CMD_CHAR: fields: - name: AT_CMD_CHAR description: This register is used to configure the content of at_cmd char. bit_offset: 0 bit_size: 8 - name: CHAR_NUM description: This register is used to configure the num of continous at_cmd chars received by receiver. bit_offset: 8 bit_size: 8 fieldset/AT_CMD_GAPTOUT: fields: - name: RX_GAP_TOUT description: This register is used to configure the duration time between the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars. bit_offset: 0 bit_size: 24 fieldset/AT_CMD_POSTCNT: fields: - name: POST_IDLE_NUM description: This register is used to configure the duration time between the last at_cmd and the next data. when the duration is less than this register value it will not take the previous data as at_cmd char. bit_offset: 0 bit_size: 24 fieldset/AT_CMD_PRECNT: fields: - name: PRE_IDLE_NUM description: This register is used to configure the idle duration time before the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char. bit_offset: 0 bit_size: 24 fieldset/AUTOBAUD: fields: - name: EN description: This is the enable bit for detecting baudrate. bit_offset: 0 bit_size: 1 - name: GLITCH_FILT description: when input pulse width is lower then this value igore this pulse.this register is used in autobaud detect process. bit_offset: 8 bit_size: 8 fieldset/CLKDIV: fields: - name: CLKDIV description: The register value is the integer part of the frequency divider's factor. bit_offset: 0 bit_size: 20 - name: FRAG description: The register value is the decimal part of the frequency divider's factor. bit_offset: 20 bit_size: 4 fieldset/CONF0: fields: - name: PARITY description: This register is used to configure the parity check mode. 0:even 1:odd. bit_offset: 0 bit_size: 1 - name: PARITY_EN description: Set this bit to enable uart parity check. bit_offset: 1 bit_size: 1 - name: BIT_NUM description: 'This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits.' bit_offset: 2 bit_size: 2 - name: STOP_BIT_NUM description: This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits. bit_offset: 4 bit_size: 2 - name: SW_RTS description: This register is used to configure the software rts signal which is used in software flow control. bit_offset: 6 bit_size: 1 - name: SW_DTR description: This register is used to configure the software dtr signal which is used in software flow control.. bit_offset: 7 bit_size: 1 - name: TXD_BRK description: Set this bit to enbale transmitter to send 0 when the process of sending data is done. bit_offset: 8 bit_size: 1 - name: IRDA_DPLX description: Set this bit to enable irda loopback mode. bit_offset: 9 bit_size: 1 - name: IRDA_TX_EN description: This is the start enable bit for irda transmitter. bit_offset: 10 bit_size: 1 - name: IRDA_WCTL description: 1.the irda transmitter's 11th bit is the same to the 10th bit. 0.set irda transmitter's 11th bit to 0. bit_offset: 11 bit_size: 1 - name: IRDA_TX_INV description: Set this bit to inverse the level value of irda transmitter's level. bit_offset: 12 bit_size: 1 - name: IRDA_RX_INV description: Set this bit to inverse the level value of irda receiver's level. bit_offset: 13 bit_size: 1 - name: LOOPBACK description: Set this bit to enable uart loopback test mode. bit_offset: 14 bit_size: 1 - name: TX_FLOW_EN description: Set this bit to enable transmitter's flow control function. bit_offset: 15 bit_size: 1 - name: IRDA_EN description: Set this bit to enable irda protocol. bit_offset: 16 bit_size: 1 - name: RXFIFO_RST description: Set this bit to reset uart receiver's fifo. bit_offset: 17 bit_size: 1 - name: TXFIFO_RST description: Set this bit to reset uart transmitter's fifo. bit_offset: 18 bit_size: 1 - name: RXD_INV description: Set this bit to inverse the level value of uart rxd signal. bit_offset: 19 bit_size: 1 - name: CTS_INV description: Set this bit to inverse the level value of uart cts signal. bit_offset: 20 bit_size: 1 - name: DSR_INV description: Set this bit to inverse the level value of uart dsr signal. bit_offset: 21 bit_size: 1 - name: TXD_INV description: Set this bit to inverse the level value of uart txd signal. bit_offset: 22 bit_size: 1 - name: RTS_INV description: Set this bit to inverse the level value of uart rts signal. bit_offset: 23 bit_size: 1 - name: DTR_INV description: Set this bit to inverse the level value of uart dtr signal. bit_offset: 24 bit_size: 1 - name: CLK_EN description: 1.force clock on for registers.support clock only when write registers. bit_offset: 25 bit_size: 1 - name: ERR_WR_MASK description: 1.receiver stops storing data int fifo when data is wrong. 0.receiver stores the data even if the received data is wrong. bit_offset: 26 bit_size: 1 - name: TICK_REF_ALWAYS_ON description: This register is used to select the clock.1.apb clock 0:ref_tick. bit_offset: 27 bit_size: 1 fieldset/CONF1: fields: - name: RXFIFO_FULL_THRHD description: When receiver receives more data than its threshold value.receiver will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd). bit_offset: 0 bit_size: 7 - name: TXFIFO_EMPTY_THRHD description: when the data amount in transmitter fifo is less than its threshold value. it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd). bit_offset: 8 bit_size: 7 - name: RX_FLOW_THRHD description: when receiver receives more data than its threshold value. receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd). bit_offset: 16 bit_size: 7 - name: RX_FLOW_EN description: This is the flow enable bit for uart receiver. 1:choose software flow control with configuring sw_rts signal. bit_offset: 23 bit_size: 1 - name: RX_TOUT_THRHD description: This register is used to configure the timeout value for uart receiver receiving a byte. bit_offset: 24 bit_size: 7 - name: RX_TOUT_EN description: This is the enble bit for uart receiver's timeout function. bit_offset: 31 bit_size: 1 fieldset/DATE: fields: - name: DATE bit_offset: 0 bit_size: 32 fieldset/FIFO: fields: - name: RXFIFO_RD_BYTE description: This register stores one byte data read by rx fifo. bit_offset: 0 bit_size: 8 fieldset/FLOW_CONF: fields: - name: SW_FLOW_CON_EN description: Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff. bit_offset: 0 bit_size: 1 - name: XONOFF_DEL description: Set this bit to remove flow control char from the received data. bit_offset: 1 bit_size: 1 - name: FORCE_XON description: Set this bit to clear ctsn to stop the transmitter from sending data. bit_offset: 2 bit_size: 1 - name: FORCE_XOFF description: Set this bit to set ctsn to enable the transmitter to go on sending data. bit_offset: 3 bit_size: 1 - name: SEND_XON description: Set this bit to send xon char. it is cleared by hardware automatically. bit_offset: 4 bit_size: 1 - name: SEND_XOFF description: Set this bit to send xoff char. it is cleared by hardware automatically. bit_offset: 5 bit_size: 1 fieldset/HIGHPULSE: fields: - name: MIN_CNT description: This register stores the value of the maxinum duration time for the high level pulse. it is used in baudrate-detect process. bit_offset: 0 bit_size: 20 fieldset/ID: fields: - name: ID bit_offset: 0 bit_size: 32 fieldset/IDLE_CONF: fields: - name: RX_IDLE_THRHD description: when receiver takes more time than this register value to receive a byte data. it will produce frame end signal for uhci to stop receiving data. bit_offset: 0 bit_size: 10 - name: TX_IDLE_NUM description: This register is used to configure the duration time between transfers. bit_offset: 10 bit_size: 10 - name: TX_BRK_NUM description: This register is used to configure the num of 0 send after the process of sending data is done. it is active when txd_brk is set to 1. bit_offset: 20 bit_size: 8 fieldset/INT_CLR: fields: - name: RXFIFO_FULL_INT_CLR description: Set this bit to clear the rxfifo_full_int_raw interrupt. bit_offset: 0 bit_size: 1 - name: TXFIFO_EMPTY_INT_CLR description: Set this bit to clear txfifo_empty_int_raw interrupt. bit_offset: 1 bit_size: 1 - name: PARITY_ERR_INT_CLR description: Set this bit to clear parity_err_int_raw interrupt. bit_offset: 2 bit_size: 1 - name: FRM_ERR_INT_CLR description: Set this bit to clear frm_err_int_raw interrupt. bit_offset: 3 bit_size: 1 - name: RXFIFO_OVF_INT_CLR description: Set this bit to clear rxfifo_ovf_int_raw interrupt. bit_offset: 4 bit_size: 1 - name: DSR_CHG_INT_CLR description: Set this bit to clear the dsr_chg_int_raw interrupt. bit_offset: 5 bit_size: 1 - name: CTS_CHG_INT_CLR description: Set this bit to clear the cts_chg_int_raw interrupt. bit_offset: 6 bit_size: 1 - name: BRK_DET_INT_CLR description: Set this bit to clear the brk_det_int_raw interrupt. bit_offset: 7 bit_size: 1 - name: RXFIFO_TOUT_INT_CLR description: Set this bit to clear the rxfifo_tout_int_raw interrupt. bit_offset: 8 bit_size: 1 - name: SW_XON_INT_CLR description: Set this bit to clear the sw_xon_int_raw interrupt. bit_offset: 9 bit_size: 1 - name: SW_XOFF_INT_CLR description: Set this bit to clear the sw_xon_int_raw interrupt. bit_offset: 10 bit_size: 1 - name: GLITCH_DET_INT_CLR description: Set this bit to clear the glitch_det_int_raw interrupt. bit_offset: 11 bit_size: 1 - name: TX_BRK_DONE_INT_CLR description: Set this bit to clear the tx_brk_done_int_raw interrupt.. bit_offset: 12 bit_size: 1 - name: TX_BRK_IDLE_DONE_INT_CLR description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt. bit_offset: 13 bit_size: 1 - name: TX_DONE_INT_CLR description: Set this bit to clear the tx_done_int_raw interrupt. bit_offset: 14 bit_size: 1 - name: RS485_PARITY_ERR_INT_CLR description: Set this bit to clear the rs485_parity_err_int_raw interrupt. bit_offset: 15 bit_size: 1 - name: RS485_FRM_ERR_INT_CLR description: Set this bit to clear the rs485_frm_err_int_raw interrupt. bit_offset: 16 bit_size: 1 - name: RS485_CLASH_INT_CLR description: Set this bit to clear the rs485_clash_int_raw interrupt. bit_offset: 17 bit_size: 1 - name: AT_CMD_CHAR_DET_INT_CLR description: Set this bit to clear the at_cmd_char_det_int_raw interrupt. bit_offset: 18 bit_size: 1 fieldset/INT_ENA: fields: - name: RXFIFO_FULL_INT_ENA description: This is the enable bit for rxfifo_full_int_st register. bit_offset: 0 bit_size: 1 - name: TXFIFO_EMPTY_INT_ENA description: This is the enable bit for rxfifo_full_int_st register. bit_offset: 1 bit_size: 1 - name: PARITY_ERR_INT_ENA description: This is the enable bit for parity_err_int_st register. bit_offset: 2 bit_size: 1 - name: FRM_ERR_INT_ENA description: This is the enable bit for frm_err_int_st register. bit_offset: 3 bit_size: 1 - name: RXFIFO_OVF_INT_ENA description: This is the enable bit for rxfifo_ovf_int_st register. bit_offset: 4 bit_size: 1 - name: DSR_CHG_INT_ENA description: This is the enable bit for dsr_chg_int_st register. bit_offset: 5 bit_size: 1 - name: CTS_CHG_INT_ENA description: This is the enable bit for cts_chg_int_st register. bit_offset: 6 bit_size: 1 - name: BRK_DET_INT_ENA description: This is the enable bit for brk_det_int_st register. bit_offset: 7 bit_size: 1 - name: RXFIFO_TOUT_INT_ENA description: This is the enable bit for rxfifo_tout_int_st register. bit_offset: 8 bit_size: 1 - name: SW_XON_INT_ENA description: This is the enable bit for sw_xon_int_st register. bit_offset: 9 bit_size: 1 - name: SW_XOFF_INT_ENA description: This is the enable bit for sw_xoff_int_st register. bit_offset: 10 bit_size: 1 - name: GLITCH_DET_INT_ENA description: This is the enable bit for glitch_det_int_st register. bit_offset: 11 bit_size: 1 - name: TX_BRK_DONE_INT_ENA description: This is the enable bit for tx_brk_done_int_st register. bit_offset: 12 bit_size: 1 - name: TX_BRK_IDLE_DONE_INT_ENA description: This is the enable bit for tx_brk_idle_done_int_st register. bit_offset: 13 bit_size: 1 - name: TX_DONE_INT_ENA description: This is the enable bit for tx_done_int_st register. bit_offset: 14 bit_size: 1 - name: RS485_PARITY_ERR_INT_ENA description: This is the enable bit for rs485_parity_err_int_st register. bit_offset: 15 bit_size: 1 - name: RS485_FRM_ERR_INT_ENA description: This is the enable bit for rs485_parity_err_int_st register. bit_offset: 16 bit_size: 1 - name: RS485_CLASH_INT_ENA description: This is the enable bit for rs485_clash_int_st register. bit_offset: 17 bit_size: 1 - name: AT_CMD_CHAR_DET_INT_ENA description: This is the enable bit for at_cmd_char_det_int_st register. bit_offset: 18 bit_size: 1 fieldset/INT_RAW: fields: - name: RXFIFO_FULL_INT_RAW description: This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd). bit_offset: 0 bit_size: 1 - name: TXFIFO_EMPTY_INT_RAW description: This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt). bit_offset: 1 bit_size: 1 - name: PARITY_ERR_INT_RAW description: This interrupt raw bit turns to high level when receiver detects the parity error of data. bit_offset: 2 bit_size: 1 - name: FRM_ERR_INT_RAW description: This interrupt raw bit turns to high level when receiver detects data's frame error. bit_offset: 3 bit_size: 1 - name: RXFIFO_OVF_INT_RAW description: This interrupt raw bit turns to high level when receiver receives more data than the fifo can store. bit_offset: 4 bit_size: 1 - name: DSR_CHG_INT_RAW description: This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal. bit_offset: 5 bit_size: 1 - name: CTS_CHG_INT_RAW description: This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal. bit_offset: 6 bit_size: 1 - name: BRK_DET_INT_RAW description: This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit. bit_offset: 7 bit_size: 1 - name: RXFIFO_TOUT_INT_RAW description: This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. bit_offset: 8 bit_size: 1 - name: SW_XON_INT_RAW description: This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1. bit_offset: 9 bit_size: 1 - name: SW_XOFF_INT_RAW description: This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1. bit_offset: 10 bit_size: 1 - name: GLITCH_DET_INT_RAW description: This interrupt raw bit turns to high level when receiver detects the start bit. bit_offset: 11 bit_size: 1 - name: TX_BRK_DONE_INT_RAW description: This interrupt raw bit turns to high level when transmitter completes sendding 0 after all the datas in transmitter's fifo are send. bit_offset: 12 bit_size: 1 - name: TX_BRK_IDLE_DONE_INT_RAW description: This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send. bit_offset: 13 bit_size: 1 - name: TX_DONE_INT_RAW description: This interrupt raw bit turns to high level when transmitter has send all the data in fifo. bit_offset: 14 bit_size: 1 - name: RS485_PARITY_ERR_INT_RAW description: This interrupt raw bit turns to high level when rs485 detects the parity error. bit_offset: 15 bit_size: 1 - name: RS485_FRM_ERR_INT_RAW description: This interrupt raw bit turns to high level when rs485 detects the data frame error. bit_offset: 16 bit_size: 1 - name: RS485_CLASH_INT_RAW description: This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver. bit_offset: 17 bit_size: 1 - name: AT_CMD_CHAR_DET_INT_RAW description: This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars. bit_offset: 18 bit_size: 1 fieldset/INT_ST: fields: - name: RXFIFO_FULL_INT_ST description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. bit_offset: 0 bit_size: 1 - name: TXFIFO_EMPTY_INT_ST description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. bit_offset: 1 bit_size: 1 - name: PARITY_ERR_INT_ST description: This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. bit_offset: 2 bit_size: 1 - name: FRM_ERR_INT_ST description: This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1. bit_offset: 3 bit_size: 1 - name: RXFIFO_OVF_INT_ST description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. bit_offset: 4 bit_size: 1 - name: DSR_CHG_INT_ST description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. bit_offset: 5 bit_size: 1 - name: CTS_CHG_INT_ST description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. bit_offset: 6 bit_size: 1 - name: BRK_DET_INT_ST description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. bit_offset: 7 bit_size: 1 - name: RXFIFO_TOUT_INT_ST description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. bit_offset: 8 bit_size: 1 - name: SW_XON_INT_ST description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. bit_offset: 9 bit_size: 1 - name: SW_XOFF_INT_ST description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. bit_offset: 10 bit_size: 1 - name: GLITCH_DET_INT_ST description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. bit_offset: 11 bit_size: 1 - name: TX_BRK_DONE_INT_ST description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. bit_offset: 12 bit_size: 1 - name: TX_BRK_IDLE_DONE_INT_ST description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. bit_offset: 13 bit_size: 1 - name: TX_DONE_INT_ST description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. bit_offset: 14 bit_size: 1 - name: RS485_PARITY_ERR_INT_ST description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. bit_offset: 15 bit_size: 1 - name: RS485_FRM_ERR_INT_ST description: This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1. bit_offset: 16 bit_size: 1 - name: RS485_CLASH_INT_ST description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. bit_offset: 17 bit_size: 1 - name: AT_CMD_CHAR_DET_INT_ST description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. bit_offset: 18 bit_size: 1 fieldset/LOWPULSE: fields: - name: MIN_CNT description: This register stores the value of the minimum duration time for the low level pulse. it is used in baudrate-detect process. bit_offset: 0 bit_size: 20 fieldset/MEM_CNT_STATUS: fields: - name: RX_MEM_CNT description: Refer to the rxfifo_cnt's description. bit_offset: 0 bit_size: 3 - name: TX_MEM_CNT description: Refer to the txfifo_cnt's description. bit_offset: 3 bit_size: 3 fieldset/MEM_CONF: fields: - name: MEM_PD description: Set this bit to power down mem.when reg_mem_pd registers in the 3 uarts are all set to 1 mem will enter low power mode. bit_offset: 0 bit_size: 1 - name: RX_SIZE description: This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128. bit_offset: 3 bit_size: 4 - name: TX_SIZE description: This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128. bit_offset: 7 bit_size: 4 - name: RX_FLOW_THRHD_H3 description: Refer to the rx_flow_thrhd's description. bit_offset: 15 bit_size: 3 - name: RX_TOUT_THRHD_H3 description: Refer to the rx_tout_thrhd's description. bit_offset: 18 bit_size: 3 - name: XON_THRESHOLD_H2 description: Refer to the uart_xon_threshold's description. bit_offset: 21 bit_size: 2 - name: XOFF_THRESHOLD_H2 description: Refer to the uart_xoff_threshold's description. bit_offset: 23 bit_size: 2 - name: RX_MEM_FULL_THRHD description: Refer to the rxfifo_full_thrhd's description. bit_offset: 25 bit_size: 3 - name: TX_MEM_EMPTY_THRHD description: Refer to txfifo_empty_thrhd's description. bit_offset: 28 bit_size: 3 fieldset/MEM_RX_STATUS: fields: - name: MEM_RX_STATUS description: This register stores the current uart rx mem read address and rx mem write address. bit_offset: 0 bit_size: 24 - name: MEM_RX_RD_ADDR description: This register stores the rx mem read address. bit_offset: 2 bit_size: 11 - name: MEM_RX_WR_ADDR description: This register stores the rx mem write address. bit_offset: 13 bit_size: 11 fieldset/MEM_TX_STATUS: fields: - name: MEM_TX_STATUS bit_offset: 0 bit_size: 24 fieldset/NEGPULSE: fields: - name: NEGEDGE_MIN_CNT description: This register stores the count of rxd negedge edge. it is used in boudrate-detect process. bit_offset: 0 bit_size: 20 fieldset/POSPULSE: fields: - name: POSEDGE_MIN_CNT description: This register stores the count of rxd posedge edge. it is used in boudrate-detect process. bit_offset: 0 bit_size: 20 fieldset/RS485_CONF: fields: - name: RS485_EN description: Set this bit to choose rs485 mode. bit_offset: 0 bit_size: 1 - name: DL0_EN description: Set this bit to delay the stop bit by 1 bit. bit_offset: 1 bit_size: 1 - name: DL1_EN description: Set this bit to delay the stop bit by 1 bit. bit_offset: 2 bit_size: 1 - name: RS485TX_RX_EN description: Set this bit to enable loopback transmitter's output data signal to receiver's input data signal. bit_offset: 3 bit_size: 1 - name: RS485RXBY_TX_EN description: '1: enable rs485''s transmitter to send data when rs485''s receiver is busy. 0:rs485''s transmitter should not send data when its receiver is busy.' bit_offset: 4 bit_size: 1 - name: RS485_RX_DLY_NUM description: This register is used to delay the receiver's internal data signal. bit_offset: 5 bit_size: 1 - name: RS485_TX_DLY_NUM description: This register is used to delay the transmitter's internal data signal. bit_offset: 6 bit_size: 4 fieldset/RXD_CNT: fields: - name: RXD_EDGE_CNT description: This register stores the count of rxd edge change. it is used in baudrate-detect process. bit_offset: 0 bit_size: 10 fieldset/SLEEP_CONF: fields: - name: ACTIVE_THRESHOLD description: When the input rxd edge changes more than this register value. the uart is active from light sleeping mode. bit_offset: 0 bit_size: 10 fieldset/STATUS: fields: - name: RXFIFO_CNT description: (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits. bit_offset: 0 bit_size: 8 - name: ST_URX_OUT description: This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1. bit_offset: 8 bit_size: 4 - name: DSRN description: This register stores the level value of the internal uart dsr signal. bit_offset: 13 bit_size: 1 - name: CTSN description: This register stores the level value of the internal uart cts signal. bit_offset: 14 bit_size: 1 - name: RXD description: This register stores the level value of the internal uart rxd signal. bit_offset: 15 bit_size: 1 - name: TXFIFO_CNT description: (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits. bit_offset: 16 bit_size: 8 - name: ST_UTX_OUT description: This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1. bit_offset: 24 bit_size: 4 - name: DTRN description: The register represent the level value of the internal uart dsr signal. bit_offset: 29 bit_size: 1 - name: RTSN description: This register represent the level value of the internal uart cts signal. bit_offset: 30 bit_size: 1 - name: TXD description: This register represent the level value of the internal uart rxd signal. bit_offset: 31 bit_size: 1 fieldset/SWFC_CONF: fields: - name: XON_THRESHOLD description: when the data amount in receiver's fifo is more than this register value. it will send a xoff char with uart_sw_flow_con_en set to 1. bit_offset: 0 bit_size: 8 - name: XOFF_THRESHOLD description: When the data amount in receiver's fifo is less than this register value. it will send a xon char with uart_sw_flow_con_en set to 1. bit_offset: 8 bit_size: 8 - name: XON_CHAR description: This register stores the xon flow control char. bit_offset: 16 bit_size: 8 - name: XOFF_CHAR description: This register stores the xoff flow control char. bit_offset: 24 bit_size: 8