block/SPI0: description: SPI (Serial Peripheral Interface) Controller 0. items: - name: CMD byte_offset: 0 fieldset: CMD - name: ADDR byte_offset: 4 - name: CTRL byte_offset: 8 fieldset: CTRL - name: CTRL1 byte_offset: 12 fieldset: CTRL1 - name: RD_STATUS byte_offset: 16 fieldset: RD_STATUS - name: CTRL2 byte_offset: 20 fieldset: CTRL2 - name: CLOCK byte_offset: 24 fieldset: CLOCK - name: USER byte_offset: 28 fieldset: USER - name: USER1 byte_offset: 32 fieldset: USER1 - name: USER2 byte_offset: 36 fieldset: USER2 - name: MOSI_DLEN byte_offset: 40 fieldset: MOSI_DLEN - name: MISO_DLEN byte_offset: 44 fieldset: MISO_DLEN - name: SLV_WR_STATUS byte_offset: 48 fieldset: SLV_WR_STATUS - name: PIN byte_offset: 52 fieldset: PIN - name: SLAVE byte_offset: 56 fieldset: SLAVE - name: SLAVE1 byte_offset: 60 fieldset: SLAVE1 - name: SLAVE2 byte_offset: 64 fieldset: SLAVE2 - name: SLAVE3 byte_offset: 68 fieldset: SLAVE3 - name: SLV_WRBUF_DLEN byte_offset: 72 fieldset: SLV_WRBUF_DLEN - name: SLV_RDBUF_DLEN byte_offset: 76 fieldset: SLV_RDBUF_DLEN - name: CACHE_FCTRL byte_offset: 80 fieldset: CACHE_FCTRL - name: CACHE_SCTRL byte_offset: 84 fieldset: CACHE_SCTRL - name: SRAM_CMD byte_offset: 88 fieldset: SRAM_CMD - name: SRAM_DRD_CMD byte_offset: 92 fieldset: SRAM_DRD_CMD - name: SRAM_DWR_CMD byte_offset: 96 fieldset: SRAM_DWR_CMD - name: SLV_RD_BIT byte_offset: 100 fieldset: SLV_RD_BIT - name: W0 byte_offset: 128 fieldset: W0 - name: W1 byte_offset: 132 fieldset: W1 - name: W2 byte_offset: 136 fieldset: W2 - name: W3 byte_offset: 140 fieldset: W3 - name: W4 byte_offset: 144 fieldset: W4 - name: W5 byte_offset: 148 fieldset: W5 - name: W6 byte_offset: 152 fieldset: W6 - name: W7 byte_offset: 156 fieldset: W7 - name: W8 byte_offset: 160 fieldset: W8 - name: W9 byte_offset: 164 fieldset: W9 - name: W10 byte_offset: 168 fieldset: W10 - name: W11 byte_offset: 172 fieldset: W11 - name: W12 byte_offset: 176 fieldset: W12 - name: W13 byte_offset: 180 fieldset: W13 - name: W14 byte_offset: 184 fieldset: W14 - name: W15 byte_offset: 188 fieldset: W15 - name: TX_CRC byte_offset: 192 fieldset: TX_CRC - name: EXT0 byte_offset: 240 fieldset: EXT0 - name: EXT1 byte_offset: 244 fieldset: EXT1 - name: EXT2 byte_offset: 248 fieldset: EXT2 - name: EXT3 byte_offset: 252 fieldset: EXT3 - name: DMA_CONF byte_offset: 256 fieldset: DMA_CONF - name: DMA_OUT_LINK byte_offset: 260 fieldset: DMA_OUT_LINK - name: DMA_IN_LINK byte_offset: 264 fieldset: DMA_IN_LINK - name: DMA_STATUS byte_offset: 268 fieldset: DMA_STATUS - name: DMA_INT_ENA byte_offset: 272 fieldset: DMA_INT_ENA - name: DMA_INT_RAW byte_offset: 276 fieldset: DMA_INT_RAW - name: DMA_INT_ST byte_offset: 280 fieldset: DMA_INT_ST - name: DMA_INT_CLR byte_offset: 284 fieldset: DMA_INT_CLR - name: IN_ERR_EOF_DES_ADDR byte_offset: 288 fieldset: IN_ERR_EOF_DES_ADDR - name: IN_SUC_EOF_DES_ADDR byte_offset: 292 fieldset: IN_SUC_EOF_DES_ADDR - name: INLINK_DSCR byte_offset: 296 fieldset: INLINK_DSCR - name: INLINK_DSCR_BF0 byte_offset: 300 fieldset: INLINK_DSCR_BF0 - name: INLINK_DSCR_BF1 byte_offset: 304 fieldset: INLINK_DSCR_BF1 - name: OUT_EOF_BFR_DES_ADDR byte_offset: 308 fieldset: OUT_EOF_BFR_DES_ADDR - name: OUT_EOF_DES_ADDR byte_offset: 312 fieldset: OUT_EOF_DES_ADDR - name: OUTLINK_DSCR byte_offset: 316 fieldset: OUTLINK_DSCR - name: OUTLINK_DSCR_BF0 byte_offset: 320 fieldset: OUTLINK_DSCR_BF0 - name: OUTLINK_DSCR_BF1 byte_offset: 324 fieldset: OUTLINK_DSCR_BF1 - name: DMA_RSTATUS byte_offset: 328 fieldset: DMA_RSTATUS - name: DMA_TSTATUS byte_offset: 332 fieldset: DMA_TSTATUS - name: DATE byte_offset: 1020 fieldset: DATE fieldset/CACHE_FCTRL: fields: - name: CACHE_REQ_EN description: 'For SPI0 Cache access enable 1: enable 0:disable.' bit_offset: 0 bit_size: 1 - name: CACHE_USR_CMD_4BYTE description: 'For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.' bit_offset: 1 bit_size: 1 - name: CACHE_FLASH_USR_CMD description: 'For SPI0 cache read flash for user define command 1: enable 0:disable.' bit_offset: 2 bit_size: 1 - name: CACHE_FLASH_PES_EN description: 'For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable.' bit_offset: 3 bit_size: 1 fieldset/CACHE_SCTRL: fields: - name: USR_SRAM_DIO description: 'For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable.' bit_offset: 1 bit_size: 1 - name: USR_SRAM_QIO description: 'For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable.' bit_offset: 2 bit_size: 1 - name: USR_WR_SRAM_DUMMY description: For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations. bit_offset: 3 bit_size: 1 - name: USR_RD_SRAM_DUMMY description: For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations. bit_offset: 4 bit_size: 1 - name: CACHE_SRAM_USR_RCMD description: For SPI0 In the spi sram mode cache read sram for user define command. bit_offset: 5 bit_size: 1 - name: SRAM_BYTES_LEN description: For SPI0 In the sram mode it is the byte length of spi read sram data. bit_offset: 6 bit_size: 8 - name: SRAM_DUMMY_CYCLELEN description: For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1). bit_offset: 14 bit_size: 8 - name: SRAM_ADDR_BITLEN description: For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1). bit_offset: 22 bit_size: 6 - name: CACHE_SRAM_USR_WCMD description: For SPI0 In the spi sram mode cache write sram for user define command. bit_offset: 28 bit_size: 1 fieldset/CLOCK: fields: - name: CLKCNT_L description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. bit_offset: 0 bit_size: 6 - name: CLKCNT_H description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. bit_offset: 6 bit_size: 6 - name: CLKCNT_N description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). bit_offset: 12 bit_size: 6 - name: CLKDIV_PRE description: In the master mode it is pre-divider of spi_clk. bit_offset: 18 bit_size: 13 - name: CLK_EQU_SYSCLK description: 'In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.' bit_offset: 31 bit_size: 1 fieldset/CMD: fields: - name: FLASH_PER description: 'program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.' bit_offset: 16 bit_size: 1 - name: FLASH_PES description: 'program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.' bit_offset: 17 bit_size: 1 - name: USR description: 'User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.' bit_offset: 18 bit_size: 1 - name: FLASH_HPM description: 'Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.' bit_offset: 19 bit_size: 1 - name: FLASH_RES description: 'This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.' bit_offset: 20 bit_size: 1 - name: FLASH_DP description: 'Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.' bit_offset: 21 bit_size: 1 - name: FLASH_CE description: 'Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.' bit_offset: 22 bit_size: 1 - name: FLASH_BE description: 'Block erase enable. A 64KB block is erased via SPI command D8H. Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.' bit_offset: 23 bit_size: 1 - name: FLASH_SE description: 'Sector erase enable. A 4KB sector is erased via SPI command 20H. Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.' bit_offset: 24 bit_size: 1 - name: FLASH_PP description: 'Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.' bit_offset: 25 bit_size: 1 - name: FLASH_WRSR description: 'Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.' bit_offset: 26 bit_size: 1 - name: FLASH_RDSR description: 'Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.' bit_offset: 27 bit_size: 1 - name: FLASH_RDID description: 'Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.' bit_offset: 28 bit_size: 1 - name: FLASH_WRDI description: 'Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.' bit_offset: 29 bit_size: 1 - name: FLASH_WREN description: 'Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.' bit_offset: 30 bit_size: 1 - name: FLASH_READ description: 'Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.' bit_offset: 31 bit_size: 1 fieldset/CTRL: fields: - name: FCS_CRC_EN description: For SPI1 initialize crc32 module before writing encrypted data to flash. Active low. bit_offset: 10 bit_size: 1 - name: TX_CRC_EN description: 'For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable.' bit_offset: 11 bit_size: 1 - name: WAIT_FLASH_IDLE_EN description: 'wait flash idle when program flash or erase flash. 1: enable 0: disable.' bit_offset: 12 bit_size: 1 - name: FASTRD_MODE description: 'This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable.' bit_offset: 13 bit_size: 1 - name: FREAD_DUAL description: 'In the read operations read-data phase apply 2 signals. 1: enable 0: disable.' bit_offset: 14 bit_size: 1 - name: RESANDRES description: 'The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable.' bit_offset: 15 bit_size: 1 - name: FREAD_QUAD description: 'In the read operations read-data phase apply 4 signals. 1: enable 0: disable.' bit_offset: 20 bit_size: 1 - name: WP description: 'Write protect signal output when SPI is idle. 1: output high 0: output low.' bit_offset: 21 bit_size: 1 - name: WRSR_2B description: 'two bytes data will be written to status register when it is set. 1: enable 0: disable.' bit_offset: 22 bit_size: 1 - name: FREAD_DIO description: 'In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.' bit_offset: 23 bit_size: 1 - name: FREAD_QIO description: 'In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.' bit_offset: 24 bit_size: 1 - name: RD_BIT_ORDER description: 'In read-data (MISO) phase 1: LSB first 0: MSB first.' bit_offset: 25 bit_size: 1 - name: WR_BIT_ORDER description: 'In command address write-data (MOSI) phases 1: LSB firs 0: MSB first.' bit_offset: 26 bit_size: 1 fieldset/CTRL1: fields: - name: CS_HOLD_DELAY_RES description: Delay cycles of resume Flash when resume Flash is enable by spi clock. bit_offset: 16 bit_size: 12 - name: CS_HOLD_DELAY description: SPI cs signal is delayed by spi clock cycles. bit_offset: 28 bit_size: 4 fieldset/CTRL2: fields: - name: SETUP_TIME description: (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit. bit_offset: 0 bit_size: 4 - name: HOLD_TIME description: delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit. bit_offset: 4 bit_size: 4 - name: CK_OUT_LOW_MODE description: modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits. bit_offset: 8 bit_size: 4 - name: CK_OUT_HIGH_MODE description: modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits. bit_offset: 12 bit_size: 4 - name: MISO_DELAY_MODE description: 'MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle.' bit_offset: 16 bit_size: 2 - name: MISO_DELAY_NUM description: MISO signals are delayed by system clock cycles. bit_offset: 18 bit_size: 3 - name: MOSI_DELAY_MODE description: 'MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle.' bit_offset: 21 bit_size: 2 - name: MOSI_DELAY_NUM description: MOSI signals are delayed by system clock cycles. bit_offset: 23 bit_size: 3 - name: CS_DELAY_MODE description: 'spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle.' bit_offset: 26 bit_size: 2 - name: CS_DELAY_NUM description: spi_cs signal is delayed by system clock cycles. bit_offset: 28 bit_size: 4 fieldset/DATE: fields: - name: DATE description: SPI register version. bit_offset: 0 bit_size: 28 fieldset/DMA_CONF: fields: - name: IN_RST description: The bit is used to reset in dma fsm and in data fifo pointer. bit_offset: 2 bit_size: 1 - name: OUT_RST description: The bit is used to reset out dma fsm and out data fifo pointer. bit_offset: 3 bit_size: 1 - name: AHBM_FIFO_RST description: reset spi dma ahb master fifo pointer. bit_offset: 4 bit_size: 1 - name: AHBM_RST description: reset spi dma ahb master. bit_offset: 5 bit_size: 1 - name: IN_LOOP_TEST description: Set bit to test in link. bit_offset: 6 bit_size: 1 - name: OUT_LOOP_TEST description: Set bit to test out link. bit_offset: 7 bit_size: 1 - name: OUT_AUTO_WRBACK description: when the link is empty jump to next automatically. bit_offset: 8 bit_size: 1 - name: OUT_EOF_MODE description: 'out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo.' bit_offset: 9 bit_size: 1 - name: OUTDSCR_BURST_EN description: read descriptor use burst mode when read data for memory. bit_offset: 10 bit_size: 1 - name: INDSCR_BURST_EN description: read descriptor use burst mode when write data to memory. bit_offset: 11 bit_size: 1 - name: OUT_DATA_BURST_EN description: spi dma read data from memory in burst mode. bit_offset: 12 bit_size: 1 - name: DMA_RX_STOP description: spi dma read data stop when in continue tx/rx mode. bit_offset: 14 bit_size: 1 - name: DMA_TX_STOP description: spi dma write data stop when in continue tx/rx mode. bit_offset: 15 bit_size: 1 - name: DMA_CONTINUE description: spi dma continue tx/rx data. bit_offset: 16 bit_size: 1 fieldset/DMA_INT_CLR: fields: - name: INLINK_DSCR_EMPTY_INT_CLR description: The clear bit for lack of enough inlink descriptors. bit_offset: 0 bit_size: 1 - name: OUTLINK_DSCR_ERROR_INT_CLR description: The clear bit for outlink descriptor error. bit_offset: 1 bit_size: 1 - name: INLINK_DSCR_ERROR_INT_CLR description: The clear bit for inlink descriptor error. bit_offset: 2 bit_size: 1 - name: IN_DONE_INT_CLR description: The clear bit for completing usage of a inlink descriptor. bit_offset: 3 bit_size: 1 - name: IN_ERR_EOF_INT_CLR description: The clear bit for receiving error. bit_offset: 4 bit_size: 1 - name: IN_SUC_EOF_INT_CLR description: The clear bit for completing receiving all the packets from host. bit_offset: 5 bit_size: 1 - name: OUT_DONE_INT_CLR description: The clear bit for completing usage of a outlink descriptor. bit_offset: 6 bit_size: 1 - name: OUT_EOF_INT_CLR description: The clear bit for sending a packet to host done. bit_offset: 7 bit_size: 1 - name: OUT_TOTAL_EOF_INT_CLR description: The clear bit for sending all the packets to host done. bit_offset: 8 bit_size: 1 fieldset/DMA_INT_ENA: fields: - name: INLINK_DSCR_EMPTY_INT_ENA description: The enable bit for lack of enough inlink descriptors. bit_offset: 0 bit_size: 1 - name: OUTLINK_DSCR_ERROR_INT_ENA description: The enable bit for outlink descriptor error. bit_offset: 1 bit_size: 1 - name: INLINK_DSCR_ERROR_INT_ENA description: The enable bit for inlink descriptor error. bit_offset: 2 bit_size: 1 - name: IN_DONE_INT_ENA description: The enable bit for completing usage of a inlink descriptor. bit_offset: 3 bit_size: 1 - name: IN_ERR_EOF_INT_ENA description: The enable bit for receiving error. bit_offset: 4 bit_size: 1 - name: IN_SUC_EOF_INT_ENA description: The enable bit for completing receiving all the packets from host. bit_offset: 5 bit_size: 1 - name: OUT_DONE_INT_ENA description: The enable bit for completing usage of a outlink descriptor. bit_offset: 6 bit_size: 1 - name: OUT_EOF_INT_ENA description: The enable bit for sending a packet to host done. bit_offset: 7 bit_size: 1 - name: OUT_TOTAL_EOF_INT_ENA description: The enable bit for sending all the packets to host done. bit_offset: 8 bit_size: 1 fieldset/DMA_INT_RAW: fields: - name: INLINK_DSCR_EMPTY_INT_RAW description: The raw bit for lack of enough inlink descriptors. bit_offset: 0 bit_size: 1 - name: OUTLINK_DSCR_ERROR_INT_RAW description: The raw bit for outlink descriptor error. bit_offset: 1 bit_size: 1 - name: INLINK_DSCR_ERROR_INT_RAW description: The raw bit for inlink descriptor error. bit_offset: 2 bit_size: 1 - name: IN_DONE_INT_RAW description: The raw bit for completing usage of a inlink descriptor. bit_offset: 3 bit_size: 1 - name: IN_ERR_EOF_INT_RAW description: The raw bit for receiving error. bit_offset: 4 bit_size: 1 - name: IN_SUC_EOF_INT_RAW description: The raw bit for completing receiving all the packets from host. bit_offset: 5 bit_size: 1 - name: OUT_DONE_INT_RAW description: The raw bit for completing usage of a outlink descriptor. bit_offset: 6 bit_size: 1 - name: OUT_EOF_INT_RAW description: The raw bit for sending a packet to host done. bit_offset: 7 bit_size: 1 - name: OUT_TOTAL_EOF_INT_RAW description: The raw bit for sending all the packets to host done. bit_offset: 8 bit_size: 1 fieldset/DMA_INT_ST: fields: - name: INLINK_DSCR_EMPTY_INT_ST description: The status bit for lack of enough inlink descriptors. bit_offset: 0 bit_size: 1 - name: OUTLINK_DSCR_ERROR_INT_ST description: The status bit for outlink descriptor error. bit_offset: 1 bit_size: 1 - name: INLINK_DSCR_ERROR_INT_ST description: The status bit for inlink descriptor error. bit_offset: 2 bit_size: 1 - name: IN_DONE_INT_ST description: The status bit for completing usage of a inlink descriptor. bit_offset: 3 bit_size: 1 - name: IN_ERR_EOF_INT_ST description: The status bit for receiving error. bit_offset: 4 bit_size: 1 - name: IN_SUC_EOF_INT_ST description: The status bit for completing receiving all the packets from host. bit_offset: 5 bit_size: 1 - name: OUT_DONE_INT_ST description: The status bit for completing usage of a outlink descriptor. bit_offset: 6 bit_size: 1 - name: OUT_EOF_INT_ST description: The status bit for sending a packet to host done. bit_offset: 7 bit_size: 1 - name: OUT_TOTAL_EOF_INT_ST description: The status bit for sending all the packets to host done. bit_offset: 8 bit_size: 1 fieldset/DMA_IN_LINK: fields: - name: INLINK_ADDR description: The address of the first inlink descriptor. bit_offset: 0 bit_size: 20 - name: INLINK_AUTO_RET description: when the bit is set inlink descriptor returns to the next descriptor while a packet is wrong. bit_offset: 20 bit_size: 1 - name: INLINK_STOP description: Set the bit to stop to use inlink descriptor. bit_offset: 28 bit_size: 1 - name: INLINK_START description: Set the bit to start to use inlink descriptor. bit_offset: 29 bit_size: 1 - name: INLINK_RESTART description: Set the bit to mount on new inlink descriptors. bit_offset: 30 bit_size: 1 fieldset/DMA_OUT_LINK: fields: - name: OUTLINK_ADDR description: The address of the first outlink descriptor. bit_offset: 0 bit_size: 20 - name: OUTLINK_STOP description: Set the bit to stop to use outlink descriptor. bit_offset: 28 bit_size: 1 - name: OUTLINK_START description: Set the bit to start to use outlink descriptor. bit_offset: 29 bit_size: 1 - name: OUTLINK_RESTART description: Set the bit to mount on new outlink descriptors. bit_offset: 30 bit_size: 1 fieldset/DMA_RSTATUS: fields: - name: DMA_OUT_STATUS description: spi dma read data from memory status. bit_offset: 0 bit_size: 32 fieldset/DMA_STATUS: fields: - name: DMA_RX_EN description: spi dma read data status bit. bit_offset: 0 bit_size: 1 - name: DMA_TX_EN description: spi dma write data status bit. bit_offset: 1 bit_size: 1 fieldset/DMA_TSTATUS: fields: - name: DMA_IN_STATUS description: spi dma write data to memory status. bit_offset: 0 bit_size: 32 fieldset/EXT0: fields: - name: T_PP_TIME description: page program delay time by system clock. bit_offset: 0 bit_size: 12 - name: T_PP_SHIFT description: page program delay time shift. bit_offset: 16 bit_size: 4 - name: T_PP_ENA description: page program delay enable. bit_offset: 31 bit_size: 1 fieldset/EXT1: fields: - name: T_ERASE_TIME description: erase flash delay time by system clock. bit_offset: 0 bit_size: 12 - name: T_ERASE_SHIFT description: erase flash delay time shift. bit_offset: 16 bit_size: 4 - name: T_ERASE_ENA description: erase flash delay enable. bit_offset: 31 bit_size: 1 fieldset/EXT2: fields: - name: ST description: The status of spi state machine. bit_offset: 0 bit_size: 3 fieldset/EXT3: fields: - name: INT_HOLD_ENA description: 'This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ¡°idle¡± phase 2: hold at ¡°prepare¡± phase.' bit_offset: 0 bit_size: 2 fieldset/INLINK_DSCR: fields: - name: DMA_INLINK_DSCR description: The content of current in descriptor pointer. bit_offset: 0 bit_size: 32 fieldset/INLINK_DSCR_BF0: fields: - name: DMA_INLINK_DSCR_BF0 description: The content of next in descriptor pointer. bit_offset: 0 bit_size: 32 fieldset/INLINK_DSCR_BF1: fields: - name: DMA_INLINK_DSCR_BF1 description: The content of current in descriptor data buffer pointer. bit_offset: 0 bit_size: 32 fieldset/IN_ERR_EOF_DES_ADDR: fields: - name: DMA_IN_ERR_EOF_DES_ADDR description: The inlink descriptor address when spi dma produce receiving error. bit_offset: 0 bit_size: 32 fieldset/IN_SUC_EOF_DES_ADDR: fields: - name: DMA_IN_SUC_EOF_DES_ADDR description: The last inlink descriptor address when spi dma produce from_suc_eof. bit_offset: 0 bit_size: 32 fieldset/MISO_DLEN: fields: - name: USR_MISO_DBITLEN description: The length in bits of read-data. The register value shall be (bit_num-1). bit_offset: 0 bit_size: 24 fieldset/MOSI_DLEN: fields: - name: USR_MOSI_DBITLEN description: The length in bits of write-data. The register value shall be (bit_num-1). bit_offset: 0 bit_size: 24 fieldset/OUTLINK_DSCR: fields: - name: DMA_OUTLINK_DSCR description: The content of current out descriptor pointer. bit_offset: 0 bit_size: 32 fieldset/OUTLINK_DSCR_BF0: fields: - name: DMA_OUTLINK_DSCR_BF0 description: The content of next out descriptor pointer. bit_offset: 0 bit_size: 32 fieldset/OUTLINK_DSCR_BF1: fields: - name: DMA_OUTLINK_DSCR_BF1 description: The content of current out descriptor data buffer pointer. bit_offset: 0 bit_size: 32 fieldset/OUT_EOF_BFR_DES_ADDR: fields: - name: DMA_OUT_EOF_BFR_DES_ADDR description: The address of buffer relative to the outlink descriptor that produce eof. bit_offset: 0 bit_size: 32 fieldset/OUT_EOF_DES_ADDR: fields: - name: DMA_OUT_EOF_DES_ADDR description: The last outlink descriptor address when spi dma produce to_eof. bit_offset: 0 bit_size: 32 fieldset/PIN: fields: - name: CS0_DIS description: 'SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin.' bit_offset: 0 bit_size: 1 - name: CS1_DIS description: 'SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin.' bit_offset: 1 bit_size: 1 - name: CS2_DIS description: 'SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin.' bit_offset: 2 bit_size: 1 - name: CK_DIS description: '1: spi clk out disable 0: spi clk out enable.' bit_offset: 5 bit_size: 1 - name: MASTER_CS_POL description: In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol. bit_offset: 6 bit_size: 3 - name: MASTER_CK_SEL description: In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis. bit_offset: 11 bit_size: 3 - name: CK_IDLE_EDGE description: '1: spi clk line is high when idle 0: spi clk line is low when idle.' bit_offset: 29 bit_size: 1 - name: CS_KEEP_ACTIVE description: spi cs line keep low when the bit is set. bit_offset: 30 bit_size: 1 fieldset/RD_STATUS: fields: - name: STATUS description: In the slave mode, it is the status for master to read out. bit_offset: 0 bit_size: 16 - name: WB_MODE description: Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit. bit_offset: 16 bit_size: 8 - name: STATUS_EXT description: In the slave mode,it is the status for master to read out. bit_offset: 24 bit_size: 8 fieldset/SLAVE: fields: - name: SLV_RD_BUF_DONE description: The interrupt raw bit for the completion of read-buffer operation in the slave mode. bit_offset: 0 bit_size: 1 - name: SLV_WR_BUF_DONE description: The interrupt raw bit for the completion of write-buffer operation in the slave mode. bit_offset: 1 bit_size: 1 - name: SLV_RD_STA_DONE description: The interrupt raw bit for the completion of read-status operation in the slave mode. bit_offset: 2 bit_size: 1 - name: SLV_WR_STA_DONE description: The interrupt raw bit for the completion of write-status operation in the slave mode. bit_offset: 3 bit_size: 1 - name: TRANS_DONE description: The interrupt raw bit for the completion of any operation in both the master mode and the slave mode. bit_offset: 4 bit_size: 1 - name: INT_EN description: Interrupt enable bits for the below 5 sources. bit_offset: 5 bit_size: 5 - name: CS_I_MODE description: In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter. bit_offset: 10 bit_size: 2 - name: SLV_LAST_COMMAND description: In the slave mode it is the value of command. bit_offset: 17 bit_size: 3 - name: SLV_LAST_STATE description: In the slave mode it is the state of spi state machine. bit_offset: 20 bit_size: 3 - name: TRANS_CNT description: 'The operations counter in both the master mode and the slave mode. 4: read-status.' bit_offset: 23 bit_size: 4 - name: SLV_CMD_DEFINE description: '1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.' bit_offset: 27 bit_size: 1 - name: SLV_WR_RD_STA_EN description: write and read status enable in the slave mode. bit_offset: 28 bit_size: 1 - name: SLV_WR_RD_BUF_EN description: write and read buffer enable in the slave mode. bit_offset: 29 bit_size: 1 - name: MODE description: '1: slave mode 0: master mode.' bit_offset: 30 bit_size: 1 - name: SYNC_RESET description: Software reset enable, reset the spi clock line cs line and data lines. bit_offset: 31 bit_size: 1 fieldset/SLAVE1: fields: - name: SLV_RDBUF_DUMMY_EN description: In the slave mode it is the enable bit of dummy phase for read-buffer operations. bit_offset: 0 bit_size: 1 - name: SLV_WRBUF_DUMMY_EN description: In the slave mode it is the enable bit of dummy phase for write-buffer operations. bit_offset: 1 bit_size: 1 - name: SLV_RDSTA_DUMMY_EN description: In the slave mode it is the enable bit of dummy phase for read-status operations. bit_offset: 2 bit_size: 1 - name: SLV_WRSTA_DUMMY_EN description: In the slave mode it is the enable bit of dummy phase for write-status operations. bit_offset: 3 bit_size: 1 - name: SLV_WR_ADDR_BITLEN description: In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1). bit_offset: 4 bit_size: 6 - name: SLV_RD_ADDR_BITLEN description: In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1). bit_offset: 10 bit_size: 6 - name: SLV_STATUS_READBACK description: 'In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS.' bit_offset: 25 bit_size: 1 - name: SLV_STATUS_FAST_EN description: In the slave mode enable fast read status. bit_offset: 26 bit_size: 1 - name: SLV_STATUS_BITLEN description: In the slave mode it is the length of status bit. bit_offset: 27 bit_size: 5 fieldset/SLAVE2: fields: - name: SLV_RDSTA_DUMMY_CYCLELEN description: In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1). bit_offset: 0 bit_size: 8 - name: SLV_WRSTA_DUMMY_CYCLELEN description: In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1). bit_offset: 8 bit_size: 8 - name: SLV_RDBUF_DUMMY_CYCLELEN description: In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1). bit_offset: 16 bit_size: 8 - name: SLV_WRBUF_DUMMY_CYCLELEN description: In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1). bit_offset: 24 bit_size: 8 fieldset/SLAVE3: fields: - name: SLV_RDBUF_CMD_VALUE description: In the slave mode it is the value of read-buffer command. bit_offset: 0 bit_size: 8 - name: SLV_WRBUF_CMD_VALUE description: In the slave mode it is the value of write-buffer command. bit_offset: 8 bit_size: 8 - name: SLV_RDSTA_CMD_VALUE description: In the slave mode it is the value of read-status command. bit_offset: 16 bit_size: 8 - name: SLV_WRSTA_CMD_VALUE description: In the slave mode it is the value of write-status command. bit_offset: 24 bit_size: 8 fieldset/SLV_RDBUF_DLEN: fields: - name: SLV_RDBUF_DBITLEN description: In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1). bit_offset: 0 bit_size: 24 fieldset/SLV_RD_BIT: fields: - name: SLV_RDATA_BIT description: In the slave mode it is the bit length of read data. The value is the length - 1. bit_offset: 0 bit_size: 24 fieldset/SLV_WRBUF_DLEN: fields: - name: SLV_WRBUF_DBITLEN description: In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1). bit_offset: 0 bit_size: 24 fieldset/SLV_WR_STATUS: fields: - name: SLV_WR_ST description: In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition. bit_offset: 0 bit_size: 32 fieldset/SRAM_CMD: fields: - name: SRAM_DIO description: For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done. bit_offset: 0 bit_size: 1 - name: SRAM_QIO description: For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done. bit_offset: 1 bit_size: 1 - name: SRAM_RSTIO description: For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done. bit_offset: 4 bit_size: 1 fieldset/SRAM_DRD_CMD: fields: - name: CACHE_SRAM_USR_RD_CMD_VALUE description: For SPI0 When cache mode is enable it is the read command value of command phase for SRAM. bit_offset: 0 bit_size: 16 - name: CACHE_SRAM_USR_RD_CMD_BITLEN description: For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1). bit_offset: 28 bit_size: 4 fieldset/SRAM_DWR_CMD: fields: - name: CACHE_SRAM_USR_WR_CMD_VALUE description: For SPI0 When cache mode is enable it is the write command value of command phase for SRAM. bit_offset: 0 bit_size: 16 - name: CACHE_SRAM_USR_WR_CMD_BITLEN description: For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1). bit_offset: 28 bit_size: 4 fieldset/TX_CRC: fields: - name: DATA description: For SPI1 the value of crc32 for 256 bits data. bit_offset: 0 bit_size: 32 fieldset/USER: fields: - name: DOUTDIN description: 'Set the bit to enable full duplex communication. 1: enable 0: disable.' bit_offset: 0 bit_size: 1 - name: CS_HOLD description: 'spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable.' bit_offset: 4 bit_size: 1 - name: CS_SETUP description: 'spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable.' bit_offset: 5 bit_size: 1 - name: CK_I_EDGE description: In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits. bit_offset: 6 bit_size: 1 - name: CK_OUT_EDGE description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. bit_offset: 7 bit_size: 1 - name: RD_BYTE_ORDER description: 'In read-data (MISO) phase 1: big-endian 0: little_endian.' bit_offset: 10 bit_size: 1 - name: WR_BYTE_ORDER description: 'In command address write-data (MOSI) phases 1: big-endian 0: litte_endian.' bit_offset: 11 bit_size: 1 - name: FWRITE_DUAL description: In the write operations read-data phase apply 2 signals. bit_offset: 12 bit_size: 1 - name: FWRITE_QUAD description: In the write operations read-data phase apply 4 signals. bit_offset: 13 bit_size: 1 - name: FWRITE_DIO description: In the write operations address phase and read-data phase apply 2 signals. bit_offset: 14 bit_size: 1 - name: FWRITE_QIO description: In the write operations address phase and read-data phase apply 4 signals. bit_offset: 15 bit_size: 1 - name: SIO description: 'Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.' bit_offset: 16 bit_size: 1 - name: USR_HOLD_POL description: 'It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low.' bit_offset: 17 bit_size: 1 - name: USR_DOUT_HOLD description: spi is hold at data out state the bit combined with spi_usr_hold_pol bit. bit_offset: 18 bit_size: 1 - name: USR_DIN_HOLD description: spi is hold at data in state the bit combined with spi_usr_hold_pol bit. bit_offset: 19 bit_size: 1 - name: USR_DUMMY_HOLD description: spi is hold at dummy state the bit combined with spi_usr_hold_pol bit. bit_offset: 20 bit_size: 1 - name: USR_ADDR_HOLD description: spi is hold at address state the bit combined with spi_usr_hold_pol bit. bit_offset: 21 bit_size: 1 - name: USR_CMD_HOLD description: spi is hold at command state the bit combined with spi_usr_hold_pol bit. bit_offset: 22 bit_size: 1 - name: USR_PREP_HOLD description: spi is hold at prepare state the bit combined with spi_usr_hold_pol bit. bit_offset: 23 bit_size: 1 - name: USR_MISO_HIGHPART description: 'read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.' bit_offset: 24 bit_size: 1 - name: USR_MOSI_HIGHPART description: 'write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.' bit_offset: 25 bit_size: 1 - name: USR_DUMMY_IDLE description: spi clock is disable in dummy phase when the bit is enable. bit_offset: 26 bit_size: 1 - name: USR_MOSI description: This bit enable the write-data phase of an operation. bit_offset: 27 bit_size: 1 - name: USR_MISO description: This bit enable the read-data phase of an operation. bit_offset: 28 bit_size: 1 - name: USR_DUMMY description: This bit enable the dummy phase of an operation. bit_offset: 29 bit_size: 1 - name: USR_ADDR description: This bit enable the address phase of an operation. bit_offset: 30 bit_size: 1 - name: USR_COMMAND description: This bit enable the command phase of an operation. bit_offset: 31 bit_size: 1 fieldset/USER1: fields: - name: USR_DUMMY_CYCLELEN description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). bit_offset: 0 bit_size: 8 - name: USR_ADDR_BITLEN description: The length in bits of address phase. The register value shall be (bit_num-1). bit_offset: 26 bit_size: 6 fieldset/USER2: fields: - name: USR_COMMAND_VALUE description: The value of command. bit_offset: 0 bit_size: 16 - name: USR_COMMAND_BITLEN description: The length in bits of command phase. The register value shall be (bit_num-1). bit_offset: 28 bit_size: 4 fieldset/W0: fields: - name: BUF0 description: data buffer. bit_offset: 0 bit_size: 32 fieldset/W1: fields: - name: BUF1 description: data buffer. bit_offset: 0 bit_size: 32 fieldset/W10: fields: - name: BUF10 description: data buffer. bit_offset: 0 bit_size: 32 fieldset/W11: fields: - name: BUF11 description: data buffer. bit_offset: 0 bit_size: 32 fieldset/W12: fields: - name: BUF12 description: data buffer. bit_offset: 0 bit_size: 32 fieldset/W13: fields: - name: BUF13 description: data buffer. bit_offset: 0 bit_size: 32 fieldset/W14: fields: - name: BUF14 description: data buffer. bit_offset: 0 bit_size: 32 fieldset/W15: fields: - name: BUF15 description: data buffer. bit_offset: 0 bit_size: 32 fieldset/W2: fields: - name: BUF2 description: data buffer. bit_offset: 0 bit_size: 32 fieldset/W3: fields: - name: BUF3 description: data buffer. bit_offset: 0 bit_size: 32 fieldset/W4: fields: - name: BUF4 description: data buffer. bit_offset: 0 bit_size: 32 fieldset/W5: fields: - name: BUF5 description: data buffer. bit_offset: 0 bit_size: 32 fieldset/W6: fields: - name: BUF6 description: data buffer. bit_offset: 0 bit_size: 32 fieldset/W7: fields: - name: BUF7 description: data buffer. bit_offset: 0 bit_size: 32 fieldset/W8: fields: - name: BUF8 description: data buffer. bit_offset: 0 bit_size: 32 fieldset/W9: fields: - name: BUF9 description: data buffer. bit_offset: 0 bit_size: 32