block/SENS: description: SENS Peripheral. items: - name: SAR_READ_CTRL byte_offset: 0 fieldset: SAR_READ_CTRL - name: SAR_READ_STATUS1 byte_offset: 4 fieldset: SAR_READ_STATUS1 - name: SAR_MEAS_WAIT1 byte_offset: 8 fieldset: SAR_MEAS_WAIT1 - name: SAR_MEAS_WAIT2 byte_offset: 12 fieldset: SAR_MEAS_WAIT2 - name: SAR_MEAS_CTRL byte_offset: 16 fieldset: SAR_MEAS_CTRL - name: SAR_READ_STATUS2 byte_offset: 20 fieldset: SAR_READ_STATUS2 - name: ULP_CP_SLEEP_CYC0 byte_offset: 24 fieldset: ULP_CP_SLEEP_CYC0 - name: ULP_CP_SLEEP_CYC1 byte_offset: 28 fieldset: ULP_CP_SLEEP_CYC1 - name: ULP_CP_SLEEP_CYC2 byte_offset: 32 fieldset: ULP_CP_SLEEP_CYC2 - name: ULP_CP_SLEEP_CYC3 byte_offset: 36 fieldset: ULP_CP_SLEEP_CYC3 - name: ULP_CP_SLEEP_CYC4 byte_offset: 40 fieldset: ULP_CP_SLEEP_CYC4 - name: SAR_START_FORCE byte_offset: 44 fieldset: SAR_START_FORCE - name: SAR_MEM_WR_CTRL byte_offset: 48 fieldset: SAR_MEM_WR_CTRL - name: SAR_ATTEN1 byte_offset: 52 fieldset: SAR_ATTEN1 - name: SAR_ATTEN2 byte_offset: 56 fieldset: SAR_ATTEN2 - name: SAR_SLAVE_ADDR1 byte_offset: 60 fieldset: SAR_SLAVE_ADDR1 - name: SAR_SLAVE_ADDR2 byte_offset: 64 fieldset: SAR_SLAVE_ADDR2 - name: SAR_SLAVE_ADDR3 byte_offset: 68 fieldset: SAR_SLAVE_ADDR3 - name: SAR_SLAVE_ADDR4 byte_offset: 72 fieldset: SAR_SLAVE_ADDR4 - name: SAR_TSENS_CTRL byte_offset: 76 fieldset: SAR_TSENS_CTRL - name: SAR_I2C_CTRL byte_offset: 80 fieldset: SAR_I2C_CTRL - name: SAR_MEAS_START1 byte_offset: 84 fieldset: SAR_MEAS_START1 - name: SAR_TOUCH_CTRL1 byte_offset: 88 fieldset: SAR_TOUCH_CTRL1 - name: SAR_TOUCH_THRES1 byte_offset: 92 fieldset: SAR_TOUCH_THRES1 - name: SAR_TOUCH_THRES2 byte_offset: 96 fieldset: SAR_TOUCH_THRES2 - name: SAR_TOUCH_THRES3 byte_offset: 100 fieldset: SAR_TOUCH_THRES3 - name: SAR_TOUCH_THRES4 byte_offset: 104 fieldset: SAR_TOUCH_THRES4 - name: SAR_TOUCH_THRES5 byte_offset: 108 fieldset: SAR_TOUCH_THRES5 - name: SAR_TOUCH_OUT1 byte_offset: 112 fieldset: SAR_TOUCH_OUT1 - name: SAR_TOUCH_OUT2 byte_offset: 116 fieldset: SAR_TOUCH_OUT2 - name: SAR_TOUCH_OUT3 byte_offset: 120 fieldset: SAR_TOUCH_OUT3 - name: SAR_TOUCH_OUT4 byte_offset: 124 fieldset: SAR_TOUCH_OUT4 - name: SAR_TOUCH_OUT5 byte_offset: 128 fieldset: SAR_TOUCH_OUT5 - name: SAR_TOUCH_CTRL2 byte_offset: 132 fieldset: SAR_TOUCH_CTRL2 - name: SAR_TOUCH_ENABLE byte_offset: 140 fieldset: SAR_TOUCH_ENABLE - name: SAR_READ_CTRL2 byte_offset: 144 fieldset: SAR_READ_CTRL2 - name: SAR_MEAS_START2 byte_offset: 148 fieldset: SAR_MEAS_START2 - name: SAR_DAC_CTRL1 byte_offset: 152 fieldset: SAR_DAC_CTRL1 - name: SAR_DAC_CTRL2 byte_offset: 156 fieldset: SAR_DAC_CTRL2 - name: SAR_MEAS_CTRL2 byte_offset: 160 fieldset: SAR_MEAS_CTRL2 - name: SAR_NOUSE byte_offset: 248 fieldset: SAR_NOUSE - name: SARDATE byte_offset: 252 fieldset: SARDATE fieldset/SARDATE: fields: - name: SAR_DATE bit_offset: 0 bit_size: 28 fieldset/SAR_ATTEN1: fields: - name: SAR1_ATTEN description: 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB. bit_offset: 0 bit_size: 32 fieldset/SAR_ATTEN2: fields: - name: SAR2_ATTEN description: 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB. bit_offset: 0 bit_size: 32 fieldset/SAR_DAC_CTRL1: fields: - name: SW_FSTEP description: frequency step for CW generator can be used to adjust the frequency. bit_offset: 0 bit_size: 16 - name: SW_TONE_EN description: '1: enable CW generator 0: disable CW generator.' bit_offset: 16 bit_size: 1 - name: DEBUG_BIT_SEL bit_offset: 17 bit_size: 5 - name: DAC_DIG_FORCE description: '1: DAC1 & DAC2 use DMA 0: DAC1 & DAC2 do not use DMA.' bit_offset: 22 bit_size: 1 - name: DAC_CLK_FORCE_LOW description: '1: force PDAC_CLK to low.' bit_offset: 23 bit_size: 1 - name: DAC_CLK_FORCE_HIGH description: '1: force PDAC_CLK to high.' bit_offset: 24 bit_size: 1 - name: DAC_CLK_INV description: '1: invert PDAC_CLK.' bit_offset: 25 bit_size: 1 fieldset/SAR_DAC_CTRL2: fields: - name: DAC_DC1 description: DC offset for DAC1 CW generator. bit_offset: 0 bit_size: 8 - name: DAC_DC2 description: DC offset for DAC2 CW generator. bit_offset: 8 bit_size: 8 - name: DAC_SCALE1 description: '00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8.' bit_offset: 16 bit_size: 2 - name: DAC_SCALE2 description: '00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8.' bit_offset: 18 bit_size: 2 - name: DAC_INV1 description: '00: do not invert any bits 01: invert all bits 10: invert MSB 11: invert all bits except MSB.' bit_offset: 20 bit_size: 2 - name: DAC_INV2 description: '00: do not invert any bits 01: invert all bits 10: invert MSB 11: invert all bits except MSB.' bit_offset: 22 bit_size: 2 - name: DAC_CW_EN1 description: '1: to select CW generator as source to PDAC1_DAC[7:0] 0: to select register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0].' bit_offset: 24 bit_size: 1 - name: DAC_CW_EN2 description: '1: to select CW generator as source to PDAC2_DAC[7:0] 0: to select register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0].' bit_offset: 25 bit_size: 1 fieldset/SAR_I2C_CTRL: fields: - name: SAR_I2C_CTRL description: I2C control data only active when reg_sar_i2c_start_force = 1. bit_offset: 0 bit_size: 28 - name: SAR_I2C_START description: start I2C only active when reg_sar_i2c_start_force = 1. bit_offset: 28 bit_size: 1 - name: SAR_I2C_START_FORCE description: '1: I2C started by SW 0: I2C started by FSM.' bit_offset: 29 bit_size: 1 fieldset/SAR_MEAS_CTRL: fields: - name: XPD_SAR_AMP_FSM bit_offset: 0 bit_size: 4 - name: AMP_RST_FB_FSM bit_offset: 4 bit_size: 4 - name: AMP_SHORT_REF_FSM bit_offset: 8 bit_size: 4 - name: AMP_SHORT_REF_GND_FSM bit_offset: 12 bit_size: 4 - name: XPD_SAR_FSM bit_offset: 16 bit_size: 4 - name: SAR_RSTB_FSM bit_offset: 20 bit_size: 4 - name: SAR2_XPD_WAIT bit_offset: 24 bit_size: 8 fieldset/SAR_MEAS_CTRL2: fields: - name: SAR1_DAC_XPD_FSM bit_offset: 0 bit_size: 4 - name: SAR1_DAC_XPD_FSM_IDLE bit_offset: 4 bit_size: 1 - name: XPD_SAR_AMP_FSM_IDLE bit_offset: 5 bit_size: 1 - name: AMP_RST_FB_FSM_IDLE bit_offset: 6 bit_size: 1 - name: AMP_SHORT_REF_FSM_IDLE bit_offset: 7 bit_size: 1 - name: AMP_SHORT_REF_GND_FSM_IDLE bit_offset: 8 bit_size: 1 - name: XPD_SAR_FSM_IDLE bit_offset: 9 bit_size: 1 - name: SAR_RSTB_FSM_IDLE bit_offset: 10 bit_size: 1 - name: SAR2_RSTB_FORCE bit_offset: 11 bit_size: 2 - name: AMP_RST_FB_FORCE bit_offset: 13 bit_size: 2 - name: AMP_SHORT_REF_FORCE bit_offset: 15 bit_size: 2 - name: AMP_SHORT_REF_GND_FORCE bit_offset: 17 bit_size: 2 fieldset/SAR_MEAS_START1: fields: - name: MEAS1_DATA_SAR description: SAR ADC1 data. bit_offset: 0 bit_size: 16 - name: MEAS1_DONE_SAR description: SAR ADC1 conversion done indication. bit_offset: 16 bit_size: 1 - name: MEAS1_START_SAR description: SAR ADC1 controller (in RTC) starts conversion only active when reg_meas1_start_force = 1. bit_offset: 17 bit_size: 1 - name: MEAS1_START_FORCE description: '1: SAR ADC1 controller (in RTC) is started by SW 0: SAR ADC1 controller is started by ULP-coprocessor.' bit_offset: 18 bit_size: 1 - name: SAR1_EN_PAD description: SAR ADC1 pad enable bitmap only active when reg_sar1_en_pad_force = 1. bit_offset: 19 bit_size: 12 - name: SAR1_EN_PAD_FORCE description: '1: SAR ADC1 pad enable bitmap is controlled by SW 0: SAR ADC1 pad enable bitmap is controlled by ULP-coprocessor.' bit_offset: 31 bit_size: 1 fieldset/SAR_MEAS_START2: fields: - name: MEAS2_DATA_SAR description: SAR ADC2 data. bit_offset: 0 bit_size: 16 - name: MEAS2_DONE_SAR description: SAR ADC2 conversion done indication. bit_offset: 16 bit_size: 1 - name: MEAS2_START_SAR description: SAR ADC2 controller (in RTC) starts conversion only active when reg_meas2_start_force = 1. bit_offset: 17 bit_size: 1 - name: MEAS2_START_FORCE description: '1: SAR ADC2 controller (in RTC) is started by SW 0: SAR ADC2 controller is started by ULP-coprocessor.' bit_offset: 18 bit_size: 1 - name: SAR2_EN_PAD description: SAR ADC2 pad enable bitmap only active when reg_sar2_en_pad_force = 1. bit_offset: 19 bit_size: 12 - name: SAR2_EN_PAD_FORCE description: '1: SAR ADC2 pad enable bitmap is controlled by SW 0: SAR ADC2 pad enable bitmap is controlled by ULP-coprocessor.' bit_offset: 31 bit_size: 1 fieldset/SAR_MEAS_WAIT1: fields: - name: SAR_AMP_WAIT1 bit_offset: 0 bit_size: 16 - name: SAR_AMP_WAIT2 bit_offset: 16 bit_size: 16 fieldset/SAR_MEAS_WAIT2: fields: - name: FORCE_XPD_SAR_SW bit_offset: 0 bit_size: 1 - name: SAR_AMP_WAIT3 bit_offset: 0 bit_size: 16 - name: FORCE_XPD_AMP bit_offset: 16 bit_size: 2 - name: FORCE_XPD_SAR bit_offset: 18 bit_size: 2 - name: SAR2_RSTB_WAIT bit_offset: 20 bit_size: 8 fieldset/SAR_MEM_WR_CTRL: fields: - name: MEM_WR_ADDR_INIT bit_offset: 0 bit_size: 11 - name: MEM_WR_ADDR_SIZE bit_offset: 11 bit_size: 11 - name: RTC_MEM_WR_OFFST_CLR bit_offset: 22 bit_size: 1 fieldset/SAR_NOUSE: fields: - name: SAR_NOUSE bit_offset: 0 bit_size: 32 fieldset/SAR_READ_CTRL: fields: - name: SAR1_CLK_DIV description: clock divider. bit_offset: 0 bit_size: 8 - name: SAR1_SAMPLE_CYCLE description: sample cycles for SAR ADC1. bit_offset: 8 bit_size: 8 - name: SAR1_SAMPLE_BIT description: '00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for 12-bit width.' bit_offset: 16 bit_size: 2 - name: SAR1_CLK_GATED bit_offset: 18 bit_size: 1 - name: SAR1_SAMPLE_NUM bit_offset: 19 bit_size: 8 - name: SAR1_DIG_FORCE description: '1: SAR ADC1 controlled by DIG ADC1 CTRL 0: SAR ADC1 controlled by RTC ADC1 CTRL.' bit_offset: 27 bit_size: 1 - name: SAR1_DATA_INV description: Invert SAR ADC1 data. bit_offset: 28 bit_size: 1 fieldset/SAR_READ_CTRL2: fields: - name: SAR2_CLK_DIV description: clock divider. bit_offset: 0 bit_size: 8 - name: SAR2_SAMPLE_CYCLE description: sample cycles for SAR ADC2. bit_offset: 8 bit_size: 8 - name: SAR2_SAMPLE_BIT description: '00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for 12-bit width.' bit_offset: 16 bit_size: 2 - name: SAR2_CLK_GATED bit_offset: 18 bit_size: 1 - name: SAR2_SAMPLE_NUM bit_offset: 19 bit_size: 8 - name: SAR2_PWDET_FORCE bit_offset: 27 bit_size: 1 - name: SAR2_DIG_FORCE description: '1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL 0: SAR ADC2 controlled by RTC ADC2 CTRL.' bit_offset: 28 bit_size: 1 - name: SAR2_DATA_INV description: Invert SAR ADC2 data. bit_offset: 29 bit_size: 1 fieldset/SAR_READ_STATUS1: fields: - name: SAR1_READER_STATUS bit_offset: 0 bit_size: 32 fieldset/SAR_READ_STATUS2: fields: - name: SAR2_READER_STATUS bit_offset: 0 bit_size: 32 fieldset/SAR_SLAVE_ADDR1: fields: - name: I2C_SLAVE_ADDR1 bit_offset: 0 bit_size: 11 - name: I2C_SLAVE_ADDR0 bit_offset: 11 bit_size: 11 - name: MEAS_STATUS bit_offset: 22 bit_size: 8 fieldset/SAR_SLAVE_ADDR2: fields: - name: I2C_SLAVE_ADDR3 bit_offset: 0 bit_size: 11 - name: I2C_SLAVE_ADDR2 bit_offset: 11 bit_size: 11 fieldset/SAR_SLAVE_ADDR3: fields: - name: I2C_SLAVE_ADDR5 bit_offset: 0 bit_size: 11 - name: I2C_SLAVE_ADDR4 bit_offset: 11 bit_size: 11 - name: TSENS_OUT description: temperature sensor data out. bit_offset: 22 bit_size: 8 - name: TSENS_RDY_OUT description: indicate temperature sensor out ready. bit_offset: 30 bit_size: 1 fieldset/SAR_SLAVE_ADDR4: fields: - name: I2C_SLAVE_ADDR7 bit_offset: 0 bit_size: 11 - name: I2C_SLAVE_ADDR6 bit_offset: 11 bit_size: 11 - name: I2C_RDATA description: I2C read data. bit_offset: 22 bit_size: 8 - name: I2C_DONE description: indicate I2C done. bit_offset: 30 bit_size: 1 fieldset/SAR_START_FORCE: fields: - name: SAR1_BIT_WIDTH description: '00: 9 bit 01: 10 bits 10: 11bits 11: 12bits.' bit_offset: 0 bit_size: 2 - name: SAR2_BIT_WIDTH description: '00: 9 bit 01: 10 bits 10: 11bits 11: 12bits.' bit_offset: 2 bit_size: 2 - name: SAR2_EN_TEST description: SAR2_EN_TEST only active when reg_sar2_dig_force = 0. bit_offset: 4 bit_size: 1 - name: SAR2_PWDET_CCT description: SAR2_PWDET_CCT PA power detector capacitance tuning. bit_offset: 5 bit_size: 3 - name: ULP_CP_FORCE_START_TOP description: '1: ULP-coprocessor is started by SW 0: ULP-coprocessor is started by timer.' bit_offset: 8 bit_size: 1 - name: ULP_CP_START_TOP description: Write 1 to start ULP-coprocessor only active when reg_ulp_cp_force_start_top = 1. bit_offset: 9 bit_size: 1 - name: SARCLK_EN bit_offset: 10 bit_size: 1 - name: PC_INIT description: initialized PC for ULP-coprocessor. bit_offset: 11 bit_size: 11 - name: SAR2_STOP description: stop SAR ADC2 conversion. bit_offset: 22 bit_size: 1 - name: SAR1_STOP description: stop SAR ADC1 conversion. bit_offset: 23 bit_size: 1 - name: SAR2_PWDET_EN description: N/A. bit_offset: 24 bit_size: 1 fieldset/SAR_TOUCH_CTRL1: fields: - name: TOUCH_MEAS_DELAY description: the meas length (in 8MHz). bit_offset: 0 bit_size: 16 - name: TOUCH_XPD_WAIT description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD. bit_offset: 16 bit_size: 8 - name: TOUCH_OUT_SEL description: '1: when the counter is greater then the threshold the touch pad is considered as "touched" 0: when the counter is less than the threshold the touch pad is considered as "touched".' bit_offset: 24 bit_size: 1 - name: TOUCH_OUT_1EN description: '1: wakeup interrupt is generated if SET1 is "touched" 0: wakeup interrupt is generated only if SET1 & SET2 is both "touched".' bit_offset: 25 bit_size: 1 - name: XPD_HALL_FORCE description: '1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor.' bit_offset: 26 bit_size: 1 - name: HALL_PHASE_FORCE description: '1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor.' bit_offset: 27 bit_size: 1 fieldset/SAR_TOUCH_CTRL2: fields: - name: TOUCH_MEAS_EN description: 10-bit register to indicate which pads are "touched". bit_offset: 0 bit_size: 10 - name: TOUCH_MEAS_DONE description: fsm set 1 to indicate touch touch meas is done. bit_offset: 10 bit_size: 1 - name: TOUCH_START_FSM_EN description: '1: TOUCH_START & TOUCH_XPD is controlled by touch fsm 0: TOUCH_START & TOUCH_XPD is controlled by registers.' bit_offset: 11 bit_size: 1 - name: TOUCH_START_EN description: '1: start touch fsm valid when reg_touch_start_force is set.' bit_offset: 12 bit_size: 1 - name: TOUCH_START_FORCE description: '1: to start touch fsm by SW 0: to start touch fsm by timer.' bit_offset: 13 bit_size: 1 - name: TOUCH_SLEEP_CYCLES description: sleep cycles for timer. bit_offset: 14 bit_size: 16 - name: TOUCH_MEAS_EN_CLR description: to clear reg_touch_meas_en. bit_offset: 30 bit_size: 1 fieldset/SAR_TOUCH_ENABLE: fields: - name: TOUCH_PAD_WORKEN description: Bitmap defining the working set during the measurement. bit_offset: 0 bit_size: 10 - name: TOUCH_PAD_OUTEN2 description: Bitmap defining SET2 for generating wakeup interrupt. SET2 is "touched" only if at least one of touch pad in SET2 is "touched". bit_offset: 10 bit_size: 10 - name: TOUCH_PAD_OUTEN1 description: Bitmap defining SET1 for generating wakeup interrupt. SET1 is "touched" only if at least one of touch pad in SET1 is "touched". bit_offset: 20 bit_size: 10 fieldset/SAR_TOUCH_OUT1: fields: - name: TOUCH_MEAS_OUT1 description: the counter for touch pad 1. bit_offset: 0 bit_size: 16 - name: TOUCH_MEAS_OUT0 description: the counter for touch pad 0. bit_offset: 16 bit_size: 16 fieldset/SAR_TOUCH_OUT2: fields: - name: TOUCH_MEAS_OUT3 description: the counter for touch pad 3. bit_offset: 0 bit_size: 16 - name: TOUCH_MEAS_OUT2 description: the counter for touch pad 2. bit_offset: 16 bit_size: 16 fieldset/SAR_TOUCH_OUT3: fields: - name: TOUCH_MEAS_OUT5 description: the counter for touch pad 5. bit_offset: 0 bit_size: 16 - name: TOUCH_MEAS_OUT4 description: the counter for touch pad 4. bit_offset: 16 bit_size: 16 fieldset/SAR_TOUCH_OUT4: fields: - name: TOUCH_MEAS_OUT7 description: the counter for touch pad 7. bit_offset: 0 bit_size: 16 - name: TOUCH_MEAS_OUT6 description: the counter for touch pad 6. bit_offset: 16 bit_size: 16 fieldset/SAR_TOUCH_OUT5: fields: - name: TOUCH_MEAS_OUT9 description: the counter for touch pad 9. bit_offset: 0 bit_size: 16 - name: TOUCH_MEAS_OUT8 description: the counter for touch pad 8. bit_offset: 16 bit_size: 16 fieldset/SAR_TOUCH_THRES1: fields: - name: TOUCH_OUT_TH1 description: the threshold for touch pad 1. bit_offset: 0 bit_size: 16 - name: TOUCH_OUT_TH0 description: the threshold for touch pad 0. bit_offset: 16 bit_size: 16 fieldset/SAR_TOUCH_THRES2: fields: - name: TOUCH_OUT_TH3 description: the threshold for touch pad 3. bit_offset: 0 bit_size: 16 - name: TOUCH_OUT_TH2 description: the threshold for touch pad 2. bit_offset: 16 bit_size: 16 fieldset/SAR_TOUCH_THRES3: fields: - name: TOUCH_OUT_TH5 description: the threshold for touch pad 5. bit_offset: 0 bit_size: 16 - name: TOUCH_OUT_TH4 description: the threshold for touch pad 4. bit_offset: 16 bit_size: 16 fieldset/SAR_TOUCH_THRES4: fields: - name: TOUCH_OUT_TH7 description: the threshold for touch pad 7. bit_offset: 0 bit_size: 16 - name: TOUCH_OUT_TH6 description: the threshold for touch pad 6. bit_offset: 16 bit_size: 16 fieldset/SAR_TOUCH_THRES5: fields: - name: TOUCH_OUT_TH9 description: the threshold for touch pad 9. bit_offset: 0 bit_size: 16 - name: TOUCH_OUT_TH8 description: the threshold for touch pad 8. bit_offset: 16 bit_size: 16 fieldset/SAR_TSENS_CTRL: fields: - name: TSENS_XPD_WAIT bit_offset: 0 bit_size: 12 - name: TSENS_XPD_FORCE bit_offset: 12 bit_size: 1 - name: TSENS_CLK_INV bit_offset: 13 bit_size: 1 - name: TSENS_CLK_GATED bit_offset: 14 bit_size: 1 - name: TSENS_IN_INV description: invert temperature sensor data. bit_offset: 15 bit_size: 1 - name: TSENS_CLK_DIV description: temperature sensor clock divider. bit_offset: 16 bit_size: 8 - name: TSENS_POWER_UP description: temperature sensor power up. bit_offset: 24 bit_size: 1 - name: TSENS_POWER_UP_FORCE description: '1: dump out & power up controlled by SW 0: by FSM.' bit_offset: 25 bit_size: 1 - name: TSENS_DUMP_OUT description: temperature sensor dump out only active when reg_tsens_power_up_force = 1. bit_offset: 26 bit_size: 1 fieldset/ULP_CP_SLEEP_CYC0: fields: - name: SLEEP_CYCLES_S0 description: sleep cycles for ULP-coprocessor timer. bit_offset: 0 bit_size: 32 fieldset/ULP_CP_SLEEP_CYC1: fields: - name: SLEEP_CYCLES_S1 bit_offset: 0 bit_size: 32 fieldset/ULP_CP_SLEEP_CYC2: fields: - name: SLEEP_CYCLES_S2 bit_offset: 0 bit_size: 32 fieldset/ULP_CP_SLEEP_CYC3: fields: - name: SLEEP_CYCLES_S3 bit_offset: 0 bit_size: 32 fieldset/ULP_CP_SLEEP_CYC4: fields: - name: SLEEP_CYCLES_S4 bit_offset: 0 bit_size: 32