block/SDHOST: description: SD/MMC Host Controller. items: - name: CTRL description: Control register. byte_offset: 0 fieldset: CTRL - name: CLKDIV description: Clock divider configuration register. byte_offset: 8 fieldset: CLKDIV - name: CLKSRC description: Clock source selection register. byte_offset: 12 fieldset: CLKSRC - name: CLKENA description: Clock enable register. byte_offset: 16 fieldset: CLKENA - name: TMOUT description: Data and response timeout configuration register. byte_offset: 20 fieldset: TMOUT - name: CTYPE description: Card bus width configuration register. byte_offset: 24 fieldset: CTYPE - name: BLKSIZ description: Card data block size configuration register. byte_offset: 28 fieldset: BLKSIZ - name: BYTCNT description: Data transfer length configuration register. byte_offset: 32 fieldset: BYTCNT - name: INTMASK description: SDIO interrupt mask register. byte_offset: 36 fieldset: INTMASK - name: CMDARG description: Command argument data register. byte_offset: 40 fieldset: CMDARG - name: CMD description: Command and boot configuration register. byte_offset: 44 fieldset: CMD - name: RESP0 description: Response data register. byte_offset: 48 fieldset: RESP0 - name: RESP1 description: Long response data register. byte_offset: 52 fieldset: RESP1 - name: RESP2 description: Long response data register. byte_offset: 56 fieldset: RESP2 - name: RESP3 description: Long response data register. byte_offset: 60 fieldset: RESP3 - name: MINTSTS description: Masked interrupt status register. byte_offset: 64 fieldset: MINTSTS - name: RINTSTS description: Raw interrupt status register. byte_offset: 68 fieldset: RINTSTS - name: STATUS description: SD/MMC status register. byte_offset: 72 fieldset: STATUS - name: FIFOTH description: FIFO configuration register. byte_offset: 76 fieldset: FIFOTH - name: CDETECT description: Card detect register. byte_offset: 80 fieldset: CDETECT - name: WRTPRT description: Card write protection (WP) status register. byte_offset: 84 fieldset: WRTPRT - name: TCBCNT description: Transferred byte count register. byte_offset: 92 fieldset: TCBCNT - name: TBBCNT description: Transferred byte count register. byte_offset: 96 fieldset: TBBCNT - name: DEBNCE description: Debounce filter time configuration register. byte_offset: 100 fieldset: DEBNCE - name: USRID description: User ID (scratchpad) register. byte_offset: 104 fieldset: USRID - name: VERID description: Version ID (scratchpad) register. byte_offset: 108 fieldset: VERID - name: HCON description: Hardware feature register. byte_offset: 112 fieldset: HCON - name: UHS description: UHS-1 register. byte_offset: 116 fieldset: UHS - name: RST_N description: Card reset register. byte_offset: 120 fieldset: RST_N - name: BMOD description: Burst mode transfer configuration register. byte_offset: 128 fieldset: BMOD - name: PLDMND description: Poll demand configuration register. byte_offset: 132 fieldset: PLDMND - name: DBADDR description: Descriptor base address register. byte_offset: 136 fieldset: DBADDR - name: IDSTS description: IDMAC status register. byte_offset: 140 fieldset: IDSTS - name: IDINTEN description: IDMAC interrupt enable register. byte_offset: 144 fieldset: IDINTEN - name: DSCADDR description: Host descriptor address pointer. byte_offset: 148 fieldset: DSCADDR - name: BUFADDR description: Host buffer address pointer register. byte_offset: 152 fieldset: BUFADDR - name: CARDTHRCTL description: Card Threshold Control register. byte_offset: 256 fieldset: CARDTHRCTL - name: EMMCDDR description: eMMC DDR register. byte_offset: 268 fieldset: EMMCDDR - name: ENSHIFT description: Enable Phase Shift register. byte_offset: 272 fieldset: ENSHIFT - name: BUFFIFO description: CPU write and read transmit data by FIFO. byte_offset: 512 fieldset: BUFFIFO - name: CLK_EDGE_SEL description: SDIO control register. byte_offset: 2048 fieldset: CLK_EDGE_SEL fieldset/BLKSIZ: description: Card data block size configuration register. fields: - name: BLOCK_SIZE description: Block size. bit_offset: 0 bit_size: 16 fieldset/BMOD: description: Burst mode transfer configuration register. fields: - name: SWR description: Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle. bit_offset: 0 bit_size: 1 - name: FB description: Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. bit_offset: 1 bit_size: 1 - name: DE description: IDMAC Enable. When set, the IDMAC is enabled. bit_offset: 7 bit_size: 1 - name: PBL description: 'Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer. PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access.' bit_offset: 8 bit_size: 3 fieldset/BUFADDR: description: Host buffer address pointer register. fields: - name: BUFADDR description: Host Buffer Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the current Data Buffer Address being accessed by the IDMAC. bit_offset: 0 bit_size: 32 fieldset/BUFFIFO: description: CPU write and read transmit data by FIFO. fields: - name: BUFFIFO description: CPU write and read transmit data by FIFO. This register points to the current Data FIFO. bit_offset: 0 bit_size: 32 fieldset/BYTCNT: description: Data transfer length configuration register. fields: - name: BYTE_COUNT description: Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer. bit_offset: 0 bit_size: 32 fieldset/CARDTHRCTL: description: Card Threshold Control register. fields: - name: CARDRDTHREN description: Card read threshold enable. 1'b0-Card read threshold disabled. 1'b1-Card read threshold enabled. bit_offset: 0 bit_size: 1 - name: CARDCLRINTEN description: 'Busy clear interrupt generation: 1''b0-Busy clear interrypt disabled. 1''b1-Busy clear interrypt enabled.' bit_offset: 1 bit_size: 1 - name: CARDWRTHREN description: Applicable when HS400 mode is enabled. 1'b0-Card write Threshold disabled. 1'b1-Card write Threshold enabled. bit_offset: 2 bit_size: 1 - name: CARDTHRESHOLD description: The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1. bit_offset: 16 bit_size: 16 fieldset/CDETECT: description: Card detect register. fields: - name: CARD_DETECT_N description: Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 represents presence of card. Only NUM_CARDS number of bits are implemented. bit_offset: 0 bit_size: 2 fieldset/CLKDIV: description: Clock divider configuration register. fields: - name: CLK_DIVIDER0 description: Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. bit_offset: 0 bit_size: 8 - name: CLK_DIVIDER1 description: Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. bit_offset: 8 bit_size: 8 - name: CLK_DIVIDER2 description: Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. bit_offset: 16 bit_size: 8 - name: CLK_DIVIDER3 description: Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. bit_offset: 24 bit_size: 8 fieldset/CLKENA: description: Clock enable register. fields: - name: CCLK_ENABLE description: 'Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. 0: Clock disabled; 1: Clock enabled.' bit_offset: 0 bit_size: 2 - name: LP_ENABLE description: 'Disable clock when the card is in IDLE state. One bit per card. 0: clock disabled; 1: clock enabled.' bit_offset: 16 bit_size: 2 fieldset/CLKSRC: description: Clock source selection register. fields: - name: CLKSRC description: 'Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for card 1. Card 0 maps and internally routes clock divider[0:3] outputs to cclk_out[1:0] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3.' bit_offset: 0 bit_size: 4 fieldset/CLK_EDGE_SEL: description: SDIO control register. fields: - name: CCLKIN_EDGE_DRV_SEL description: It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270. bit_offset: 0 bit_size: 3 - name: CCLKIN_EDGE_SAM_SEL description: It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270. bit_offset: 3 bit_size: 3 - name: CCLKIN_EDGE_SLF_SEL description: It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270. bit_offset: 6 bit_size: 3 - name: CCLLKIN_EDGE_H description: The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L. bit_offset: 9 bit_size: 4 - name: CCLLKIN_EDGE_L description: The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H. bit_offset: 13 bit_size: 4 - name: CCLLKIN_EDGE_N description: The value should be equal to CCLKIN_EDGE_L. bit_offset: 17 bit_size: 4 - name: ESDIO_MODE description: Enable esdio mode. bit_offset: 21 bit_size: 1 - name: ESD_MODE description: Enable esd mode. bit_offset: 22 bit_size: 1 - name: CCLK_EN description: Sdio clock enable. bit_offset: 23 bit_size: 1 fieldset/CMD: description: Command and boot configuration register. fields: - name: INDEX description: Command index. bit_offset: 0 bit_size: 6 - name: RESPONSE_EXPECT description: '0: No response expected from card; 1: Response expected from card.' bit_offset: 6 bit_size: 1 - name: RESPONSE_LENGTH description: '0: Short response expected from card; 1: Long response expected from card.' bit_offset: 7 bit_size: 1 - name: CHECK_RESPONSE_CRC description: '0: Do not check; 1: Check response CRC. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller.' bit_offset: 8 bit_size: 1 - name: DATA_EXPECTED description: '0: No data transfer expected; 1: Data transfer expected.' bit_offset: 9 bit_size: 1 - name: READ_WRITE description: '0: Read from card; 1: Write to card. Don''t care if no data is expected from card.' bit_offset: 10 bit_size: 1 - name: TRANSFER_MODE description: 'Block data transfer command; 1: Stream data transfer command. Don''t care if no data expected.' bit_offset: 11 bit_size: 1 - name: SEND_AUTO_STOP description: '0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer.' bit_offset: 12 bit_size: 1 - name: WAIT_PRVDATA_COMPLETE description: '0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command.' bit_offset: 13 bit_size: 1 - name: STOP_ABORT_CMD description: '0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state.' bit_offset: 14 bit_size: 1 - name: SEND_INITIALIZATION description: '0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card.' bit_offset: 15 bit_size: 1 - name: CARD_NUMBER description: Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported. bit_offset: 16 bit_size: 5 - name: UPDATE_CLOCK_REGISTERS_ONLY description: '0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards.' bit_offset: 21 bit_size: 1 - name: READ_CEATA_DEVICE description: 'Read access flag. 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device.' bit_offset: 22 bit_size: 1 - name: CCS_EXPECTED description: 'Expected Command Completion Signal (CCS) configuration. 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked.' bit_offset: 23 bit_size: 1 - name: USE_HOLE description: 'Use Hold Register. 0: CMD and DATA sent to card bypassing HOLD Register; 1: CMD and DATA sent to card through the HOLD Register.' bit_offset: 29 bit_size: 1 - name: START_CMD description: Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register. bit_offset: 31 bit_size: 1 fieldset/CMDARG: description: Command argument data register. fields: - name: CMDARG description: Value indicates command argument to be passed to the card. bit_offset: 0 bit_size: 32 fieldset/CTRL: description: Control register. fields: - name: CONTROLLER_RESET description: To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles. bit_offset: 0 bit_size: 1 - name: FIFO_RESET description: 'To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared.' bit_offset: 1 bit_size: 1 - name: DMA_RESET description: To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks. bit_offset: 2 bit_size: 1 - name: INT_ENABLE description: 'Global interrupt enable/disable bit. 0: Disable; 1: Enable.' bit_offset: 4 bit_size: 1 - name: READ_WAIT description: For sending read-wait to SDIO cards. bit_offset: 6 bit_size: 1 - name: SEND_IRQ_RESPONSE description: Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state. bit_offset: 7 bit_size: 1 - name: ABORT_READ_DATA description: After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle. bit_offset: 8 bit_size: 1 - name: SEND_CCSD description: 'When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS.' bit_offset: 9 bit_size: 1 - name: SEND_AUTO_STOP_CCSD description: Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit. bit_offset: 10 bit_size: 1 - name: CEATA_DEVICE_INTERRUPT_STATUS description: Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit. bit_offset: 11 bit_size: 1 fieldset/CTYPE: description: Card bus width configuration register. fields: - name: CARD_WIDTH4 description: 'One bit per card indicates if card is 1-bit or 4-bit mode. 0: 1-bit mode; 1: 4-bit mode. Bit[1:0] correspond to card[1:0] respectively.' bit_offset: 0 bit_size: 2 - name: CARD_WIDTH8 description: 'One bit per card indicates if card is in 8-bit mode. 0: Non 8-bit mode; 1: 8-bit mode. Bit[17:16] correspond to card[1:0] respectively.' bit_offset: 16 bit_size: 2 fieldset/DBADDR: description: Descriptor base address register. fields: - name: DBADDR description: Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only. bit_offset: 0 bit_size: 32 fieldset/DEBNCE: description: Debounce filter time configuration register. fields: - name: DEBOUNCE_COUNT description: Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \verb+~+ 25 ms to prevent the card instability when the card is inserted or removed. bit_offset: 0 bit_size: 24 fieldset/DSCADDR: description: Host descriptor address pointer. fields: - name: DSCADDR description: Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC. bit_offset: 0 bit_size: 32 fieldset/EMMCDDR: description: eMMC DDR register. fields: - name: HALFSTARTBIT description: 'Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: 1''b0-Full cycle. 1''b1-less than one full cycle.' bit_offset: 0 bit_size: 2 - name: HS400_MODE description: Set 1 to enable HS400 mode. bit_offset: 31 bit_size: 1 fieldset/ENSHIFT: description: Enable Phase Shift register. fields: - name: ENABLE_SHIFT description: Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. 2'b00-Default phase shift. 2'b01-Enables shifted to next immediate positive edge. 2'b10-Enables shifted to next immediate negative edge. 2'b11-Reserved. bit_offset: 0 bit_size: 4 fieldset/FIFOTH: description: FIFO configuration register. fields: - name: TX_WMARK description: FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. bit_offset: 0 bit_size: 12 - name: RX_WMARK description: FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. bit_offset: 16 bit_size: 11 - name: DMA_MULTIPLE_TRANSACTION_SIZE description: 'Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer.' bit_offset: 28 bit_size: 3 fieldset/HCON: description: Hardware feature register. fields: - name: CARD_TYPE description: Hardware support SDIO and MMC. bit_offset: 0 bit_size: 1 - name: CARD_NUM description: Support card number is 2. bit_offset: 1 bit_size: 5 - name: BUS_TYPE description: Register config is APB bus. bit_offset: 6 bit_size: 1 - name: DATA_WIDTH description: Regisger data widht is 32. bit_offset: 7 bit_size: 3 - name: ADDR_WIDTH description: Register address width is 32. bit_offset: 10 bit_size: 6 - name: DMA_WIDTH description: DMA data witdth is 32. bit_offset: 18 bit_size: 3 - name: RAM_INDISE description: Inside RAM in SDMMC module. bit_offset: 21 bit_size: 1 - name: HOLD description: Have a hold regiser in data path. bit_offset: 22 bit_size: 1 - name: NUM_CLK_DIV description: Have 4 clk divider in design. bit_offset: 24 bit_size: 2 fieldset/IDINTEN: description: IDMAC interrupt enable register. fields: - name: TI description: Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled. bit_offset: 0 bit_size: 1 - name: RI description: Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled. bit_offset: 1 bit_size: 1 - name: FBE description: Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled. bit_offset: 2 bit_size: 1 - name: DU description: Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled. bit_offset: 4 bit_size: 1 - name: CES description: Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary. bit_offset: 5 bit_size: 1 - name: NI description: 'Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0]: Transmit Interrupt; IDINTEN[1]: Receive Interrupt.' bit_offset: 8 bit_size: 1 - name: AI description: 'Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2]: Fatal Bus Error Interrupt; IDINTEN[4]: DU Interrupt.' bit_offset: 9 bit_size: 1 fieldset/IDSTS: description: IDMAC status register. fields: - name: TI description: Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit. bit_offset: 0 bit_size: 1 - name: RI description: Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit. bit_offset: 1 bit_size: 1 - name: FBE description: Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit. bit_offset: 2 bit_size: 1 - name: DU description: Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit. bit_offset: 4 bit_size: 1 - name: CES description: 'Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error; RTO : Response Timeout/Boot Ack Timeout; RCRC : Response CRC; SBE : Start Bit Error; DRTO : Data Read Timeout/BDS timeout; DCRC : Data CRC for Receive; RE : Response Error. Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error.' bit_offset: 5 bit_size: 1 - name: NIS description: 'Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit.' bit_offset: 8 bit_size: 1 - name: AIS description: 'Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit.' bit_offset: 9 bit_size: 1 - name: FBE_CODE description: 'Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an interrupt. 001: Host Abort received during transmission; 010: Host Abort received during reception; Others: Reserved.' bit_offset: 10 bit_size: 3 - name: FSM description: 'DMAC FSM present state. 0: DMA_IDLE (idle state); 1: DMA_SUSPEND (suspend state); 2: DESC_RD (descriptor reading state); 3: DESC_CHK (descriptor checking state); 4: DMA_RD_REQ_WAIT (read-data request waiting state); 5: DMA_WR_REQ_WAIT (write-data request waiting state); 6: DMA_RD (data-read state); 7: DMA_WR (data-write state); 8: DESC_CLOSE (descriptor close state).' bit_offset: 13 bit_size: 4 fieldset/INTMASK: description: SDIO interrupt mask register. fields: - name: INT_MASK description: 'These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): Rx Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation-by-host timeout; Bit 9 (DRTO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect.' bit_offset: 0 bit_size: 16 - name: SDIO_INT_MASK description: SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt. bit_offset: 16 bit_size: 2 fieldset/MINTSTS: description: Masked interrupt status register. fields: - name: INT_STATUS_MSK description: 'Interrupt enabled only if corresponding bit in interrupt mask register is set. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect.' bit_offset: 0 bit_size: 16 - name: SDIO_INTERRUPT_MSK description: Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt). bit_offset: 16 bit_size: 2 fieldset/PLDMND: description: Poll demand configuration register. fields: - name: PD description: Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only. bit_offset: 0 bit_size: 32 fieldset/RESP0: description: Response data register. fields: - name: RESPONSE0 description: Bit[31:0] of response. bit_offset: 0 bit_size: 32 fieldset/RESP1: description: Long response data register. fields: - name: RESPONSE1 description: Bit[63:32] of long response. bit_offset: 0 bit_size: 32 fieldset/RESP2: description: Long response data register. fields: - name: RESPONSE2 description: Bit[95:64] of long response. bit_offset: 0 bit_size: 32 fieldset/RESP3: description: Long response data register. fields: - name: RESPONSE3 description: Bit[127:96] of long response. bit_offset: 0 bit_size: 32 fieldset/RINTSTS: description: Raw interrupt status register. fields: - name: INT_STATUS_RAW description: 'Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect.' bit_offset: 0 bit_size: 16 - name: SDIO_INTERRUPT_RAW description: 'Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. 0: No SDIO interrupt from card; 1: SDIO interrupt from card.' bit_offset: 16 bit_size: 2 fieldset/RST_N: description: Card reset register. fields: - name: CARD_RESET description: 'Hardware reset. 1: Active mode; 0: Reset. These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1''b0 to reset card0, SDHOST_RST_CARD_RESET[1] should be set to 1''b0 to reset card1.' bit_offset: 0 bit_size: 2 fieldset/STATUS: description: SD/MMC status register. fields: - name: FIFO_RX_WATERMARK description: FIFO reached Receive watermark level, not qualified with data transfer. bit_offset: 0 bit_size: 1 - name: FIFO_TX_WATERMARK description: FIFO reached Transmit watermark level, not qualified with data transfer. bit_offset: 1 bit_size: 1 - name: FIFO_EMPTY description: FIFO is empty status. bit_offset: 2 bit_size: 1 - name: FIFO_FULL description: FIFO is full status. bit_offset: 3 bit_size: 1 - name: COMMAND_FSM_STATES description: 'Command FSM states. 0: Idle; 1: Send init sequence; 2: Send cmd start bit; 3: Send cmd tx bit; 4: Send cmd index + arg; 5: Send cmd crc7; 6: Send cmd end bit; 7: Receive resp start bit; 8: Receive resp IRQ response; 9: Receive resp tx bit; 10: Receive resp cmd idx; 11: Receive resp data; 12: Receive resp crc7; 13: Receive resp end bit; 14: Cmd path wait NCC; 15: Wait, cmd-to-response turnaround.' bit_offset: 4 bit_size: 4 - name: DATA_3_STATUS description: 'Raw selected sdhost_card_data[3], checks whether card is present. 0: card not present; 1: card present.' bit_offset: 8 bit_size: 1 - name: DATA_BUSY description: 'Inverted version of raw selected sdhost_card_data[0]. 0: Card data not busy; 1: Card data busy.' bit_offset: 9 bit_size: 1 - name: DATA_STATE_MC_BUSY description: Data transmit or receive state-machine is busy. bit_offset: 10 bit_size: 1 - name: RESPONSE_INDEX description: Index of previous response, including any auto-stop sent by core. bit_offset: 11 bit_size: 6 - name: FIFO_COUNT description: FIFO count, number of filled locations in FIFO. bit_offset: 17 bit_size: 13 fieldset/TBBCNT: description: Transferred byte count register. fields: - name: TBBCNT description: Number of bytes transferred between Host/DMA memory and BIU FIFO. bit_offset: 0 bit_size: 32 fieldset/TCBCNT: description: Transferred byte count register. fields: - name: TCBCNT description: Number of bytes transferred by CIU unit to card. bit_offset: 0 bit_size: 32 fieldset/TMOUT: description: Data and response timeout configuration register. fields: - name: RESPONSE_TIMEOUT description: Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out. bit_offset: 0 bit_size: 8 - name: DATA_TIMEOUT description: 'Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled.' bit_offset: 8 bit_size: 24 fieldset/UHS: description: UHS-1 register. fields: - name: DDR description: DDR mode selecton,1 bit for each card. 0-Non-DDR mdoe. 1-DDR mdoe. bit_offset: 16 bit_size: 2 fieldset/USRID: description: User ID (scratchpad) register. fields: - name: USRID description: User identification register, value set by user. Can also be used as a scratchpad register by user. bit_offset: 0 bit_size: 32 fieldset/VERID: description: Version ID (scratchpad) register. fields: - name: VERSIONID description: Hardware version register. Can also be read by fireware. bit_offset: 0 bit_size: 32 fieldset/WRTPRT: description: Card write protection (WP) status register. fields: - name: WRITE_PROTECT description: Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write protection. Only NUM_CARDS number of bits are implemented. bit_offset: 0 bit_size: 2