block/RMT:
  description: Remote Control.
  items:
  - name: CHDATA
    array:
      len: 8
      stride: 4
    byte_offset: 0
  - name: CHCONF0
    array:
      len: 8
      stride: 8
    byte_offset: 32
    fieldset: CHCONF0
  - name: CHCONF1
    array:
      len: 8
      stride: 8
    byte_offset: 36
    fieldset: CHCONF1
  - name: CHSTATUS
    array:
      len: 8
      stride: 4
    byte_offset: 96
    fieldset: CHSTATUS
  - name: CHADDR
    array:
      len: 8
      stride: 4
    byte_offset: 128
    fieldset: CHADDR
  - name: INT_RAW
    byte_offset: 160
    fieldset: INT_RAW
  - name: INT_ST
    byte_offset: 164
    fieldset: INT_ST
  - name: INT_ENA
    byte_offset: 168
    fieldset: INT_ENA
  - name: INT_CLR
    byte_offset: 172
    fieldset: INT_CLR
  - name: CHCARRIER_DUTY
    array:
      len: 8
      stride: 4
    byte_offset: 176
    fieldset: CHCARRIER_DUTY
  - name: CH_TX_LIM
    array:
      len: 8
      stride: 4
    byte_offset: 208
    fieldset: CH_TX_LIM
  - name: APB_CONF
    byte_offset: 240
    fieldset: APB_CONF
  - name: DATE
    byte_offset: 252
    fieldset: DATE
fieldset/APB_CONF:
  fields:
  - name: APB_FIFO_MASK
    description: Set this bit to disable apb fifo access.
    bit_offset: 0
    bit_size: 1
  - name: MEM_TX_WRAP_EN
    description: when datas need to be send is more than channel's mem can store then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn.
    bit_offset: 1
    bit_size: 1
fieldset/CHADDR:
  fields:
  - name: APB_MEM_ADDR
    description: The ram relative address in channel0 by apb fifo access.
    bit_offset: 0
    bit_size: 32
fieldset/CHCARRIER_DUTY:
  fields:
  - name: CARRIER_LOW
    description: This register is used to configure carrier wave's low level value for channel0.
    bit_offset: 0
    bit_size: 16
  - name: CARRIER_HIGH
    description: This register is used to configure carrier wave's high level value for channel0.
    bit_offset: 16
    bit_size: 16
fieldset/CHCONF0:
  fields:
  - name: DIV_CNT
    description: This register is used to configure the frequency divider's factor in channel0.
    bit_offset: 0
    bit_size: 8
  - name: IDLE_THRES
    description: In receive mode when no edge is detected on the input signal for longer than reg_idle_thres_ch0 then the receive process is done.
    bit_offset: 8
    bit_size: 16
  - name: MEM_SIZE
    description: This register is used to configure the the amount of memory blocks allocated to channel0.
    bit_offset: 24
    bit_size: 4
  - name: CARRIER_EN
    description: This is the carrier modulation enable control bit for channel0.
    bit_offset: 28
    bit_size: 1
  - name: CARRIER_OUT_LV
    description: This bit is used to configure the way carrier wave is modulated for channel0.1'b1:transmit on low output level 1'b0:transmit on high output level.
    bit_offset: 29
    bit_size: 1
  - name: MEM_PD
    description: This bit is used to reduce power consumed by mem. 1:mem is in low power state.
    bit_offset: 30
    bit_size: 1
  - name: CLK_EN
    description: This bit is used to control clock.when software config RMT internal registers it controls the register clock.
    bit_offset: 31
    bit_size: 1
fieldset/CHCONF1:
  fields:
  - name: TX_START
    description: Set this bit to start sending data for channel0.
    bit_offset: 0
    bit_size: 1
  - name: RX_EN
    description: Set this bit to enbale receving data for channel0.
    bit_offset: 1
    bit_size: 1
  - name: MEM_WR_RST
    description: Set this bit to reset write ram address for channel0 by receiver access.
    bit_offset: 2
    bit_size: 1
  - name: MEM_RD_RST
    description: Set this bit to reset read ram address for channel0 by transmitter access.
    bit_offset: 3
    bit_size: 1
  - name: APB_MEM_RST
    description: Set this bit to reset W/R ram address for channel0 by apb fifo access.
    bit_offset: 4
    bit_size: 1
  - name: MEM_OWNER
    description: This is the mark of channel0's ram usage right.1'b1：receiver uses the ram 0：transmitter uses the ram.
    bit_offset: 5
    bit_size: 1
  - name: TX_CONTI_MODE
    description: Set this bit to continue sending from the first data to the last data in channel0 again and again.
    bit_offset: 6
    bit_size: 1
  - name: RX_FILTER_EN
    description: This is the receive filter enable bit for channel0.
    bit_offset: 7
    bit_size: 1
  - name: RX_FILTER_THRES
    description: in receive mode channel0 ignore input pulse when the pulse width is smaller then this value.
    bit_offset: 8
    bit_size: 8
  - name: REF_CNT_RST
    description: This bit is used to reset divider in channel0.
    bit_offset: 16
    bit_size: 1
  - name: REF_ALWAYS_ON
    description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref.
    bit_offset: 17
    bit_size: 1
  - name: IDLE_OUT_LV
    description: This bit configures the output signal's level for channel0 in IDLE state.
    bit_offset: 18
    bit_size: 1
  - name: IDLE_OUT_EN
    description: This is the output enable control bit for channel0 in IDLE state.
    bit_offset: 19
    bit_size: 1
fieldset/CHSTATUS:
  fields:
  - name: MEM_WADDR_EX
    description: The current memory read address of channel0.
    bit_offset: 0
    bit_size: 10
  - name: STATUS
    description: The status for channel0.
    bit_offset: 0
    bit_size: 32
  - name: MEM_RADDR_EX
    description: The current memory write address of channel0.
    bit_offset: 12
    bit_size: 10
  - name: STATE
    description: 'The channel0 state machine status register.3''h0 : idle, 3''h1 : send, 3''h2 : read memory, 3''h3 : receive, 3''h4 : wait.'
    bit_offset: 24
    bit_size: 3
  - name: MEM_OWNER_ERR
    description: When channel0 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1.
    bit_offset: 27
    bit_size: 1
  - name: MEM_FULL
    description: The memory full status bit for channel0 turns to high level when mem_waddr_ex is greater than or equal to the configuration range.
    bit_offset: 28
    bit_size: 1
  - name: MEM_EMPTY
    description: The memory empty status bit for channel0. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.
    bit_offset: 29
    bit_size: 1
  - name: APB_MEM_WR_ERR
    description: The apb write memory status bit for channel0 turns to high level when the apb write address exceeds the configuration range.
    bit_offset: 30
    bit_size: 1
  - name: APB_MEM_RD_ERR
    description: The apb read memory status bit for channel0 turns to high level when the apb read address exceeds the configuration range.
    bit_offset: 31
    bit_size: 1
fieldset/CH_TX_LIM:
  fields:
  - name: TX_LIM
    description: When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0 produce the relative interrupt.
    bit_offset: 0
    bit_size: 9
fieldset/DATE:
  fields:
  - name: DATE
    description: This is the version register.
    bit_offset: 0
    bit_size: 32
fieldset/INT_CLR:
  fields:
  - name: CH_TX_END
    description: Set this bit to clear the rmt_ch%s_rx_end_int_raw..
    bit_offset: 0
    bit_size: 1
    array:
      len: 8
      stride: 3
  - name: CH_RX_END
    description: Set this bit to clear the rmt_ch%s_tx_end_int_raw.
    bit_offset: 1
    bit_size: 1
    array:
      len: 8
      stride: 3
  - name: CH_ERR
    description: Set this bit to clear the rmt_ch%s_err_int_raw.
    bit_offset: 2
    bit_size: 1
    array:
      len: 8
      stride: 3
  - name: CH_TX_THR_EVENT
    description: Set this bit to clear the rmt_ch%s_tx_thr_event_int_raw interrupt.
    bit_offset: 24
    bit_size: 1
    array:
      len: 8
      stride: 1
fieldset/INT_ENA:
  fields:
  - name: CH_TX_END
    description: Set this bit to enable rmt_ch%s_tx_end_int_st.
    bit_offset: 0
    bit_size: 1
    array:
      len: 8
      stride: 3
  - name: CH_RX_END
    description: Set this bit to enable rmt_ch%s_rx_end_int_st.
    bit_offset: 1
    bit_size: 1
    array:
      len: 8
      stride: 3
  - name: CH_ERR
    description: Set this bit to enable rmt_ch%s_err_int_st.
    bit_offset: 2
    bit_size: 1
    array:
      len: 8
      stride: 3
  - name: CH_TX_THR_EVENT
    description: Set this bit to enable rmt_ch%s_tx_thr_event_int_st.
    bit_offset: 24
    bit_size: 1
    array:
      len: 8
      stride: 1
fieldset/INT_RAW:
  fields:
  - name: CH_TX_END
    description: The interrupt raw bit for channel %s turns to high level when the transmit process is done.
    bit_offset: 0
    bit_size: 1
    array:
      len: 8
      stride: 3
  - name: CH_RX_END
    description: The interrupt raw bit for channel %s turns to high level when the receive process is done.
    bit_offset: 1
    bit_size: 1
    array:
      len: 8
      stride: 3
  - name: CH_ERR
    description: The interrupt raw bit for channel %s turns to high level when channle %s detects some errors.
    bit_offset: 2
    bit_size: 1
    array:
      len: 8
      stride: 3
  - name: CH_TX_THR_EVENT
    description: The interrupt raw bit for channel %s turns to high level when transmitter in channle%s have send datas more than reg_rmt_tx_lim_ch%s after detecting this interrupt software can updata the old datas with new datas.
    bit_offset: 24
    bit_size: 1
    array:
      len: 8
      stride: 1
fieldset/INT_ST:
  fields:
  - name: CH_TX_END
    description: The interrupt state bit for channel %s's mt_ch%s_tx_end_int_raw when mt_ch%s_tx_end_int_ena is set to %s.
    bit_offset: 0
    bit_size: 1
    array:
      len: 8
      stride: 3
  - name: CH_RX_END
    description: The interrupt state bit for channel %s's rmt_ch%s_rx_end_int_raw when rmt_ch%s_rx_end_int_ena is set to %s.
    bit_offset: 1
    bit_size: 1
    array:
      len: 8
      stride: 3
  - name: CH_ERR
    description: The interrupt state bit for channel %s's rmt_ch%s_err_int_raw when rmt_ch%s_err_int_ena is set to %s.
    bit_offset: 2
    bit_size: 1
    array:
      len: 8
      stride: 3
  - name: CH_TX_THR_EVENT
    description: The interrupt state bit for channel %s's rmt_ch%s_tx_thr_event_int_raw when mt_ch%s_tx_thr_event_int_ena is set to 1.
    bit_offset: 24
    bit_size: 1
    array:
      len: 8
      stride: 1