block/I2C0: description: I2C (Inter-Integrated Circuit) Controller 0. items: - name: SCL_LOW_PERIOD byte_offset: 0 fieldset: SCL_LOW_PERIOD - name: CTR byte_offset: 4 fieldset: CTR - name: SR byte_offset: 8 fieldset: SR - name: TO byte_offset: 12 fieldset: TO - name: SLAVE_ADDR byte_offset: 16 fieldset: SLAVE_ADDR - name: RXFIFO_ST byte_offset: 20 fieldset: RXFIFO_ST - name: FIFO_CONF byte_offset: 24 fieldset: FIFO_CONF - name: DATA byte_offset: 28 fieldset: DATA - name: INT_RAW byte_offset: 32 fieldset: INT_RAW - name: INT_CLR byte_offset: 36 fieldset: INT_CLR - name: INT_ENA byte_offset: 40 fieldset: INT_ENA - name: INT_STATUS byte_offset: 44 fieldset: INT_STATUS - name: SDA_HOLD byte_offset: 48 fieldset: SDA_HOLD - name: SDA_SAMPLE byte_offset: 52 fieldset: SDA_SAMPLE - name: SCL_HIGH_PERIOD byte_offset: 56 fieldset: SCL_HIGH_PERIOD - name: SCL_START_HOLD byte_offset: 64 fieldset: SCL_START_HOLD - name: SCL_RSTART_SETUP byte_offset: 68 fieldset: SCL_RSTART_SETUP - name: SCL_STOP_HOLD byte_offset: 72 fieldset: SCL_STOP_HOLD - name: SCL_STOP_SETUP byte_offset: 76 fieldset: SCL_STOP_SETUP - name: SCL_FILTER_CFG byte_offset: 80 fieldset: SCL_FILTER_CFG - name: SDA_FILTER_CFG byte_offset: 84 fieldset: SDA_FILTER_CFG - name: COMD array: len: 16 stride: 4 byte_offset: 88 fieldset: COMD - name: DATE byte_offset: 248 fieldset: DATE - name: FIFO_START_ADDR byte_offset: 256 fieldset/COMD: fields: - name: COMMAND description: 'This is the content of command0. It consists of three part. op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.' bit_offset: 0 bit_size: 14 - name: COMMAND_DONE description: When command0 is done in I2C Master mode this bit changes to high level. bit_offset: 31 bit_size: 1 fieldset/CTR: fields: - name: SDA_FORCE_OUT description: '1: normally ouput sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal).' bit_offset: 0 bit_size: 1 - name: SCL_FORCE_OUT description: '1: normally ouput scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal).' bit_offset: 1 bit_size: 1 - name: SAMPLE_SCL_LEVEL description: Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level. bit_offset: 2 bit_size: 1 - name: MS_MODE description: Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave. bit_offset: 4 bit_size: 1 - name: TRANS_START description: Set this bit to start sending data in txfifo. bit_offset: 5 bit_size: 1 - name: TX_LSB_FIRST description: 'This bit is used to control the sending mode for data need to be send. 1: receive data from most significant bit 0: receive data from least significant bit.' bit_offset: 6 bit_size: 1 - name: RX_LSB_FIRST description: 'This bit is used to control the storage mode for received datas. 1: receive data from most significant bit 0: receive data from least significant bit.' bit_offset: 7 bit_size: 1 - name: CLK_EN description: This is the clock gating control bit for reading or writing registers. bit_offset: 8 bit_size: 1 fieldset/DATA: fields: - name: FIFO_RDATA description: The register represent the byte data read from rxfifo when use apb fifo access. bit_offset: 0 bit_size: 8 fieldset/DATE: fields: - name: DATE bit_offset: 0 bit_size: 32 fieldset/FIFO_CONF: fields: - name: RXFIFO_FULL_THRHD bit_offset: 0 bit_size: 5 - name: TXFIFO_EMPTY_THRHD description: Config txfifo empty threhd value when using apb fifo access. bit_offset: 5 bit_size: 5 - name: NONFIFO_EN description: Set this bit to enble apb nonfifo access. bit_offset: 10 bit_size: 1 - name: FIFO_ADDR_CFG_EN description: When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram. bit_offset: 11 bit_size: 1 - name: RX_FIFO_RST description: Set this bit to reset rx fifo when using apb fifo access. bit_offset: 12 bit_size: 1 - name: TX_FIFO_RST description: Set this bit to reset tx fifo when using apb fifo access. bit_offset: 13 bit_size: 1 - name: NONFIFO_RX_THRES description: when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data. bit_offset: 14 bit_size: 6 - name: NONFIFO_TX_THRES description: when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data. bit_offset: 20 bit_size: 6 fieldset/INT_CLR: fields: - name: RXFIFO_FULL_INT_CLR description: Set this bit to clear the rxfifo_full_int interrupt. bit_offset: 0 bit_size: 1 - name: TXFIFO_EMPTY_INT_CLR description: Set this bit to clear the txfifo_empty_int interrupt. bit_offset: 1 bit_size: 1 - name: RXFIFO_OVF_INT_CLR description: Set this bit to clear the rxfifo_ovf_int interrupt. bit_offset: 2 bit_size: 1 - name: END_DETECT_INT_CLR description: Set this bit to clear the end_detect_int interrupt. bit_offset: 3 bit_size: 1 - name: SLAVE_TRAN_COMP_INT_CLR description: Set this bit to clear the slave_tran_comp_int interrupt. bit_offset: 4 bit_size: 1 - name: ARBITRATION_LOST_INT_CLR description: Set this bit to clear the arbitration_lost_int interrupt. bit_offset: 5 bit_size: 1 - name: MASTER_TRAN_COMP_INT_CLR description: Set this bit to clear the master_tran_comp interrupt. bit_offset: 6 bit_size: 1 - name: TRANS_COMPLETE_INT_CLR description: Set this bit to clear the trans_complete_int interrupt. bit_offset: 7 bit_size: 1 - name: TIME_OUT_INT_CLR description: Set this bit to clear the time_out_int interrupt. bit_offset: 8 bit_size: 1 - name: TRANS_START_INT_CLR description: Set this bit to clear the trans_start_int interrupt. bit_offset: 9 bit_size: 1 - name: ACK_ERR_INT_CLR description: Set this bit to clear the ack_err_int interrupt. bit_offset: 10 bit_size: 1 - name: RX_REC_FULL_INT_CLR description: Set this bit to clear the rx_rec_full_int interrupt. bit_offset: 11 bit_size: 1 - name: TX_SEND_EMPTY_INT_CLR description: Set this bit to clear the tx_send_empty_int interrupt. bit_offset: 12 bit_size: 1 fieldset/INT_ENA: fields: - name: RXFIFO_FULL_INT_ENA description: The enable bit for rxfifo_full_int interrupt. bit_offset: 0 bit_size: 1 - name: TXFIFO_EMPTY_INT_ENA description: The enable bit for txfifo_empty_int interrupt. bit_offset: 1 bit_size: 1 - name: RXFIFO_OVF_INT_ENA description: The enable bit for rxfifo_ovf_int interrupt. bit_offset: 2 bit_size: 1 - name: END_DETECT_INT_ENA description: The enable bit for end_detect_int interrupt. bit_offset: 3 bit_size: 1 - name: SLAVE_TRAN_COMP_INT_ENA description: The enable bit for slave_tran_comp_int interrupt. bit_offset: 4 bit_size: 1 - name: ARBITRATION_LOST_INT_ENA description: The enable bit for arbitration_lost_int interrupt. bit_offset: 5 bit_size: 1 - name: MASTER_TRAN_COMP_INT_ENA description: The enable bit for master_tran_comp_int interrupt. bit_offset: 6 bit_size: 1 - name: TRANS_COMPLETE_INT_ENA description: The enable bit for trans_complete_int interrupt. bit_offset: 7 bit_size: 1 - name: TIME_OUT_INT_ENA description: The enable bit for time_out_int interrupt. bit_offset: 8 bit_size: 1 - name: TRANS_START_INT_ENA description: The enable bit for trans_start_int interrupt. bit_offset: 9 bit_size: 1 - name: ACK_ERR_INT_ENA description: The enable bit for ack_err_int interrupt. bit_offset: 10 bit_size: 1 - name: RX_REC_FULL_INT_ENA description: The enable bit for rx_rec_full_int interrupt. bit_offset: 11 bit_size: 1 - name: TX_SEND_EMPTY_INT_ENA description: The enable bit for tx_send_empty_int interrupt. bit_offset: 12 bit_size: 1 fieldset/INT_RAW: fields: - name: RXFIFO_FULL_INT_RAW description: The raw interrupt status bit for rxfifo full when use apb fifo access. bit_offset: 0 bit_size: 1 - name: TXFIFO_EMPTY_INT_RAW description: The raw interrupt status bit for txfifo empty when use apb fifo access. bit_offset: 1 bit_size: 1 - name: RXFIFO_OVF_INT_RAW description: The raw interrupt status bit for receiving data overflow when use apb fifo access. bit_offset: 2 bit_size: 1 - name: END_DETECT_INT_RAW description: The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt. bit_offset: 3 bit_size: 1 - name: SLAVE_TRAN_COMP_INT_RAW description: The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt. bit_offset: 4 bit_size: 1 - name: ARBITRATION_LOST_INT_RAW description: The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt. bit_offset: 5 bit_size: 1 - name: MASTER_TRAN_COMP_INT_RAW description: The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt. bit_offset: 6 bit_size: 1 - name: TRANS_COMPLETE_INT_RAW description: The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt. bit_offset: 7 bit_size: 1 - name: TIME_OUT_INT_RAW description: The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt. bit_offset: 8 bit_size: 1 - name: TRANS_START_INT_RAW description: The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt. bit_offset: 9 bit_size: 1 - name: ACK_ERR_INT_RAW description: The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt.. bit_offset: 10 bit_size: 1 - name: RX_REC_FULL_INT_RAW description: The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt. bit_offset: 11 bit_size: 1 - name: TX_SEND_EMPTY_INT_RAW description: The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt.. bit_offset: 12 bit_size: 1 fieldset/INT_STATUS: fields: - name: RXFIFO_FULL_INT_ST description: The masked interrupt status for rxfifo_full_int interrupt. bit_offset: 0 bit_size: 1 - name: TXFIFO_EMPTY_INT_ST description: The masked interrupt status for txfifo_empty_int interrupt. bit_offset: 1 bit_size: 1 - name: RXFIFO_OVF_INT_ST description: The masked interrupt status for rxfifo_ovf_int interrupt. bit_offset: 2 bit_size: 1 - name: END_DETECT_INT_ST description: The masked interrupt status for end_detect_int interrupt. bit_offset: 3 bit_size: 1 - name: SLAVE_TRAN_COMP_INT_ST description: The masked interrupt status for slave_tran_comp_int interrupt. bit_offset: 4 bit_size: 1 - name: ARBITRATION_LOST_INT_ST description: The masked interrupt status for arbitration_lost_int interrupt. bit_offset: 5 bit_size: 1 - name: MASTER_TRAN_COMP_INT_ST description: The masked interrupt status for master_tran_comp_int interrupt. bit_offset: 6 bit_size: 1 - name: TRANS_COMPLETE_INT_ST description: The masked interrupt status for trans_complete_int interrupt. bit_offset: 7 bit_size: 1 - name: TIME_OUT_INT_ST description: The masked interrupt status for time_out_int interrupt. bit_offset: 8 bit_size: 1 - name: TRANS_START_INT_ST description: The masked interrupt status for trans_start_int interrupt. bit_offset: 9 bit_size: 1 - name: ACK_ERR_INT_ST description: The masked interrupt status for ack_err_int interrupt. bit_offset: 10 bit_size: 1 - name: RX_REC_FULL_INT_ST description: The masked interrupt status for rx_rec_full_int interrupt. bit_offset: 11 bit_size: 1 - name: TX_SEND_EMPTY_INT_ST description: The masked interrupt status for tx_send_empty_int interrupt. bit_offset: 12 bit_size: 1 fieldset/RXFIFO_ST: fields: - name: RXFIFO_START_ADDR description: This is the offset address of the last receiving data as described in nonfifo_rx_thres_register. bit_offset: 0 bit_size: 5 - name: RXFIFO_END_ADDR description: This is the offset address of the first receiving data as described in nonfifo_rx_thres_register. bit_offset: 5 bit_size: 5 - name: TXFIFO_START_ADDR description: This is the offset address of the first sending data as described in nonfifo_tx_thres register. bit_offset: 10 bit_size: 5 - name: TXFIFO_END_ADDR description: This is the offset address of the last sending data as described in nonfifo_tx_thres register. bit_offset: 15 bit_size: 5 fieldset/SCL_FILTER_CFG: fields: - name: SCL_FILTER_THRES description: When input SCL's pulse width is smaller than this register value I2C ignores this pulse. bit_offset: 0 bit_size: 3 - name: SCL_FILTER_EN description: This is the filter enable bit for SCL. bit_offset: 3 bit_size: 1 fieldset/SCL_HIGH_PERIOD: fields: - name: SCL_HIGH_PERIOD description: This register is used to configure the clock num during SCL is low level. bit_offset: 0 bit_size: 14 fieldset/SCL_LOW_PERIOD: fields: - name: SCL_LOW_PERIOD description: This register is used to configure the low level width of SCL clock. bit_offset: 0 bit_size: 14 fieldset/SCL_RSTART_SETUP: fields: - name: TIME description: This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark. bit_offset: 0 bit_size: 10 fieldset/SCL_START_HOLD: fields: - name: TIME description: This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark. bit_offset: 0 bit_size: 10 fieldset/SCL_STOP_HOLD: fields: - name: TIME description: This register is used to configure the clock num after the STOP bit's posedge. bit_offset: 0 bit_size: 14 fieldset/SCL_STOP_SETUP: fields: - name: TIME description: This register is used to configure the clock num between the posedge of SCL and the posedge of SDA. bit_offset: 0 bit_size: 10 fieldset/SDA_FILTER_CFG: fields: - name: SDA_FILTER_THRES description: When input SCL's pulse width is smaller than this register value I2C ignores this pulse. bit_offset: 0 bit_size: 3 - name: SDA_FILTER_EN description: This is the filter enable bit for SDA. bit_offset: 3 bit_size: 1 fieldset/SDA_HOLD: fields: - name: TIME description: This register is used to configure the clock num I2C used to hold the data after the negedge of SCL. bit_offset: 0 bit_size: 10 fieldset/SDA_SAMPLE: fields: - name: TIME description: This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL. bit_offset: 0 bit_size: 10 fieldset/SLAVE_ADDR: fields: - name: SLAVE_ADDR description: when configured as i2c slave this register is used to configure slave's address. bit_offset: 0 bit_size: 15 - name: ADDR_10BIT_EN description: This register is used to enable slave 10bit address mode. bit_offset: 31 bit_size: 1 fieldset/SR: fields: - name: ACK_REC description: This register stores the value of ACK bit. bit_offset: 0 bit_size: 1 - name: SLAVE_RW description: 'when in slave mode 1: master read slave 0: master write slave.' bit_offset: 1 bit_size: 1 - name: TIME_OUT description: when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level. bit_offset: 2 bit_size: 1 - name: ARB_LOST description: when I2C lost control of SDA line this register changes to high level. bit_offset: 3 bit_size: 1 - name: BUS_BUSY description: 1:I2C bus is busy transferring data. 0:I2C bus is in idle state. bit_offset: 4 bit_size: 1 - name: SLAVE_ADDRESSED description: when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level. bit_offset: 5 bit_size: 1 - name: BYTE_TRANS description: This register changes to high level when one byte is transferred. bit_offset: 6 bit_size: 1 - name: RXFIFO_CNT description: This register represent the amount of data need to send. bit_offset: 8 bit_size: 6 - name: TXFIFO_CNT description: This register stores the amount of received data in ram. bit_offset: 18 bit_size: 6 - name: SCL_MAIN_STATE_LAST description: 'This register stores the value of state machine for i2c module. 3''h0: SCL_MAIN_IDLE 3''h1: SCL_ADDRESS_SHIFT 3''h2: SCL_ACK_ADDRESS 3''h3: SCL_RX_DATA 3''h4 SCL_TX_DATA 3''h5:SCL_SEND_ACK 3''h6:SCL_WAIT_ACK.' bit_offset: 24 bit_size: 3 - name: SCL_STATE_LAST description: 'This register stores the value of state machine to produce SCL. 3''h0: SCL_IDLE 3''h1:SCL_START 3''h2:SCL_LOW_EDGE 3''h3: SCL_LOW 3''h4:SCL_HIGH_EDGE 3''h5:SCL_HIGH 3''h6:SCL_STOP.' bit_offset: 28 bit_size: 3 fieldset/TO: fields: - name: TIME_OUT description: This register is used to configure the max clock number of receiving a data. bit_offset: 0 bit_size: 20