block/APB_CTRL:
  description: APB (Advanced Peripheral Bus) Controller.
  items:
  - name: SYSCLK_CONF
    byte_offset: 0
    fieldset: SYSCLK_CONF
  - name: XTAL_TICK_CONF
    byte_offset: 4
    fieldset: XTAL_TICK_CONF
  - name: PLL_TICK_CONF
    byte_offset: 8
    fieldset: PLL_TICK_CONF
  - name: CK8M_TICK_CONF
    byte_offset: 12
    fieldset: CK8M_TICK_CONF
  - name: APB_SARADC_CTRL
    byte_offset: 16
    fieldset: APB_SARADC_CTRL
  - name: APB_SARADC_CTRL2
    byte_offset: 20
    fieldset: APB_SARADC_CTRL2
  - name: APB_SARADC_FSM
    byte_offset: 24
    fieldset: APB_SARADC_FSM
  - name: APB_SARADC_SAR1_PATT_TAB
    array:
      len: 4
      stride: 4
    byte_offset: 28
    fieldset: APB_SARADC_SAR1_PATT_TAB
  - name: APB_SARADC_SAR2_PATT_TAB
    array:
      len: 4
      stride: 4
    byte_offset: 44
    fieldset: APB_SARADC_SAR2_PATT_TAB
  - name: APLL_TICK_CONF
    byte_offset: 60
    fieldset: APLL_TICK_CONF
  - name: DATE
    byte_offset: 124
    fieldset: DATE
fieldset/APB_SARADC_CTRL:
  fields:
  - name: SARADC_START_FORCE
    bit_offset: 0
    bit_size: 1
  - name: SARADC_START
    bit_offset: 1
    bit_size: 1
  - name: SARADC_SAR2_MUX
    description: '1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL.'
    bit_offset: 2
    bit_size: 1
  - name: SARADC_WORK_MODE
    description: '0: single mode 1: double mode 2: alternate mode.'
    bit_offset: 3
    bit_size: 2
  - name: SARADC_SAR_SEL
    description: '0: SAR1 1: SAR2 only work for single SAR mode.'
    bit_offset: 5
    bit_size: 1
  - name: SARADC_SAR_CLK_GATED
    bit_offset: 6
    bit_size: 1
  - name: SARADC_SAR_CLK_DIV
    description: SAR clock divider.
    bit_offset: 7
    bit_size: 8
  - name: SARADC_SAR1_PATT_LEN
    description: 0 ~ 15 means length 1 ~ 16.
    bit_offset: 15
    bit_size: 4
  - name: SARADC_SAR2_PATT_LEN
    description: 0 ~ 15 means length 1 ~ 16.
    bit_offset: 19
    bit_size: 4
  - name: SARADC_SAR1_PATT_P_CLEAR
    description: clear the pointer of pattern table for DIG ADC1 CTRL.
    bit_offset: 23
    bit_size: 1
  - name: SARADC_SAR2_PATT_P_CLEAR
    description: clear the pointer of pattern table for DIG ADC2 CTRL.
    bit_offset: 24
    bit_size: 1
  - name: SARADC_DATA_SAR_SEL
    description: '1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.'
    bit_offset: 25
    bit_size: 1
  - name: SARADC_DATA_TO_I2S
    description: '1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix.'
    bit_offset: 26
    bit_size: 1
fieldset/APB_SARADC_CTRL2:
  fields:
  - name: SARADC_MEAS_NUM_LIMIT
    bit_offset: 0
    bit_size: 1
  - name: SARADC_MAX_MEAS_NUM
    description: max conversion number.
    bit_offset: 1
    bit_size: 8
  - name: SARADC_SAR1_INV
    description: '1: data to DIG ADC1 CTRL is inverted otherwise not.'
    bit_offset: 9
    bit_size: 1
  - name: SARADC_SAR2_INV
    description: '1: data to DIG ADC2 CTRL is inverted otherwise not.'
    bit_offset: 10
    bit_size: 1
fieldset/APB_SARADC_FSM:
  fields:
  - name: SARADC_RSTB_WAIT
    bit_offset: 0
    bit_size: 8
  - name: SARADC_STANDBY_WAIT
    bit_offset: 8
    bit_size: 8
  - name: SARADC_START_WAIT
    bit_offset: 16
    bit_size: 8
  - name: SARADC_SAMPLE_CYCLE
    description: sample cycles.
    bit_offset: 24
    bit_size: 8
fieldset/APB_SARADC_SAR1_PATT_TAB:
  fields:
  - name: SARADC_SAR1_PATT_TAB1
    description: item 0 ~ 3 for pattern table 1 (each item one byte).
    bit_offset: 0
    bit_size: 32
fieldset/APB_SARADC_SAR2_PATT_TAB:
  fields:
  - name: SARADC_SAR2_PATT_TAB1
    description: item 0 ~ 3 for pattern table 2 (each item one byte).
    bit_offset: 0
    bit_size: 32
fieldset/APLL_TICK_CONF:
  fields:
  - name: APLL_TICK_NUM
    bit_offset: 0
    bit_size: 8
fieldset/CK8M_TICK_CONF:
  fields:
  - name: CK8M_TICK_NUM
    bit_offset: 0
    bit_size: 8
fieldset/DATE:
  fields:
  - name: DATE
    bit_offset: 0
    bit_size: 32
fieldset/PLL_TICK_CONF:
  fields:
  - name: PLL_TICK_NUM
    bit_offset: 0
    bit_size: 8
fieldset/SYSCLK_CONF:
  fields:
  - name: PRE_DIV_CNT
    bit_offset: 0
    bit_size: 10
  - name: CLK_320M_EN
    bit_offset: 10
    bit_size: 1
  - name: CLK_EN
    bit_offset: 11
    bit_size: 1
  - name: RST_TICK_CNT
    bit_offset: 12
    bit_size: 1
  - name: QUICK_CLK_CHNG
    bit_offset: 13
    bit_size: 1
fieldset/XTAL_TICK_CONF:
  fields:
  - name: XTAL_TICK_NUM
    bit_offset: 0
    bit_size: 8