block/PRCI:
  description: Power Reset Clock Interrupts.
  items:
  - name: hfrosccfg
    description: Clock Configuration Register.
    byte_offset: 0
    fieldset: hfrosccfg
  - name: hfxosccfg
    description: Clock Configuration Register.
    byte_offset: 4
    fieldset: hfxosccfg
  - name: pllcfg
    description: PLL Configuration Register.
    byte_offset: 8
    fieldset: pllcfg
  - name: plloutdiv
    description: PLL Divider Register.
    byte_offset: 12
    fieldset: plloutdiv
  - name: coreclkcfg
    description: Clock Configuration Register.
    byte_offset: 16
fieldset/hfrosccfg:
  description: Clock Configuration Register.
  fields:
  - name: div
    bit_offset: 0
    bit_size: 6
  - name: trim
    bit_offset: 16
    bit_size: 5
  - name: enable
    bit_offset: 30
    bit_size: 1
  - name: ready
    bit_offset: 31
    bit_size: 1
fieldset/hfxosccfg:
  description: Clock Configuration Register.
  fields:
  - name: enable
    bit_offset: 30
    bit_size: 1
  - name: ready
    bit_offset: 31
    bit_size: 1
fieldset/pllcfg:
  description: PLL Configuration Register.
  fields:
  - name: pllr
    bit_offset: 0
    bit_size: 3
    enum: pllr
  - name: pllf
    bit_offset: 4
    bit_size: 6
  - name: pllq
    bit_offset: 10
    bit_size: 2
    enum: pllq
  - name: sel
    bit_offset: 16
    bit_size: 1
  - name: refsel
    bit_offset: 17
    bit_size: 1
  - name: bypass
    bit_offset: 18
    bit_size: 1
  - name: lock
    bit_offset: 31
    bit_size: 1
fieldset/plloutdiv:
  description: PLL Divider Register.
  fields:
  - name: div
    bit_offset: 0
    bit_size: 6
  - name: divby1
    bit_offset: 8
    bit_size: 1
enum/pllq:
  bit_size: 2
  variants:
  - name: Q2
    value: 1
  - name: Q4
    value: 2
  - name: Q8
    value: 3
enum/pllr:
  bit_size: 3
  variants:
  - name: R1
    value: 0
  - name: R2
    value: 1
  - name: R3
    value: 2
  - name: R4
    value: 3