block/IPCC:
  description: IPCC.
  items:
  - name: C1CR
    description: Control register CPU1.
    byte_offset: 0
    fieldset: C1CR
  - name: C1MR
    description: Mask register CPU1.
    byte_offset: 4
    fieldset: C1MR
  - name: C1SCR
    description: Status Set or Clear register CPU1.
    byte_offset: 8
    access: Write
    fieldset: C1SCR
  - name: C1TOC2SR
    description: CPU1 to CPU2 status register.
    byte_offset: 12
    access: Read
    fieldset: C1TOC2SR
  - name: C2CR
    description: Control register CPU2.
    byte_offset: 16
    fieldset: C2CR
  - name: C2MR
    description: Mask register CPU2.
    byte_offset: 20
    fieldset: C2MR
  - name: C2SCR
    description: Status Set or Clear register CPU2.
    byte_offset: 24
    access: Write
    fieldset: C2SCR
  - name: C2TOC1SR
    description: CPU2 to CPU1 status register.
    byte_offset: 28
    access: Read
    fieldset: C2TOC1SR
  - name: HWCFGR
    description: IPCC Hardware configuration register.
    byte_offset: 1008
    access: Read
    fieldset: HWCFGR
  - name: VERR
    description: IPCC version register.
    byte_offset: 1012
    access: Read
    fieldset: VERR
  - name: IPIDR
    description: IPCC indentification register.
    byte_offset: 1016
    access: Read
    fieldset: IPIDR
  - name: SIDR
    description: IPCC size indentification register.
    byte_offset: 1020
    access: Read
    fieldset: SIDR
fieldset/C1CR:
  description: Control register CPU1.
  fields:
  - name: RXOIE
    description: processor 1 Receive channel occupied interrupt enable.
    bit_offset: 0
    bit_size: 1
  - name: TXFIE
    description: processor 1 Transmit channel free interrupt enable.
    bit_offset: 16
    bit_size: 1
fieldset/C1MR:
  description: Mask register CPU1.
  fields:
  - name: CH1OM
    description: processor 1 Receive channel 1 occupied interrupt enable.
    bit_offset: 0
    bit_size: 1
  - name: CH2OM
    description: processor 1 Receive channel 2 occupied interrupt enable.
    bit_offset: 1
    bit_size: 1
  - name: CH3OM
    description: processor 1 Receive channel 3 occupied interrupt enable.
    bit_offset: 2
    bit_size: 1
  - name: CH4OM
    description: processor 1 Receive channel 4 occupied interrupt enable.
    bit_offset: 3
    bit_size: 1
  - name: CH5OM
    description: processor 1 Receive channel 5 occupied interrupt enable.
    bit_offset: 4
    bit_size: 1
  - name: CH6OM
    description: processor 1 Receive channel 6 occupied interrupt enable.
    bit_offset: 5
    bit_size: 1
  - name: CH1FM
    description: processor 1 Transmit channel 1 free interrupt mask.
    bit_offset: 16
    bit_size: 1
  - name: CH2FM
    description: processor 1 Transmit channel 2 free interrupt mask.
    bit_offset: 17
    bit_size: 1
  - name: CH3FM
    description: processor 1 Transmit channel 3 free interrupt mask.
    bit_offset: 18
    bit_size: 1
  - name: CH4FM
    description: processor 1 Transmit channel 4 free interrupt mask.
    bit_offset: 19
    bit_size: 1
  - name: CH5FM
    description: processor 1 Transmit channel 5 free interrupt mask.
    bit_offset: 20
    bit_size: 1
  - name: CH6FM
    description: processor 1 Transmit channel 6 free interrupt mask.
    bit_offset: 21
    bit_size: 1
fieldset/C1SCR:
  description: Status Set or Clear register CPU1.
  fields:
  - name: CH1C
    description: processor 1 Receive channel 1 status clear.
    bit_offset: 0
    bit_size: 1
  - name: CH2C
    description: processor 1 Receive channel 2 status clear.
    bit_offset: 1
    bit_size: 1
  - name: CH3C
    description: processor 1 Receive channel 3 status clear.
    bit_offset: 2
    bit_size: 1
  - name: CH4C
    description: processor 1 Receive channel 4 status clear.
    bit_offset: 3
    bit_size: 1
  - name: CH5C
    description: processor 1 Receive channel 5 status clear.
    bit_offset: 4
    bit_size: 1
  - name: CH6C
    description: processor 1 Receive channel 6 status clear.
    bit_offset: 5
    bit_size: 1
  - name: CH1S
    description: processor 1 Transmit channel 1 status set.
    bit_offset: 16
    bit_size: 1
  - name: CH2S
    description: processor 1 Transmit channel 2 status set.
    bit_offset: 17
    bit_size: 1
  - name: CH3S
    description: processor 1 Transmit channel 3 status set.
    bit_offset: 18
    bit_size: 1
  - name: CH4S
    description: processor 1 Transmit channel 4 status set.
    bit_offset: 19
    bit_size: 1
  - name: CH5S
    description: processor 1 Transmit channel 5 status set.
    bit_offset: 20
    bit_size: 1
  - name: CH6S
    description: processor 1 Transmit channel 6 status set.
    bit_offset: 21
    bit_size: 1
fieldset/C1TOC2SR:
  description: CPU1 to CPU2 status register.
  fields:
  - name: CH1F
    description: processor 1 transmit to process 2 Receive channel 1 status flag.
    bit_offset: 0
    bit_size: 1
  - name: CH2F
    description: processor 1 transmit to process 2 Receive channel 2 status flag.
    bit_offset: 1
    bit_size: 1
  - name: CH3F
    description: processor 1 transmit to process 2 Receive channel 3 status flag.
    bit_offset: 2
    bit_size: 1
  - name: CH4F
    description: processor 1 transmit to process 2 Receive channel 4 status flag.
    bit_offset: 3
    bit_size: 1
  - name: CH5F
    description: processor 1 transmit to process 2 Receive channel 5 status flag.
    bit_offset: 4
    bit_size: 1
  - name: CH6F
    description: processor 1 transmit to process 2 Receive channel 6 status flag.
    bit_offset: 5
    bit_size: 1
fieldset/C2CR:
  description: Control register CPU2.
  fields:
  - name: RXOIE
    description: processor 2 Receive channel occupied interrupt enable.
    bit_offset: 0
    bit_size: 1
  - name: TXFIE
    description: processor 2 Transmit channel free interrupt enable.
    bit_offset: 16
    bit_size: 1
fieldset/C2MR:
  description: Mask register CPU2.
  fields:
  - name: CH1OM
    description: processor 2 Receive channel 1 occupied interrupt enable.
    bit_offset: 0
    bit_size: 1
  - name: CH2OM
    description: processor 2 Receive channel 2 occupied interrupt enable.
    bit_offset: 1
    bit_size: 1
  - name: CH3OM
    description: processor 2 Receive channel 3 occupied interrupt enable.
    bit_offset: 2
    bit_size: 1
  - name: CH4OM
    description: processor 2 Receive channel 4 occupied interrupt enable.
    bit_offset: 3
    bit_size: 1
  - name: CH5OM
    description: processor 2 Receive channel 5 occupied interrupt enable.
    bit_offset: 4
    bit_size: 1
  - name: CH6OM
    description: processor 2 Receive channel 6 occupied interrupt enable.
    bit_offset: 5
    bit_size: 1
  - name: CH1FM
    description: processor 2 Transmit channel 1 free interrupt mask.
    bit_offset: 16
    bit_size: 1
  - name: CH2FM
    description: processor 2 Transmit channel 2 free interrupt mask.
    bit_offset: 17
    bit_size: 1
  - name: CH3FM
    description: processor 2 Transmit channel 3 free interrupt mask.
    bit_offset: 18
    bit_size: 1
  - name: CH4FM
    description: processor 2 Transmit channel 4 free interrupt mask.
    bit_offset: 19
    bit_size: 1
  - name: CH5FM
    description: processor 2 Transmit channel 5 free interrupt mask.
    bit_offset: 20
    bit_size: 1
  - name: CH6FM
    description: processor 2 Transmit channel 6 free interrupt mask.
    bit_offset: 21
    bit_size: 1
fieldset/C2SCR:
  description: Status Set or Clear register CPU2.
  fields:
  - name: CH1C
    description: processor 2 Receive channel 1 status clear.
    bit_offset: 0
    bit_size: 1
  - name: CH2C
    description: processor 2 Receive channel 2 status clear.
    bit_offset: 1
    bit_size: 1
  - name: CH3C
    description: processor 2 Receive channel 3 status clear.
    bit_offset: 2
    bit_size: 1
  - name: CH4C
    description: processor 2 Receive channel 4 status clear.
    bit_offset: 3
    bit_size: 1
  - name: CH5C
    description: processor 2 Receive channel 5 status clear.
    bit_offset: 4
    bit_size: 1
  - name: CH6C
    description: processor 2 Receive channel 6 status clear.
    bit_offset: 5
    bit_size: 1
  - name: CH1S
    description: processor 2 Transmit channel 1 status set.
    bit_offset: 16
    bit_size: 1
  - name: CH2S
    description: processor 2 Transmit channel 2 status set.
    bit_offset: 17
    bit_size: 1
  - name: CH3S
    description: processor 2 Transmit channel 3 status set.
    bit_offset: 18
    bit_size: 1
  - name: CH4S
    description: processor 2 Transmit channel 4 status set.
    bit_offset: 19
    bit_size: 1
  - name: CH5S
    description: processor 2 Transmit channel 5 status set.
    bit_offset: 20
    bit_size: 1
  - name: CH6S
    description: processor 2 Transmit channel 6 status set.
    bit_offset: 21
    bit_size: 1
fieldset/C2TOC1SR:
  description: CPU2 to CPU1 status register.
  fields:
  - name: CH1F
    description: processor 2 transmit to process 1 Receive channel 1 status flag.
    bit_offset: 0
    bit_size: 1
  - name: CH2F
    description: processor 2 transmit to process 1 Receive channel 2 status flag.
    bit_offset: 1
    bit_size: 1
  - name: CH3F
    description: processor 2 transmit to process 1 Receive channel 3 status flag.
    bit_offset: 2
    bit_size: 1
  - name: CH4F
    description: processor 2 transmit to process 1 Receive channel 4 status flag.
    bit_offset: 3
    bit_size: 1
  - name: CH5F
    description: processor 2 transmit to process 1 Receive channel 5 status flag.
    bit_offset: 4
    bit_size: 1
  - name: CH6F
    description: processor 2 transmit to process 1 Receive channel 6 status flag.
    bit_offset: 5
    bit_size: 1
fieldset/HWCFGR:
  description: IPCC Hardware configuration register.
  fields:
  - name: CHANNELS
    description: Number of channels per CPU supported by the IP, range 1 to 16.
    bit_offset: 0
    bit_size: 8
fieldset/IPIDR:
  description: IPCC indentification register.
  fields:
  - name: IPID
    description: Identification Code.
    bit_offset: 0
    bit_size: 32
fieldset/SIDR:
  description: IPCC size indentification register.
  fields:
  - name: SID
    description: Size Identification Code.
    bit_offset: 0
    bit_size: 32
fieldset/VERR:
  description: IPCC version register.
  fields:
  - name: MINREV
    description: Minor Revision.
    bit_offset: 0
    bit_size: 4
  - name: MAJREV
    description: Major Revision.
    bit_offset: 4
    bit_size: 4