block/Flash:
  description: Flash.
  items:
  - name: ACR
    description: Access control register.
    byte_offset: 0
    fieldset: ACR
  - name: KEYR
    description: Flash key register.
    byte_offset: 8
    access: Write
    fieldset: KEYR
  - name: OPTKEYR
    description: Option byte key register.
    byte_offset: 12
    access: Write
    fieldset: OPTKEYR
  - name: SR
    description: Status register.
    byte_offset: 16
    fieldset: SR
  - name: CR
    description: Flash control register.
    byte_offset: 20
    fieldset: CR
  - name: ECCR
    description: Flash ECC register.
    byte_offset: 24
    fieldset: ECCR
  - name: OPTR
    description: Flash option register.
    byte_offset: 32
    fieldset: OPTR
  - name: PCROP1ASR
    description: Flash Bank 1 PCROP Start address zone A register.
    byte_offset: 36
    fieldset: PCROP1ASR
  - name: PCROP1AER
    description: Flash Bank 1 PCROP End address zone A register.
    byte_offset: 40
    fieldset: PCROP1AER
  - name: WRP1AR
    description: Flash Bank 1 WRP area A address register.
    byte_offset: 44
    fieldset: WRP1AR
  - name: WRP1BR
    description: Flash Bank 1 WRP area B address register.
    byte_offset: 48
    fieldset: WRP1BR
  - name: PCROP1BSR
    description: Flash Bank 1 PCROP Start address area B register.
    byte_offset: 52
    fieldset: PCROP1BSR
  - name: PCROP1BER
    description: Flash Bank 1 PCROP End address area B register.
    byte_offset: 56
    fieldset: PCROP1BER
  - name: IPCCBR
    description: IPCC mailbox data buffer address register.
    byte_offset: 60
    fieldset: IPCCBR
  - name: C2ACR
    description: CPU2 cortex M0 access control register.
    byte_offset: 92
    fieldset: C2ACR
  - name: C2SR
    description: CPU2 cortex M0 status register.
    byte_offset: 96
    fieldset: C2SR
  - name: C2CR
    description: CPU2 cortex M0 control register.
    byte_offset: 100
    fieldset: C2CR
  - name: SFR
    description: Secure flash start address register.
    byte_offset: 128
    fieldset: SFR
  - name: SRRVR
    description: Secure SRAM2 start address and cortex M0 reset vector register.
    byte_offset: 132
    fieldset: SRRVR
fieldset/ACR:
  description: Access control register.
  fields:
  - name: LATENCY
    description: Latency.
    bit_offset: 0
    bit_size: 3
  - name: PRFTEN
    description: Prefetch enable.
    bit_offset: 8
    bit_size: 1
  - name: ICEN
    description: Instruction cache enable.
    bit_offset: 9
    bit_size: 1
  - name: DCEN
    description: Data cache enable.
    bit_offset: 10
    bit_size: 1
  - name: ICRST
    description: Instruction cache reset.
    bit_offset: 11
    bit_size: 1
  - name: DCRST
    description: Data cache reset.
    bit_offset: 12
    bit_size: 1
  - name: PES
    description: CPU1 CortexM4 program erase suspend request.
    bit_offset: 15
    bit_size: 1
  - name: EMPTY
    description: Flash User area empty.
    bit_offset: 16
    bit_size: 1
fieldset/C2ACR:
  description: CPU2 cortex M0 access control register.
  fields:
  - name: PRFTEN
    description: CPU2 cortex M0 prefetch enable.
    bit_offset: 8
    bit_size: 1
  - name: ICEN
    description: CPU2 cortex M0 instruction cache enable.
    bit_offset: 9
    bit_size: 1
  - name: ICRST
    description: CPU2 cortex M0 instruction cache reset.
    bit_offset: 11
    bit_size: 1
  - name: PES
    description: CPU2 cortex M0 program erase suspend request.
    bit_offset: 15
    bit_size: 1
fieldset/C2CR:
  description: CPU2 cortex M0 control register.
  fields:
  - name: PG
    description: Programming.
    bit_offset: 0
    bit_size: 1
  - name: PER
    description: Page erase.
    bit_offset: 1
    bit_size: 1
  - name: MER
    description: Masse erase.
    bit_offset: 2
    bit_size: 1
  - name: PNB
    description: Page Number selection.
    bit_offset: 3
    bit_size: 8
  - name: STRT
    description: Start.
    bit_offset: 16
    bit_size: 1
  - name: FSTPG
    description: Fast programming.
    bit_offset: 18
    bit_size: 1
  - name: EOPIE
    description: End of operation interrupt enable.
    bit_offset: 24
    bit_size: 1
  - name: ERRIE
    description: Error interrupt enable.
    bit_offset: 25
    bit_size: 1
  - name: RDERRIE
    description: PCROP read error interrupt enable.
    bit_offset: 26
    bit_size: 1
fieldset/C2SR:
  description: CPU2 cortex M0 status register.
  fields:
  - name: EOP
    description: End of operation.
    bit_offset: 0
    bit_size: 1
  - name: OPERR
    description: Operation error.
    bit_offset: 1
    bit_size: 1
  - name: PROGERR
    description: Programming error.
    bit_offset: 3
    bit_size: 1
  - name: WRPERR
    description: write protection error.
    bit_offset: 4
    bit_size: 1
  - name: PGAERR
    description: Programming alignment error.
    bit_offset: 5
    bit_size: 1
  - name: SIZERR
    description: Size error.
    bit_offset: 6
    bit_size: 1
  - name: PGSERR
    description: Programming sequence error.
    bit_offset: 7
    bit_size: 1
  - name: MISSERR
    description: Fast programming data miss error.
    bit_offset: 8
    bit_size: 1
  - name: FASTERR
    description: Fast programming error.
    bit_offset: 9
    bit_size: 1
  - name: RDERR
    description: PCROP read error.
    bit_offset: 14
    bit_size: 1
  - name: BSY
    description: Busy.
    bit_offset: 16
    bit_size: 1
  - name: CFGBSY
    description: Programming or erase configuration busy.
    bit_offset: 18
    bit_size: 1
  - name: PESD
    description: Programming or erase operation suspended.
    bit_offset: 19
    bit_size: 1
fieldset/CR:
  description: Flash control register.
  fields:
  - name: PG
    description: Programming.
    bit_offset: 0
    bit_size: 1
  - name: PER
    description: Page erase.
    bit_offset: 1
    bit_size: 1
  - name: MER
    description: This bit triggers the mass erase (all user pages) when set.
    bit_offset: 2
    bit_size: 1
  - name: PNB
    description: Page number selection.
    bit_offset: 3
    bit_size: 8
  - name: STRT
    description: Start.
    bit_offset: 16
    bit_size: 1
  - name: OPTSTRT
    description: Options modification start.
    bit_offset: 17
    bit_size: 1
  - name: FSTPG
    description: Fast programming.
    bit_offset: 18
    bit_size: 1
  - name: EOPIE
    description: End of operation interrupt enable.
    bit_offset: 24
    bit_size: 1
  - name: ERRIE
    description: Error interrupt enable.
    bit_offset: 25
    bit_size: 1
  - name: RDERRIE
    description: PCROP read error interrupt enable.
    bit_offset: 26
    bit_size: 1
  - name: OBL_LAUNCH
    description: Force the option byte loading.
    bit_offset: 27
    bit_size: 1
  - name: OPTLOCK
    description: Options Lock.
    bit_offset: 30
    bit_size: 1
  - name: LOCK
    description: FLASH_CR Lock.
    bit_offset: 31
    bit_size: 1
fieldset/ECCR:
  description: Flash ECC register.
  fields:
  - name: ADDR_ECC
    description: ECC fail address.
    bit_offset: 0
    bit_size: 17
  - name: SYSF_ECC
    description: System Flash ECC fail.
    bit_offset: 20
    bit_size: 1
  - name: ECCCIE
    description: ECC correction interrupt enable.
    bit_offset: 24
    bit_size: 1
  - name: CPUID
    description: CPU identification.
    bit_offset: 26
    bit_size: 3
  - name: ECCC
    description: ECC correction.
    bit_offset: 30
    bit_size: 1
  - name: ECCD
    description: ECC detection.
    bit_offset: 31
    bit_size: 1
fieldset/IPCCBR:
  description: IPCC mailbox data buffer address register.
  fields:
  - name: IPCCDBA
    description: PCC mailbox data buffer base address.
    bit_offset: 0
    bit_size: 14
fieldset/KEYR:
  description: Flash key register.
  fields:
  - name: KEYR
    description: KEYR.
    bit_offset: 0
    bit_size: 32
fieldset/OPTKEYR:
  description: Option byte key register.
  fields:
  - name: OPTKEYR
    description: Option byte key.
    bit_offset: 0
    bit_size: 32
fieldset/OPTR:
  description: Flash option register.
  fields:
  - name: RDP
    description: Read protection level.
    bit_offset: 0
    bit_size: 8
  - name: ESE
    description: Security enabled.
    bit_offset: 8
    bit_size: 1
  - name: BOR_LEV
    description: BOR reset Level.
    bit_offset: 9
    bit_size: 3
  - name: nRST_STOP
    description: nRST_STOP.
    bit_offset: 12
    bit_size: 1
  - name: nRST_STDBY
    description: nRST_STDBY.
    bit_offset: 13
    bit_size: 1
  - name: nRST_SHDW
    description: nRST_SHDW.
    bit_offset: 14
    bit_size: 1
  - name: IDWG_SW
    description: Independent watchdog selection.
    bit_offset: 16
    bit_size: 1
  - name: IWDG_STOP
    description: Independent watchdog counter freeze in Stop mode.
    bit_offset: 17
    bit_size: 1
  - name: IWDG_STDBY
    description: Independent watchdog counter freeze in Standby mode.
    bit_offset: 18
    bit_size: 1
  - name: WWDG_SW
    description: Window watchdog selection.
    bit_offset: 19
    bit_size: 1
  - name: nBOOT1
    description: Boot configuration.
    bit_offset: 23
    bit_size: 1
  - name: SRAM2_PE
    description: SRAM2 parity check enable.
    bit_offset: 24
    bit_size: 1
  - name: SRAM2_RST
    description: SRAM2 Erase when system reset.
    bit_offset: 25
    bit_size: 1
  - name: nSWBOOT0
    description: Software Boot0.
    bit_offset: 26
    bit_size: 1
  - name: nBOOT0
    description: nBoot0 option bit.
    bit_offset: 27
    bit_size: 1
  - name: AGC_TRIM
    description: Radio Automatic Gain Control Trimming.
    bit_offset: 29
    bit_size: 3
fieldset/PCROP1AER:
  description: Flash Bank 1 PCROP End address zone A register.
  fields:
  - name: PCROP1A_END
    description: Bank 1 PCROP area end offset.
    bit_offset: 0
    bit_size: 9
  - name: PCROP_RDP
    description: PCROP area preserved when RDP level decreased.
    bit_offset: 31
    bit_size: 1
fieldset/PCROP1ASR:
  description: Flash Bank 1 PCROP Start address zone A register.
  fields:
  - name: PCROP1A_STRT
    description: Bank 1 PCROPQ area start offset.
    bit_offset: 0
    bit_size: 9
fieldset/PCROP1BER:
  description: Flash Bank 1 PCROP End address area B register.
  fields:
  - name: PCROP1B_END
    description: Bank 1 PCROP area end area B offset.
    bit_offset: 0
    bit_size: 9
fieldset/PCROP1BSR:
  description: Flash Bank 1 PCROP Start address area B register.
  fields:
  - name: PCROP1B_STRT
    description: Bank 1 PCROP area B start offset.
    bit_offset: 0
    bit_size: 9
fieldset/SFR:
  description: Secure flash start address register.
  fields:
  - name: SFSA
    description: Secure flash start address.
    bit_offset: 0
    bit_size: 8
  - name: FSD
    description: Flash security disable.
    bit_offset: 8
    bit_size: 1
  - name: DDS
    description: Disable Cortex M0 debug access.
    bit_offset: 12
    bit_size: 1
fieldset/SR:
  description: Status register.
  fields:
  - name: EOP
    description: End of operation.
    bit_offset: 0
    bit_size: 1
  - name: OPERR
    description: Operation error.
    bit_offset: 1
    bit_size: 1
  - name: PROGERR
    description: Programming error.
    bit_offset: 3
    bit_size: 1
  - name: WRPERR
    description: Write protected error.
    bit_offset: 4
    bit_size: 1
  - name: PGAERR
    description: Programming alignment error.
    bit_offset: 5
    bit_size: 1
  - name: SIZERR
    description: Size error.
    bit_offset: 6
    bit_size: 1
  - name: PGSERR
    description: Programming sequence error.
    bit_offset: 7
    bit_size: 1
  - name: MISERR
    description: Fast programming data miss error.
    bit_offset: 8
    bit_size: 1
  - name: FASTERR
    description: Fast programming error.
    bit_offset: 9
    bit_size: 1
  - name: OPTNV
    description: User Option OPTVAL indication.
    bit_offset: 13
    bit_size: 1
  - name: RDERR
    description: PCROP read error.
    bit_offset: 14
    bit_size: 1
  - name: OPTVERR
    description: Option validity error.
    bit_offset: 15
    bit_size: 1
  - name: BSY
    description: Busy.
    bit_offset: 16
    bit_size: 1
  - name: CFGBSY
    description: Programming or erase configuration busy.
    bit_offset: 18
    bit_size: 1
  - name: PESD
    description: Programming or erase operation suspended.
    bit_offset: 19
    bit_size: 1
fieldset/SRRVR:
  description: Secure SRAM2 start address and cortex M0 reset vector register.
  fields:
  - name: SBRV
    description: cortex M0 access control register.
    bit_offset: 0
    bit_size: 18
  - name: SBRSA
    description: Secure backup SRAM2a start address.
    bit_offset: 18
    bit_size: 5
  - name: BRSD
    description: backup SRAM2a security disable.
    bit_offset: 23
    bit_size: 1
  - name: SNBRSA
    description: Secure non backup SRAM2a start address.
    bit_offset: 25
    bit_size: 5
  - name: NBRSD
    description: non-backup SRAM2b security disable.
    bit_offset: 30
    bit_size: 1
  - name: C2OPT
    description: CPU2 cortex M0 boot reset vector memory selection.
    bit_offset: 31
    bit_size: 1
fieldset/WRP1AR:
  description: Flash Bank 1 WRP area A address register.
  fields:
  - name: WRP1A_STRT
    description: Bank 1 WRP first area A start offset.
    bit_offset: 0
    bit_size: 8
  - name: WRP1A_END
    description: Bank 1 WRP first area A end offset.
    bit_offset: 16
    bit_size: 8
fieldset/WRP1BR:
  description: Flash Bank 1 WRP area B address register.
  fields:
  - name: WRP1B_END
    description: Bank 1 WRP second area B start offset.
    bit_offset: 0
    bit_size: 8
  - name: WRP1B_STRT
    description: Bank 1 WRP second area B end offset.
    bit_offset: 16
    bit_size: 8