block/TIM3:
  description: TIM3.
  items:
  - name: CR1
    description: TIM3 control register 1.
    byte_offset: 0
    bit_size: 16
    fieldset: CR1
  - name: CR2
    description: TIM3 control register 2.
    byte_offset: 4
    fieldset: CR2
  - name: SMCR
    description: TIM3 slave mode control register.
    byte_offset: 8
    fieldset: SMCR
  - name: DIER
    description: TIM3 DMA/interrupt enable register.
    byte_offset: 12
    bit_size: 16
    fieldset: DIER
  - name: SR
    description: TIM3 status register.
    byte_offset: 16
    fieldset: SR
  - name: EGR
    description: TIM3 event generation register.
    byte_offset: 20
    access: Write
    bit_size: 16
    fieldset: EGR
  - name: CCMR1ALTERNATE3
    description: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:.
    byte_offset: 24
    fieldset: CCMR1ALTERNATE3
  - name: CCMR2ALTERNATE19
    description: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:.
    byte_offset: 28
    fieldset: CCMR2ALTERNATE19
  - name: CCER
    description: TIM3 capture/compare enable register.
    byte_offset: 32
    fieldset: CCER
  - name: CNT
    description: TIM3 counter.
    byte_offset: 36
    fieldset: CNT
  - name: PSC
    description: TIM3 prescaler.
    byte_offset: 40
    bit_size: 16
    fieldset: PSC
  - name: ARR
    description: TIM3 auto-reload register.
    byte_offset: 44
    bit_size: 16
    fieldset: ARR
  - name: RCR
    description: TIM3 repetition counter register.
    byte_offset: 48
    bit_size: 16
    fieldset: RCR
  - name: CCR1
    description: TIM3 capture/compare register 1.
    byte_offset: 52
    bit_size: 16
    fieldset: CCR1
  - name: CCR2
    description: TIM3 capture/compare register 2.
    byte_offset: 56
    bit_size: 16
    fieldset: CCR2
  - name: CCR3
    description: TIM3 capture/compare register 3.
    byte_offset: 60
    bit_size: 16
    fieldset: CCR3
  - name: CCR4
    description: TIM3 capture/compare register 4.
    byte_offset: 64
    bit_size: 16
    fieldset: CCR4
  - name: BDTR
    description: As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
    byte_offset: 68
    fieldset: BDTR
  - name: DCR
    description: TIM3 DMA control register.
    byte_offset: 72
    bit_size: 16
    fieldset: DCR
  - name: DMAR
    description: TIM3 DMA address for full transfer.
    byte_offset: 76
    fieldset: DMAR
  - name: CCMR3
    description: The channels 5 and 6 can only be configured in output. Output compare mode:.
    byte_offset: 84
    fieldset: CCMR3
  - name: CCR5
    description: TIM3 capture/compare register 5.
    byte_offset: 88
    fieldset: CCR5
  - name: CCR6
    description: TIM3 capture/compare register 6.
    byte_offset: 92
    bit_size: 16
    fieldset: CCR6
fieldset/ARR:
  description: TIM3 auto-reload register.
  bit_size: 16
  fields:
  - name: ARR
    description: ARR.
    bit_offset: 0
    bit_size: 16
fieldset/BDTR:
  description: As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
  fields:
  - name: DTG
    description: DTG.
    bit_offset: 0
    bit_size: 8
  - name: LOCK
    description: LOCK.
    bit_offset: 8
    bit_size: 2
  - name: OSSI
    description: OSSI.
    bit_offset: 10
    bit_size: 1
  - name: OSSR
    description: OSSR.
    bit_offset: 11
    bit_size: 1
  - name: BKE
    description: BKE.
    bit_offset: 12
    bit_size: 1
  - name: BKP
    description: BKP.
    bit_offset: 13
    bit_size: 1
  - name: AOE
    description: AOE.
    bit_offset: 14
    bit_size: 1
  - name: MOE
    description: MOE.
    bit_offset: 15
    bit_size: 1
  - name: BKF
    description: BKF.
    bit_offset: 16
    bit_size: 4
  - name: BK2F
    description: BK2F.
    bit_offset: 20
    bit_size: 4
  - name: BK2E
    description: BK2E.
    bit_offset: 24
    bit_size: 1
  - name: BK2P
    description: BK2P.
    bit_offset: 25
    bit_size: 1
  - name: BKDSRM
    description: BKDSRM.
    bit_offset: 26
    bit_size: 1
  - name: BK2DSRM
    description: BK2DSRM.
    bit_offset: 27
    bit_size: 1
  - name: BKBID
    description: BKBID.
    bit_offset: 28
    bit_size: 1
  - name: BK2BID
    description: BK2BID.
    bit_offset: 29
    bit_size: 1
fieldset/CCER:
  description: TIM3 capture/compare enable register.
  fields:
  - name: CC1E
    description: CC1E.
    bit_offset: 0
    bit_size: 1
  - name: CC1P
    description: CC1P.
    bit_offset: 1
    bit_size: 1
  - name: CC1NE
    description: CC1NE.
    bit_offset: 2
    bit_size: 1
  - name: CC1NP
    description: CC1NP.
    bit_offset: 3
    bit_size: 1
  - name: CC2E
    description: CC2E.
    bit_offset: 4
    bit_size: 1
  - name: CC2P
    description: CC2P.
    bit_offset: 5
    bit_size: 1
  - name: CC2NE
    description: CC2NE.
    bit_offset: 6
    bit_size: 1
  - name: CC2NP
    description: CC2NP.
    bit_offset: 7
    bit_size: 1
  - name: CC3E
    description: CC3E.
    bit_offset: 8
    bit_size: 1
  - name: CC3P
    description: CC3P.
    bit_offset: 9
    bit_size: 1
  - name: CC3NE
    description: CC3NE.
    bit_offset: 10
    bit_size: 1
  - name: CC3NP
    description: CC3NP.
    bit_offset: 11
    bit_size: 1
  - name: CC4E
    description: CC4E.
    bit_offset: 12
    bit_size: 1
  - name: CC4P
    description: CC4P.
    bit_offset: 13
    bit_size: 1
  - name: CC4NP
    description: CC4NP.
    bit_offset: 15
    bit_size: 1
  - name: CC5E
    description: CC5E.
    bit_offset: 16
    bit_size: 1
  - name: CC5P
    description: CC5P.
    bit_offset: 17
    bit_size: 1
  - name: CC6E
    description: CC6E.
    bit_offset: 20
    bit_size: 1
  - name: CC6P
    description: CC6P.
    bit_offset: 21
    bit_size: 1
fieldset/CCMR1ALTERNATE3:
  description: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:.
  fields:
  - name: CC1S
    description: CC1S.
    bit_offset: 0
    bit_size: 2
  - name: IC1PSC
    description: IC1PSC.
    bit_offset: 2
    bit_size: 2
  - name: IC1F
    description: IC1F.
    bit_offset: 4
    bit_size: 4
  - name: CC2S
    description: CC2S.
    bit_offset: 8
    bit_size: 2
  - name: IC2PSC
    description: IC2PSC.
    bit_offset: 10
    bit_size: 2
  - name: IC2F
    description: IC2F.
    bit_offset: 12
    bit_size: 4
fieldset/CCMR2ALTERNATE19:
  description: The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:.
  fields:
  - name: CC3S
    description: CC3S.
    bit_offset: 0
    bit_size: 2
  - name: IC3PSC
    description: IC3PSC.
    bit_offset: 2
    bit_size: 2
  - name: IC3F
    description: IC3F.
    bit_offset: 4
    bit_size: 4
  - name: CC4S
    description: CC4S.
    bit_offset: 8
    bit_size: 2
  - name: IC4PSC
    description: IC4PSC.
    bit_offset: 10
    bit_size: 2
  - name: IC4F
    description: IC4F.
    bit_offset: 12
    bit_size: 4
fieldset/CCMR3:
  description: The channels 5 and 6 can only be configured in output. Output compare mode:.
  fields:
  - name: OC5FE
    description: OC5FE.
    bit_offset: 2
    bit_size: 1
  - name: OC5PE
    description: OC5PE.
    bit_offset: 3
    bit_size: 1
  - name: OC5M
    description: OC5M.
    bit_offset: 4
    bit_size: 3
  - name: OC5CE
    description: OC5CE.
    bit_offset: 7
    bit_size: 1
  - name: OC6FE
    description: OC6FE.
    bit_offset: 10
    bit_size: 1
  - name: OC6PE
    description: OC6PE.
    bit_offset: 11
    bit_size: 1
  - name: OC6M
    description: OC6M.
    bit_offset: 12
    bit_size: 3
  - name: OC6CE
    description: OC6CE.
    bit_offset: 15
    bit_size: 1
  - name: OC5M3
    description: OC5M3.
    bit_offset: 16
    bit_size: 1
  - name: OC6M3
    description: OC6M3.
    bit_offset: 24
    bit_size: 1
fieldset/CCR1:
  description: TIM3 capture/compare register 1.
  bit_size: 16
  fields:
  - name: CCR1
    description: CCR1.
    bit_offset: 0
    bit_size: 16
fieldset/CCR2:
  description: TIM3 capture/compare register 2.
  bit_size: 16
  fields:
  - name: CCR2
    description: CCR2.
    bit_offset: 0
    bit_size: 16
fieldset/CCR3:
  description: TIM3 capture/compare register 3.
  bit_size: 16
  fields:
  - name: CCR3
    description: CCR3.
    bit_offset: 0
    bit_size: 16
fieldset/CCR4:
  description: TIM3 capture/compare register 4.
  bit_size: 16
  fields:
  - name: CCR4
    description: CCR4.
    bit_offset: 0
    bit_size: 16
fieldset/CCR5:
  description: TIM3 capture/compare register 5.
  fields:
  - name: CCR5
    description: CCR5.
    bit_offset: 0
    bit_size: 16
  - name: GC5C1
    description: GC5C1.
    bit_offset: 29
    bit_size: 1
  - name: GC5C2
    description: GC5C2.
    bit_offset: 30
    bit_size: 1
  - name: GC5C3
    description: GC5C3.
    bit_offset: 31
    bit_size: 1
fieldset/CCR6:
  description: TIM3 capture/compare register 6.
  bit_size: 16
  fields:
  - name: CCR6
    description: CCR6.
    bit_offset: 0
    bit_size: 16
fieldset/CNT:
  description: TIM3 counter.
  fields:
  - name: CNT
    description: CNT.
    bit_offset: 0
    bit_size: 16
  - name: UIFCPY
    description: UIFCPY.
    bit_offset: 31
    bit_size: 1
fieldset/CR1:
  description: TIM3 control register 1.
  bit_size: 16
  fields:
  - name: CEN
    description: CEN.
    bit_offset: 0
    bit_size: 1
  - name: UDIS
    description: UDIS.
    bit_offset: 1
    bit_size: 1
  - name: URS
    description: URS.
    bit_offset: 2
    bit_size: 1
  - name: OPM
    description: OPM.
    bit_offset: 3
    bit_size: 1
  - name: DIR
    description: DIR.
    bit_offset: 4
    bit_size: 1
  - name: CMS
    description: CMS.
    bit_offset: 5
    bit_size: 2
  - name: ARPE
    description: ARPE.
    bit_offset: 7
    bit_size: 1
  - name: CKD
    description: CKD.
    bit_offset: 8
    bit_size: 2
  - name: UIFREMAP
    description: UIFREMAP.
    bit_offset: 11
    bit_size: 1
fieldset/CR2:
  description: TIM3 control register 2.
  fields:
  - name: CCPC
    description: CCPC.
    bit_offset: 0
    bit_size: 1
  - name: CCUS
    description: CCUS.
    bit_offset: 2
    bit_size: 1
  - name: CCDS
    description: CCDS.
    bit_offset: 3
    bit_size: 1
  - name: MMS
    description: MMS.
    bit_offset: 4
    bit_size: 3
  - name: TI1S
    description: TI1S.
    bit_offset: 7
    bit_size: 1
  - name: OIS1
    description: OIS1.
    bit_offset: 8
    bit_size: 1
  - name: OIS1N
    description: OIS1N.
    bit_offset: 9
    bit_size: 1
  - name: OIS2
    description: OIS2.
    bit_offset: 10
    bit_size: 1
  - name: OIS2N
    description: OIS2N.
    bit_offset: 11
    bit_size: 1
  - name: OIS3
    description: OIS3.
    bit_offset: 12
    bit_size: 1
  - name: OIS3N
    description: OIS3N.
    bit_offset: 13
    bit_size: 1
  - name: OIS4
    description: OIS4.
    bit_offset: 14
    bit_size: 1
  - name: OIS5
    description: OIS5.
    bit_offset: 16
    bit_size: 1
  - name: OIS6
    description: OIS6.
    bit_offset: 18
    bit_size: 1
  - name: MMS2
    description: MMS2.
    bit_offset: 20
    bit_size: 4
fieldset/DCR:
  description: TIM3 DMA control register.
  bit_size: 16
  fields:
  - name: DBA
    description: DBA.
    bit_offset: 0
    bit_size: 5
  - name: DBL
    description: DBL.
    bit_offset: 8
    bit_size: 5
fieldset/DIER:
  description: TIM3 DMA/interrupt enable register.
  bit_size: 16
  fields:
  - name: UIE
    description: UIE.
    bit_offset: 0
    bit_size: 1
  - name: CC1IE
    description: CC1IE.
    bit_offset: 1
    bit_size: 1
  - name: CC2IE
    description: CC2IE.
    bit_offset: 2
    bit_size: 1
  - name: CC3IE
    description: CC3IE.
    bit_offset: 3
    bit_size: 1
  - name: CC4IE
    description: CC4IE.
    bit_offset: 4
    bit_size: 1
  - name: COMIE
    description: COMIE.
    bit_offset: 5
    bit_size: 1
  - name: TIE
    description: TIE.
    bit_offset: 6
    bit_size: 1
  - name: BIE
    description: BIE.
    bit_offset: 7
    bit_size: 1
  - name: UDE
    description: UDE.
    bit_offset: 8
    bit_size: 1
  - name: CC1DE
    description: CC1DE.
    bit_offset: 9
    bit_size: 1
  - name: CC2DE
    description: CC2DE.
    bit_offset: 10
    bit_size: 1
  - name: CC3DE
    description: CC3DE.
    bit_offset: 11
    bit_size: 1
  - name: CC4DE
    description: CC4DE.
    bit_offset: 12
    bit_size: 1
  - name: COMDE
    description: COMDE.
    bit_offset: 13
    bit_size: 1
  - name: TDE
    description: TDE.
    bit_offset: 14
    bit_size: 1
fieldset/DMAR:
  description: TIM3 DMA address for full transfer.
  fields:
  - name: DMAB
    description: DMAB.
    bit_offset: 0
    bit_size: 32
fieldset/EGR:
  description: TIM3 event generation register.
  bit_size: 16
  fields:
  - name: UG
    description: UG.
    bit_offset: 0
    bit_size: 1
  - name: CC1G
    description: CC1G.
    bit_offset: 1
    bit_size: 1
  - name: CC2G
    description: CC2G.
    bit_offset: 2
    bit_size: 1
  - name: CC3G
    description: CC3G.
    bit_offset: 3
    bit_size: 1
  - name: CC4G
    description: CC4G.
    bit_offset: 4
    bit_size: 1
  - name: COMG
    description: COMG.
    bit_offset: 5
    bit_size: 1
  - name: TG
    description: TG.
    bit_offset: 6
    bit_size: 1
  - name: BG
    description: BG.
    bit_offset: 7
    bit_size: 1
  - name: B2G
    description: B2G.
    bit_offset: 8
    bit_size: 1
fieldset/PSC:
  description: TIM3 prescaler.
  bit_size: 16
  fields:
  - name: PSC
    description: PSC.
    bit_offset: 0
    bit_size: 16
fieldset/RCR:
  description: TIM3 repetition counter register.
  bit_size: 16
  fields:
  - name: REP
    description: REP.
    bit_offset: 0
    bit_size: 16
fieldset/SMCR:
  description: TIM3 slave mode control register.
  fields:
  - name: SMS
    description: SMS.
    bit_offset: 0
    bit_size: 3
  - name: TS
    description: TS.
    bit_offset: 4
    bit_size: 3
  - name: MSM
    description: MSM.
    bit_offset: 7
    bit_size: 1
  - name: ETF
    description: ETF.
    bit_offset: 8
    bit_size: 4
  - name: ETPS
    description: ETPS.
    bit_offset: 12
    bit_size: 2
  - name: ECE
    description: ECE.
    bit_offset: 14
    bit_size: 1
  - name: ETP
    description: ETP.
    bit_offset: 15
    bit_size: 1
  - name: SMS3
    description: SMS3.
    bit_offset: 16
    bit_size: 1
  - name: TS3
    description: TS3.
    bit_offset: 20
    bit_size: 1
  - name: TS4
    description: TS4.
    bit_offset: 21
    bit_size: 1
fieldset/SR:
  description: TIM3 status register.
  fields:
  - name: UIF
    description: UIF.
    bit_offset: 0
    bit_size: 1
  - name: CC1IF
    description: CC1IF.
    bit_offset: 1
    bit_size: 1
  - name: CC2IF
    description: CC2IF.
    bit_offset: 2
    bit_size: 1
  - name: CC3IF
    description: CC3IF.
    bit_offset: 3
    bit_size: 1
  - name: CC4IF
    description: CC4IF.
    bit_offset: 4
    bit_size: 1
  - name: COMIF
    description: COMIF.
    bit_offset: 5
    bit_size: 1
  - name: TIF
    description: TIF.
    bit_offset: 6
    bit_size: 1
  - name: BIF
    description: BIF.
    bit_offset: 7
    bit_size: 1
  - name: B2IF
    description: B2IF.
    bit_offset: 8
    bit_size: 1
  - name: CC1OF
    description: CC1OF.
    bit_offset: 9
    bit_size: 1
  - name: CC2OF
    description: CC2OF.
    bit_offset: 10
    bit_size: 1
  - name: CC3OF
    description: CC3OF.
    bit_offset: 11
    bit_size: 1
  - name: CC4OF
    description: CC4OF.
    bit_offset: 12
    bit_size: 1
  - name: SBIF
    description: SBIF.
    bit_offset: 13
    bit_size: 1
  - name: CC5IF
    description: CC5IF.
    bit_offset: 16
    bit_size: 1
  - name: CC6IF
    description: CC6IF.
    bit_offset: 17
    bit_size: 1