block/RTC:
  description: RTC.
  items:
  - name: TR
    description: 'The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
    byte_offset: 0
    fieldset: TR
  - name: DR
    description: 'The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
    byte_offset: 4
    fieldset: DR
  - name: SSR
    description: RTC sub second register.
    byte_offset: 8
    access: Read
    fieldset: SSR
  - name: ICSR
    description: 'This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
    byte_offset: 12
    fieldset: ICSR
  - name: PRER
    description: 'This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page1830. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
    byte_offset: 16
    fieldset: PRER
  - name: WUTR
    description: 'This register can be written only when WUTWF is set to 1 in RTC_ICSR. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
    byte_offset: 20
    fieldset: WUTR
  - name: CR
    description: 'This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
    byte_offset: 24
    fieldset: CR
  - name: SMCR
    description: This register can be written only when the APB access is secure.
    byte_offset: 32
    fieldset: SMCR
  - name: WPR
    description: RTC write protection register.
    byte_offset: 36
    access: Write
    fieldset: WPR
  - name: CALR
    description: 'This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
    byte_offset: 40
    fieldset: CALR
  - name: SHIFTR
    description: 'This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
    byte_offset: 44
    access: Write
    fieldset: SHIFTR
  - name: ALRMR
    description: Alarm %s register.
    array:
      len: 2
      stride: 8
    byte_offset: 64
    fieldset: ALRMR
  - name: ALRMSSR
    description: Alarm %s sub-second register.
    array:
      len: 2
      stride: 8
    byte_offset: 68
    fieldset: ALRMSSR
  - name: SR
    description: 'This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
    byte_offset: 80
    access: Read
    fieldset: SR
  - name: MISR
    description: RTC non-secure masked interrupt status register.
    byte_offset: 84
    access: Read
    fieldset: MISR
  - name: SMISR
    description: 'This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
    byte_offset: 88
    access: Read
    fieldset: SMISR
  - name: SCR
    description: 'This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
    byte_offset: 92
    access: Write
    fieldset: SCR
  - name: CFGR
    description: RTC configuration register.
    byte_offset: 96
    fieldset: CFGR
  - name: HWCFGR
    description: RTC hardware configuration register.
    byte_offset: 1008
    access: Read
    fieldset: HWCFGR
  - name: VERR
    description: RTC version register.
    byte_offset: 1012
    access: Read
    fieldset: VERR
  - name: IPIDR
    description: RTC identification register.
    byte_offset: 1016
    access: Read
    fieldset: IPIDR
  - name: SIDR
    description: RTC size identification register.
    byte_offset: 1020
    access: Read
    fieldset: SIDR
fieldset/ALRMR:
  description: Alarm %s register.
  fields:
  - name: SU
    description: Second units in BCD format.
    bit_offset: 0
    bit_size: 4
  - name: ST
    description: Second tens in BCD format.
    bit_offset: 4
    bit_size: 3
  - name: MSK1
    description: Alarm seconds mask.
    bit_offset: 7
    bit_size: 1
    enum: MSK1
  - name: MNU
    description: Minute units in BCD format.
    bit_offset: 8
    bit_size: 4
  - name: MNT
    description: Minute tens in BCD format.
    bit_offset: 12
    bit_size: 3
  - name: MSK2
    description: Alarm minutes mask.
    bit_offset: 15
    bit_size: 1
    enum: MSK2
  - name: HU
    description: Hour units in BCD format.
    bit_offset: 16
    bit_size: 4
  - name: HT
    description: Hour tens in BCD format.
    bit_offset: 20
    bit_size: 2
  - name: PM
    description: PM.
    bit_offset: 22
    bit_size: 1
    enum: ALRMR_PM
  - name: MSK3
    description: Alarm hours mask.
    bit_offset: 23
    bit_size: 1
    enum: MSK3
  - name: DU
    description: Date units or day in BCD format.
    bit_offset: 24
    bit_size: 4
  - name: DT
    description: Date tens in BCD format.
    bit_offset: 28
    bit_size: 2
  - name: WDSEL
    description: WDSEL.
    bit_offset: 30
    bit_size: 1
    enum: WDSEL
  - name: MSK4
    description: Alarm date mask.
    bit_offset: 31
    bit_size: 1
    enum: MSK4
fieldset/ALRMSSR:
  description: Alarm %s sub-second register.
  fields:
  - name: SS
    description: SS.
    bit_offset: 0
    bit_size: 15
  - name: MASKSS
    description: MASKSS.
    bit_offset: 24
    bit_size: 4
fieldset/CALR:
  description: 'This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
  fields:
  - name: CALM
    description: CALM.
    bit_offset: 0
    bit_size: 9
  - name: CALW16
    description: CALW16.
    bit_offset: 13
    bit_size: 1
    enum: CALW16
  - name: CALW8
    description: CALW8.
    bit_offset: 14
    bit_size: 1
    enum: CALW8
  - name: CALP
    description: CALP.
    bit_offset: 15
    bit_size: 1
    enum: CALP
fieldset/CFGR:
  description: RTC configuration register.
  fields:
  - name: OUT2_RMP
    description: OUT2_RMP.
    bit_offset: 0
    bit_size: 1
  - name: LSCOEN
    description: LSCOEN.
    bit_offset: 1
    bit_size: 2
fieldset/CR:
  description: 'This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
  fields:
  - name: WUCKSEL
    description: WUCKSEL.
    bit_offset: 0
    bit_size: 3
    enum: WUCKSEL
  - name: TSEDGE
    description: TSEDGE.
    bit_offset: 3
    bit_size: 1
    enum: TSEDGE
  - name: REFCKON
    description: REFCKON.
    bit_offset: 4
    bit_size: 1
    enum: REFCKON
  - name: BYPSHAD
    description: BYPSHAD.
    bit_offset: 5
    bit_size: 1
    enum: BYPSHAD
  - name: FMT
    description: FMT.
    bit_offset: 6
    bit_size: 1
    enum: FMT
  - name: ALRE
    description: Alarm %s enable.
    bit_offset: 8
    bit_size: 1
    array:
      len: 2
      stride: 1
    enum: ALRE
  - name: WUTE
    description: WUTE.
    bit_offset: 10
    bit_size: 1
    enum: WUTE
  - name: TSE
    description: TSE.
    bit_offset: 11
    bit_size: 1
    enum: TSE
  - name: ALRIE
    description: Alarm %s interrupt enable.
    bit_offset: 12
    bit_size: 1
    array:
      len: 2
      stride: 1
    enum: ALRIE
  - name: WUTIE
    description: WUTIE.
    bit_offset: 14
    bit_size: 1
    enum: WUTIE
  - name: TSIE
    description: TSIE.
    bit_offset: 15
    bit_size: 1
    enum: TSIE
  - name: ADD1H
    description: ADD1H.
    bit_offset: 16
    bit_size: 1
    enum: ADD1H
  - name: SUB1H
    description: SUB1H.
    bit_offset: 17
    bit_size: 1
    enum: SUB1H
  - name: BKP
    description: BKP.
    bit_offset: 18
    bit_size: 1
    enum: BKP
  - name: COSEL
    description: COSEL.
    bit_offset: 19
    bit_size: 1
    enum: COSEL
  - name: POL
    description: POL.
    bit_offset: 20
    bit_size: 1
    enum: POL
  - name: OSEL
    description: OSEL.
    bit_offset: 21
    bit_size: 2
    enum: OSEL
  - name: COE
    description: COE.
    bit_offset: 23
    bit_size: 1
    enum: COE
  - name: ITSE
    description: ITSE.
    bit_offset: 24
    bit_size: 1
    enum: ITSE
  - name: TAMPTS
    description: TAMPTS.
    bit_offset: 25
    bit_size: 1
    enum: TAMPTS
  - name: TAMPOE
    description: TAMPOE.
    bit_offset: 26
    bit_size: 1
    enum: TAMPOE
  - name: TAMPALRM_PU
    description: TAMPALRM_PU.
    bit_offset: 29
    bit_size: 1
    enum: TAMPALRM_PU
  - name: TAMPALRM_TYPE
    description: TAMPALRM_TYPE.
    bit_offset: 30
    bit_size: 1
    enum: TAMPALRM_TYPE
  - name: OUT2EN
    description: OUT2EN.
    bit_offset: 31
    bit_size: 1
    enum: OUT2EN
fieldset/DR:
  description: 'The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
  fields:
  - name: DU
    description: DU.
    bit_offset: 0
    bit_size: 4
  - name: DT
    description: DT.
    bit_offset: 4
    bit_size: 2
  - name: MU
    description: MU.
    bit_offset: 8
    bit_size: 4
  - name: MT
    description: MT.
    bit_offset: 12
    bit_size: 1
  - name: WDU
    description: WDU.
    bit_offset: 13
    bit_size: 3
  - name: YU
    description: YU.
    bit_offset: 16
    bit_size: 4
  - name: YT
    description: YT.
    bit_offset: 20
    bit_size: 4
fieldset/HWCFGR:
  description: RTC hardware configuration register.
  fields:
  - name: ALARMB
    description: ALARMB.
    bit_offset: 0
    bit_size: 4
  - name: WAKEUP
    description: WAKEUP.
    bit_offset: 4
    bit_size: 4
  - name: SMOOTH_CALIB
    description: SMOOTH_CALIB.
    bit_offset: 8
    bit_size: 4
  - name: TIMESTAMP
    description: TIMESTAMP.
    bit_offset: 12
    bit_size: 4
  - name: OPTIONREG_OUT
    description: OPTIONREG_OUT.
    bit_offset: 16
    bit_size: 8
  - name: TRUST_ZONE
    description: TRUST_ZONE.
    bit_offset: 24
    bit_size: 4
fieldset/ICSR:
  description: 'This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
  fields:
  - name: ALRWF
    description: Alarm %s write flag.
    bit_offset: 0
    bit_size: 1
    array:
      len: 2
      stride: 1
  - name: WUTWF
    description: WUTWF.
    bit_offset: 2
    bit_size: 1
    enum: WUTWF
  - name: SHPF
    description: SHPF.
    bit_offset: 3
    bit_size: 1
    enum: SHPF
  - name: INITS
    description: INITS.
    bit_offset: 4
    bit_size: 1
    enum: INITS
  - name: RSF
    description: RSF.
    bit_offset: 5
    bit_size: 1
    enum: RSF
  - name: INITF
    description: INITF.
    bit_offset: 6
    bit_size: 1
    enum: INITF
  - name: INIT
    description: INIT.
    bit_offset: 7
    bit_size: 1
    enum: INIT
  - name: RECALPF
    description: RECALPF.
    bit_offset: 16
    bit_size: 1
    enum: RECALPF
fieldset/IPIDR:
  description: RTC identification register.
  fields:
  - name: ID
    description: ID.
    bit_offset: 0
    bit_size: 32
fieldset/MISR:
  description: RTC non-secure masked interrupt status register.
  fields:
  - name: ALRMF
    description: Alarm %s masked flag.
    bit_offset: 0
    bit_size: 1
    array:
      len: 2
      stride: 1
    enum: ALRMF
  - name: WUTMF
    description: WUTMF.
    bit_offset: 2
    bit_size: 1
    enum: WUTMF
  - name: TSMF
    description: TSMF.
    bit_offset: 3
    bit_size: 1
    enum: TSMF
  - name: TSOVMF
    description: TSOVMF.
    bit_offset: 4
    bit_size: 1
    enum: TSOVMF
  - name: ITSMF
    description: ITSMF.
    bit_offset: 5
    bit_size: 1
    enum: ITSMF
fieldset/PRER:
  description: 'This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page1830. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
  fields:
  - name: PREDIV_S
    description: PREDIV_S.
    bit_offset: 0
    bit_size: 15
  - name: PREDIV_A
    description: PREDIV_A.
    bit_offset: 16
    bit_size: 7
fieldset/SCR:
  description: 'This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
  fields:
  - name: CALRAF
    description: CALRAF.
    bit_offset: 0
    bit_size: 1
    enum: CALRAF
  - name: CALRBF
    description: CALRBF.
    bit_offset: 1
    bit_size: 1
    enum: CALRBF
  - name: CWUTF
    description: CWUTF.
    bit_offset: 2
    bit_size: 1
    enum: CWUTF
  - name: CTSF
    description: CTSF.
    bit_offset: 3
    bit_size: 1
    enum: CTSF
  - name: CTSOVF
    description: CTSOVF.
    bit_offset: 4
    bit_size: 1
    enum: CTSOVF
  - name: CITSF
    description: CITSF.
    bit_offset: 5
    bit_size: 1
    enum: CITSF
fieldset/SHIFTR:
  description: 'This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
  fields:
  - name: SUBFS
    description: SUBFS.
    bit_offset: 0
    bit_size: 15
  - name: ADD1S
    description: ADD1S.
    bit_offset: 31
    bit_size: 1
    enum: ADD1S
fieldset/SIDR:
  description: RTC size identification register.
  fields:
  - name: SID
    description: SID.
    bit_offset: 0
    bit_size: 32
fieldset/SMCR:
  description: This register can be written only when the APB access is secure.
  fields:
  - name: ALRADPROT
    description: ALRADPROT.
    bit_offset: 0
    bit_size: 1
  - name: ALRBDPROT
    description: ALRBDPROT.
    bit_offset: 1
    bit_size: 1
  - name: WUTDPROT
    description: WUTDPROT.
    bit_offset: 2
    bit_size: 1
  - name: TSDPROT
    description: TSDPROT.
    bit_offset: 3
    bit_size: 1
  - name: CALDPROT
    description: CALDPROT.
    bit_offset: 13
    bit_size: 1
  - name: INITDPROT
    description: INITDPROT.
    bit_offset: 14
    bit_size: 1
  - name: DECPROT
    description: DECPROT.
    bit_offset: 15
    bit_size: 1
fieldset/SMISR:
  description: 'This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
  fields:
  - name: ALRAMF
    description: ALRAMF.
    bit_offset: 0
    bit_size: 1
  - name: ALRBMF
    description: ALRBMF.
    bit_offset: 1
    bit_size: 1
  - name: WUTMF
    description: WUTMF.
    bit_offset: 2
    bit_size: 1
  - name: TSMF
    description: TSMF.
    bit_offset: 3
    bit_size: 1
  - name: TSOVMF
    description: TSOVMF.
    bit_offset: 4
    bit_size: 1
  - name: ITSMF
    description: ITSMF.
    bit_offset: 5
    bit_size: 1
fieldset/SR:
  description: 'This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
  fields:
  - name: ALRF
    description: Alarm %s flag.
    bit_offset: 0
    bit_size: 1
    array:
      len: 2
      stride: 1
    enum: ALRF
  - name: WUTF
    description: WUTF.
    bit_offset: 2
    bit_size: 1
    enum: WUTF
  - name: TSF
    description: TSF.
    bit_offset: 3
    bit_size: 1
    enum: TSF
  - name: TSOVF
    description: TSOVF.
    bit_offset: 4
    bit_size: 1
    enum: TSOVF
  - name: ITSF
    description: ITSF.
    bit_offset: 5
    bit_size: 1
    enum: ITSF
fieldset/SSR:
  description: RTC sub second register.
  fields:
  - name: SS
    description: SS.
    bit_offset: 0
    bit_size: 16
fieldset/TR:
  description: 'The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
  fields:
  - name: SU
    description: SU.
    bit_offset: 0
    bit_size: 4
  - name: ST
    description: ST.
    bit_offset: 4
    bit_size: 3
  - name: MNU
    description: MNU.
    bit_offset: 8
    bit_size: 4
  - name: MNT
    description: MNT.
    bit_offset: 12
    bit_size: 3
  - name: HU
    description: HU.
    bit_offset: 16
    bit_size: 4
  - name: HT
    description: HT.
    bit_offset: 20
    bit_size: 2
  - name: PM
    description: PM.
    bit_offset: 22
    bit_size: 1
    enum: TR_PM
fieldset/VERR:
  description: RTC version register.
  fields:
  - name: MINREV
    description: MINREV.
    bit_offset: 0
    bit_size: 4
  - name: MAJREV
    description: MAJREV.
    bit_offset: 4
    bit_size: 4
fieldset/WPR:
  description: RTC write protection register.
  fields:
  - name: KEY
    description: KEY.
    bit_offset: 0
    bit_size: 8
    enum: KEY
fieldset/WUTR:
  description: 'This register can be written only when WUTWF is set to 1 in RTC_ICSR. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.'
  fields:
  - name: WUT
    description: WUT.
    bit_offset: 0
    bit_size: 16
enum/ADD1H:
  bit_size: 1
  variants:
  - name: Add1
    description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode.
    value: 1
enum/ADD1S:
  bit_size: 1
  variants:
  - name: Add1
    description: Add one second to the clock/calendar.
    value: 1
enum/ALRE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Alarm disabled.
    value: 0
  - name: Enabled
    description: Alarm enabled.
    value: 1
enum/ALRF:
  bit_size: 1
  variants:
  - name: Match
    description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR).
    value: 1
enum/ALRIE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Alarm Interrupt disabled.
    value: 0
  - name: Enabled
    description: Alarm Interrupt enabled.
    value: 1
enum/ALRMF:
  bit_size: 1
  variants:
  - name: Match
    description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR).
    value: 1
enum/ALRMR_PM:
  bit_size: 1
  variants:
  - name: AM
    description: AM or 24-hour format.
    value: 0
  - name: PM
    description: PM.
    value: 1
enum/BKP:
  bit_size: 1
  variants:
  - name: DSTNotChanged
    description: Daylight Saving Time change has not been performed.
    value: 0
  - name: DSTChanged
    description: Daylight Saving Time change has been performed.
    value: 1
enum/BYPSHAD:
  bit_size: 1
  variants:
  - name: ShadowReg
    description: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles.
    value: 0
  - name: BypassShadowReg
    description: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters.
    value: 1
enum/CALP:
  bit_size: 1
  variants:
  - name: NoChange
    description: No RTCCLK pulses are added.
    value: 0
  - name: IncreaseFreq
    description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm).
    value: 1
enum/CALRAF:
  bit_size: 1
  variants:
  - name: Clear
    description: Clear interrupt flag.
    value: 1
enum/CALRBF:
  bit_size: 1
  variants:
  - name: Clear
    description: Clear interrupt flag.
    value: 1
enum/CALW16:
  bit_size: 1
  variants:
  - name: SixteenSeconds
    description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1.
    value: 1
enum/CALW8:
  bit_size: 1
  variants:
  - name: EightSeconds
    description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected.
    value: 1
enum/CITSF:
  bit_size: 1
  variants:
  - name: Clear
    description: Clear interrupt flag.
    value: 1
enum/COE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Calibration output disabled.
    value: 0
  - name: Enabled
    description: Calibration output enabled.
    value: 1
enum/COSEL:
  bit_size: 1
  variants:
  - name: CalFreq_512Hz
    description: Calibration output is 512 Hz (with default prescaler setting).
    value: 0
  - name: CalFreq_1Hz
    description: Calibration output is 1 Hz (with default prescaler setting).
    value: 1
enum/CTSF:
  bit_size: 1
  variants:
  - name: Clear
    description: Clear interrupt flag.
    value: 1
enum/CTSOVF:
  bit_size: 1
  variants:
  - name: Clear
    description: Clear interrupt flag.
    value: 1
enum/CWUTF:
  bit_size: 1
  variants:
  - name: Clear
    description: Clear interrupt flag.
    value: 1
enum/FMT:
  bit_size: 1
  variants:
  - name: TwentyFourHour
    description: 24 hour/day format.
    value: 0
  - name: AmPm
    description: AM/PM hour format.
    value: 1
enum/INIT:
  bit_size: 1
  variants:
  - name: FreeRunningMode
    description: Free running mode.
    value: 0
  - name: InitMode
    description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
    value: 1
enum/INITF:
  bit_size: 1
  variants:
  - name: NotAllowed
    description: Calendar registers update is not allowed.
    value: 0
  - name: Allowed
    description: Calendar registers update is allowed.
    value: 1
enum/INITS:
  bit_size: 1
  variants:
  - name: NotInitalized
    description: Calendar has not been initialized.
    value: 0
  - name: Initalized
    description: Calendar has been initialized.
    value: 1
enum/ITSE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Internal event timestamp disabled.
    value: 0
  - name: Enabled
    description: Internal event timestamp enabled.
    value: 1
enum/ITSF:
  bit_size: 1
  variants:
  - name: TimestampEvent
    description: This flag is set by hardware when a timestamp on the internal event occurs.
    value: 1
enum/ITSMF:
  bit_size: 1
  variants:
  - name: TimestampEvent
    description: This flag is set by hardware when a timestamp on the internal event occurs.
    value: 1
enum/KEY:
  bit_size: 8
  variants:
  - name: Activate
    description: Activate write protection (any value that is not the keys).
    value: 0
  - name: Deactivate2
    description: Key 2.
    value: 83
  - name: Deactivate1
    description: Key 1.
    value: 202
enum/MSK1:
  bit_size: 1
  variants:
  - name: Mask
    description: Alarm set if the date/day match.
    value: 0
  - name: NotMask
    description: Date/day don’t care in Alarm comparison.
    value: 1
enum/MSK2:
  bit_size: 1
  variants:
  - name: Mask
    description: Alarm set if the date/day match.
    value: 0
  - name: NotMask
    description: Date/day don’t care in Alarm comparison.
    value: 1
enum/MSK3:
  bit_size: 1
  variants:
  - name: Mask
    description: Alarm set if the date/day match.
    value: 0
  - name: NotMask
    description: Date/day don’t care in Alarm comparison.
    value: 1
enum/MSK4:
  bit_size: 1
  variants:
  - name: Mask
    description: Alarm set if the date/day match.
    value: 0
  - name: NotMask
    description: Date/day don’t care in Alarm comparison.
    value: 1
enum/OSEL:
  bit_size: 2
  variants:
  - name: Disabled
    description: Output disabled.
    value: 0
  - name: AlarmA
    description: Alarm A output enabled.
    value: 1
  - name: AlarmB
    description: Alarm B output enabled.
    value: 2
  - name: Wakeup
    description: Wakeup output enabled.
    value: 3
enum/OUT2EN:
  bit_size: 1
  variants:
  - name: Disabled
    description: RTC output 2 disable.
    value: 0
  - name: Enabled
    description: RTC output 2 enable.
    value: 1
enum/POL:
  bit_size: 1
  variants:
  - name: High
    description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]).
    value: 0
  - name: Low
    description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]).
    value: 1
enum/RECALPF:
  bit_size: 1
  variants:
  - name: Pending
    description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0.
    value: 1
enum/REFCKON:
  bit_size: 1
  variants:
  - name: Disabled
    description: RTC_REFIN detection disabled.
    value: 0
  - name: Enabled
    description: RTC_REFIN detection enabled.
    value: 1
enum/RSF:
  bit_size: 1
  variants:
  - name: R_NotSynced_W_Clear
    description: Calendar shadow registers not yet synchronized.
    value: 0
  - name: Synced
    description: Calendar shadow registers synchronized.
    value: 1
enum/SHPF:
  bit_size: 1
  variants:
  - name: NoShiftPending
    description: No shift operation is pending.
    value: 0
  - name: ShiftPending
    description: A shift operation is pending.
    value: 1
enum/SUB1H:
  bit_size: 1
  variants:
  - name: Sub1
    description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode.
    value: 1
enum/TAMPALRM_PU:
  bit_size: 1
  variants:
  - name: NoPullUp
    description: No pull-up is applied on TAMPALRM output.
    value: 0
  - name: PullUp
    description: A pull-up is applied on TAMPALRM output.
    value: 1
enum/TAMPALRM_TYPE:
  bit_size: 1
  variants:
  - name: PushPull
    description: TAMPALRM is push-pull output.
    value: 0
  - name: OpenDrain
    description: TAMPALRM is open-drain output.
    value: 1
enum/TAMPOE:
  bit_size: 1
  variants:
  - name: Disabled
    description: The tamper flag is not routed on TAMPALRM.
    value: 0
  - name: Enabled
    description: The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL.
    value: 1
enum/TAMPTS:
  bit_size: 1
  variants:
  - name: Disabled
    description: Tamper detection event does not cause a RTC timestamp to be saved.
    value: 0
  - name: Enabled
    description: Save RTC timestamp on tamper detection event.
    value: 1
enum/TR_PM:
  bit_size: 1
  variants:
  - name: AM
    description: AM or 24-hour format.
    value: 0
  - name: PM
    description: PM.
    value: 1
enum/TSE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Timestamp disabled.
    value: 0
  - name: Enabled
    description: Timestamp enabled.
    value: 1
enum/TSEDGE:
  bit_size: 1
  variants:
  - name: RisingEdge
    description: RTC_TS input rising edge generates a time-stamp event.
    value: 0
  - name: FallingEdge
    description: RTC_TS input falling edge generates a time-stamp event.
    value: 1
enum/TSF:
  bit_size: 1
  variants:
  - name: TimestampEvent
    description: This flag is set by hardware when a time-stamp event occurs.
    value: 1
enum/TSIE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Time-stamp Interrupt disabled.
    value: 0
  - name: Enabled
    description: Time-stamp Interrupt enabled.
    value: 1
enum/TSMF:
  bit_size: 1
  variants:
  - name: TimestampEvent
    description: This flag is set by hardware when a time-stamp event occurs.
    value: 1
enum/TSOVF:
  bit_size: 1
  variants:
  - name: Overflow
    description: This flag is set by hardware when a time-stamp event occurs while TSF is already set.
    value: 1
enum/TSOVMF:
  bit_size: 1
  variants:
  - name: Overflow
    description: This flag is set by hardware when a time-stamp event occurs while TSF is already set.
    value: 1
enum/WDSEL:
  bit_size: 1
  variants:
  - name: DateUnits
    description: DU[3:0] represents the date units.
    value: 0
  - name: WeekDay
    description: DU[3:0] represents the week day. DT[1:0] is don’t care.
    value: 1
enum/WUCKSEL:
  bit_size: 3
  variants:
  - name: Div16
    description: RTC/16 clock is selected.
    value: 0
  - name: Div8
    description: RTC/8 clock is selected.
    value: 1
  - name: Div4
    description: RTC/4 clock is selected.
    value: 2
  - name: Div2
    description: RTC/2 clock is selected.
    value: 3
  - name: ClockSpare
    description: ck_spre (usually 1 Hz) clock is selected.
    value: 4
  - name: ClockSpareWithOffset
    description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value.
    value: 6
enum/WUTE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Wakeup timer disabled.
    value: 0
  - name: Enabled
    description: Wakeup timer enabled.
    value: 1
enum/WUTF:
  bit_size: 1
  variants:
  - name: Zero
    description: This flag is set by hardware when the wakeup auto-reload counter reaches 0.
    value: 1
enum/WUTIE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Wakeup timer interrupt disabled.
    value: 0
  - name: Enabled
    description: Wakeup timer interrupt enabled.
    value: 1
enum/WUTMF:
  bit_size: 1
  variants:
  - name: Zero
    description: This flag is set by hardware when the wakeup auto-reload counter reaches 0.
    value: 1
enum/WUTWF:
  bit_size: 1
  variants:
  - name: UpdateNotAllowed
    description: Wakeup timer configuration update not allowed.
    value: 0
  - name: UpdateAllowed
    description: Wakeup timer configuration update allowed.
    value: 1