block/RCC:
  description: RCC.
  items:
  - name: TZCR
    description: This register is used to switch the RCC into secure mode. This register can only be accessed in secure mode.
    byte_offset: 0
    fieldset: TZCR
  - name: OCENSETR
    description: 'This register is used to control the oscillators.Writing to this register has no effect, writing will set the corresponding bits. Reading will give the effective values of each bit.If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
    byte_offset: 12
    fieldset: OCENSETR
  - name: OCENCLRR
    description: 'This register is used to control the oscillators.Writing to this register has no effect, writing will clear the corresponding bits. Reading will give the effective values of the enable bits.If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
    byte_offset: 16
    fieldset: OCENCLRR
  - name: HSICFGR
    description: 'This register is used to configure the HSI. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
    byte_offset: 24
    fieldset: HSICFGR
  - name: CSICFGR
    description: This register is used to fine-tune the CSI frequency. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See The clock restore sequence description for details.
    byte_offset: 28
    fieldset: CSICFGR
  - name: MPCKSELR
    description: 'This register is used to select the clock source for the MPU. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
    byte_offset: 32
    fieldset: MPCKSELR
  - name: ASSCKSELR
    description: 'This register is used to select the clock source for the AXI sub-system. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
    byte_offset: 36
    fieldset: ASSCKSELR
  - name: RCK12SELR
    description: 'This register is used to select the reference clock for PLL1 and PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
    byte_offset: 40
    fieldset: RCK12SELR
  - name: MPCKDIVR
    description: 'This register is used to control the MPU clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.'
    byte_offset: 44
    fieldset: MPCKDIVR
  - name: AXIDIVR
    description: 'This register is used to control the AXI Matrix clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.'
    byte_offset: 48
    fieldset: AXIDIVR
  - name: APB4DIVR
    description: 'This register is used to control the APB4 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.'
    byte_offset: 60
    fieldset: APB4DIVR
  - name: APB5DIVR
    description: 'This register is used to control the APB5 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.'
    byte_offset: 64
    fieldset: APB5DIVR
  - name: RTCDIVR
    description: This register is used to divide the HSE clock for RTC. If TZEN = , this register can only be modified in secure mode.
    byte_offset: 68
    fieldset: RTCDIVR
  - name: MSSCKSELR
    description: 'This register is used to select the clock source for the MCU sub-system, including the MCU itself. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
    byte_offset: 72
    fieldset: MSSCKSELR
  - name: PLL1CR
    description: 'This register is used to control the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
    byte_offset: 128
    fieldset: PLL1CR
  - name: PLL1CFGR1
    description: 'This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
    byte_offset: 132
    fieldset: PLL1CFGR1
  - name: PLL1CFGR2
    description: 'This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
    byte_offset: 136
    fieldset: PLL1CFGR2
  - name: PLL1FRACR
    description: 'This register is used to fine-tune the frequency of the PLL1 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
    byte_offset: 140
    fieldset: PLL1FRACR
  - name: PLL1CSGR
    description: 'This register is used to configure the PLL1.It is not recommended to change the content of this register when the PLL1 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
    byte_offset: 144
    fieldset: PLL1CSGR
  - name: PLL2CR
    description: 'This register is used to control the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
    byte_offset: 148
    fieldset: PLL2CR
  - name: PLL2CFGR1
    description: 'This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
    byte_offset: 152
    fieldset: PLL2CFGR1
  - name: PLL2CFGR2
    description: 'This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
    byte_offset: 156
    fieldset: PLL2CFGR2
  - name: PLL2FRACR
    description: 'This register is used to fine-tune the frequency of the PLL2 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
    byte_offset: 160
    fieldset: PLL2FRACR
  - name: PLL2CSGR
    description: 'This register is used to configure the PLL2. It is not recommended to change the content of this register when the PLL2 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
    byte_offset: 164
    fieldset: PLL2CSGR
  - name: I2C46CKSELR
    description: 'This register is used to control the selection of the kernel clock for the I2C4 and I2C6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.'
    byte_offset: 192
    fieldset: I2C46CKSELR
  - name: SPI6CKSELR
    description: 'This register is used to control the selection of the kernel clock for the SPI6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.'
    byte_offset: 196
    fieldset: SPI6CKSELR
  - name: UART1CKSELR
    description: 'This register is used to control the selection of the kernel clock for the USART1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.'
    byte_offset: 200
    fieldset: UART1CKSELR
  - name: RNG1CKSELR
    description: 'This register is used to control the selection of the kernel clock for the RNG1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.'
    byte_offset: 204
    fieldset: RNG1CKSELR
  - name: CPERCKSELR
    description: 'This register is used to select an oscillator source as kernel clock for the per_ck clock. The per_ck clock is distributed to several peripherals. Refer to Section: Clock enabling delays.'
    byte_offset: 208
    fieldset: CPERCKSELR
  - name: STGENCKSELR
    description: 'This register is used to select the peripheral clock for the STGEN block. Note that this clock is used to provide a time reference for the application. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.'
    byte_offset: 212
    fieldset: STGENCKSELR
  - name: DDRITFCR
    description: This register is used to control the DDR interface, including the DDRC and DDRPHYC. If TZEN = , this register can only be modified in secure mode.
    byte_offset: 216
    fieldset: DDRITFCR
  - name: MP_BOOTCR
    description: 'This register is used to control the HOLD boot function when the system exits from Standby. Refer to Section: MCU HOLD_BOOT after processor reset. This register is reset when a system reset occurs, but not when the circuit exits from Standby (app_rst reset).If TZEN = , this register can only be modified in secure mode. This register can only be accessed by the MPU.'
    byte_offset: 256
    fieldset: MP_BOOTCR
  - name: MP_SREQSETR
    description: Writing has no effect, reading will return the values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode.
    byte_offset: 260
    fieldset: MP_SREQSETR
  - name: MP_SREQCLRR
    description: Writing has no effect, reading will return the effective values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode.
    byte_offset: 264
    fieldset: MP_SREQCLRR
  - name: MP_GCR
    description: The register contains global control bits. If TZEN = , this register can only be modified in secure mode.
    byte_offset: 268
    fieldset: MP_GCR
  - name: MP_APRSTCR
    description: This register is used to control the behavior of the warm reset. If TZEN = , this register can only be modified in secure mode.
    byte_offset: 272
    fieldset: MP_APRSTCR
  - name: MP_APRSTSR
    description: This register provides a status of the RDCTL. If TZEN = , this register can only be modified in secure mode.
    byte_offset: 276
    access: Read
    fieldset: MP_APRSTSR
  - name: BDCR
    description: 'This register is used to control the LSE function. Wait states are inserted in case of successive write accesses to this register. The number of wait states may be up to 7 cycles of AHB4 clock.After a system reset, the register RCC_BDCR is write-protected. In order to modify this register, the DBP bit in the PWR control register 1 (PWR_CR1) has to be set to . Bits of RCC_BDCR register are only reset after a backup domain reset: nreset_vsw (see Section10.3.6: Backup domain reset). Any other internal or external reset will not have any effect on these bits.This register is located into the VSW domain. If TZEN = , this register can only be modified in secure mode.'
    byte_offset: 320
    fieldset: BDCR
  - name: RDLSICR
    description: This register is used to control the minimum NRST active duration and LSI function.0 to 7 wait states are inserted for word, half-word and byte accesses. Wait states are inserted in case of successive accesses to this register.This register is reset by the por_rst reset, and it is located into the VDD domain. If TZEN = , this register can only be modified in secure mode.
    byte_offset: 324
    fieldset: RDLSICR
  - name: APB4RSTSETR
    description: This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
    byte_offset: 384
    fieldset: APB4RSTSETR
  - name: APB4RSTCLRR
    description: This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.
    byte_offset: 388
    fieldset: APB4RSTCLRR
  - name: APB5RSTSETR
    description: This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
    byte_offset: 392
    fieldset: APB5RSTSETR
  - name: APB5RSTCLRR
    description: This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
    byte_offset: 396
    fieldset: APB5RSTCLRR
  - name: AHB5RSTSETR
    description: This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
    byte_offset: 400
    fieldset: AHB5RSTSETR
  - name: AHB5RSTCLRR
    description: This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
    byte_offset: 404
    fieldset: AHB5RSTCLRR
  - name: AHB6RSTSETR
    description: This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
    byte_offset: 408
    fieldset: AHB6RSTSETR
  - name: AHB6RSTCLRR
    description: This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.
    byte_offset: 412
    fieldset: AHB6RSTCLRR
  - name: TZAHB6RSTSETR
    description: This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
    byte_offset: 416
    fieldset: TZAHB6RSTSETR
  - name: TZAHB6RSTCLRR
    description: This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
    byte_offset: 420
    fieldset: TZAHB6RSTCLRR
  - name: MP_APB4ENSETR
    description: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to.
    byte_offset: 512
    fieldset: MP_APB4ENSETR
  - name: MP_APB4ENCLRR
    description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to.
    byte_offset: 516
    fieldset: MP_APB4ENCLRR
  - name: MP_APB5ENSETR
    description: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to.
    byte_offset: 520
    fieldset: MP_APB5ENSETR
  - name: MP_APB5ENCLRR
    description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to.
    byte_offset: 524
    fieldset: MP_APB5ENCLRR
  - name: MP_AHB5ENSETR
    description: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
    byte_offset: 528
    fieldset: MP_AHB5ENSETR
  - name: MP_AHB5ENCLRR
    description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
    byte_offset: 532
    fieldset: MP_AHB5ENCLRR
  - name: MP_AHB6ENSETR
    description: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to.
    byte_offset: 536
    fieldset: MP_AHB6ENSETR
  - name: MP_AHB6ENCLRR
    description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to.
    byte_offset: 540
    fieldset: MP_AHB6ENCLRR
  - name: MP_TZAHB6ENSETR
    description: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
    byte_offset: 544
    fieldset: MP_TZAHB6ENSETR
  - name: MP_TZAHB6ENCLRR
    description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
    byte_offset: 548
    fieldset: MP_TZAHB6ENCLRR
  - name: MC_APB4ENSETR
    description: This register is used to set the peripheral clock enable bit.
    byte_offset: 640
    fieldset: MC_APB4ENSETR
  - name: MC_APB4ENCLRR
    description: This register is used to clear the peripheral clock enable bit.
    byte_offset: 644
    fieldset: MC_APB4ENCLRR
  - name: MC_APB5ENSETR
    description: This register is used to set the peripheral clock enable bit.
    byte_offset: 648
    fieldset: MC_APB5ENSETR
  - name: MC_APB5ENCLRR
    description: This register is used to clear the peripheral clock enable bit.
    byte_offset: 652
    fieldset: MC_APB5ENCLRR
  - name: MC_AHB5ENSETR
    description: This register is used to set the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode.
    byte_offset: 656
    fieldset: MC_AHB5ENSETR
  - name: MC_AHB5ENCLRR
    description: This register is used to clear the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode.
    byte_offset: 660
    fieldset: MC_AHB5ENCLRR
  - name: MC_AHB6ENSETR
    description: This register is used to set the peripheral clock enable bit.
    byte_offset: 664
    fieldset: MC_AHB6ENSETR
  - name: MC_AHB6ENCLRR
    description: This register is used to clear the peripheral clock enable bit.
    byte_offset: 668
    fieldset: MC_AHB6ENCLRR
  - name: MP_APB4LPENSETR
    description: This register is used by the MCU in order to clear the PERxLPEN bits.
    byte_offset: 768
    fieldset: MP_APB4LPENSETR
  - name: MP_APB4LPENCLRR
    description: This register is used by the MCU.
    byte_offset: 772
    fieldset: MP_APB4LPENCLRR
  - name: MP_APB5LPENSETR
    description: This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
    byte_offset: 776
    fieldset: MP_APB5LPENSETR
  - name: MP_APB5LPENCLRR
    description: This register is used by the Mpu.
    byte_offset: 780
    fieldset: MP_APB5LPENCLRR
  - name: MP_AHB5LPENSETR
    description: This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
    byte_offset: 784
    fieldset: MP_AHB5LPENSETR
  - name: MP_AHB5LPENCLRR
    description: This register is used by the MCU.
    byte_offset: 788
    fieldset: MP_AHB5LPENCLRR
  - name: MP_AHB6LPENSETR
    description: This register is used by the MCU in order to clear the PERxLPEN bits.
    byte_offset: 792
    fieldset: MP_AHB6LPENSETR
  - name: MP_AHB6LPENCLRR
    description: This register is used by the MCU in order to clear the PERxLPEN bits.
    byte_offset: 796
    fieldset: MP_AHB6LPENCLRR
  - name: MP_TZAHB6LPENSETR
    description: This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
    byte_offset: 800
    fieldset: MP_TZAHB6LPENSETR
  - name: MP_TZAHB6LPENCLRR
    description: This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
    byte_offset: 804
    fieldset: MP_TZAHB6LPENCLRR
  - name: MC_APB4LPENSETR
    description: This register is used by the MCU in order to set the PERxLPEN bit.
    byte_offset: 896
    fieldset: MC_APB4LPENSETR
  - name: MC_APB4LPENCLRR
    description: This register is used by the MCU in order to clear the PERxLPEN bit.
    byte_offset: 900
    fieldset: MC_APB4LPENCLRR
  - name: MC_APB5LPENSETR
    description: This register is used by the MCU in order to set the PERxLPEN bit.
    byte_offset: 904
    fieldset: MC_APB5LPENSETR
  - name: MC_APB5LPENCLRR
    description: This register is used by the MCU in order to clear the PERxLPEN bit.
    byte_offset: 908
    fieldset: MC_APB5LPENCLRR
  - name: MC_AHB5LPENSETR
    description: This register is used by the MCU in order to set the PERxLPEN bit. If TZEN = , this register can only be modified in secure mode.
    byte_offset: 912
    fieldset: MC_AHB5LPENSETR
  - name: MC_AHB5LPENCLRR
    description: This register is used by the MCU in order to clear the PERxLPEN bit If TZEN = , this register can only be modified in secure mode.
    byte_offset: 916
    fieldset: MC_AHB5LPENCLRR
  - name: MC_AHB6LPENSETR
    description: This register is used by the MCU in order to set the PERxLPEN bit.
    byte_offset: 920
    fieldset: MC_AHB6LPENSETR
  - name: MC_AHB6LPENCLRR
    description: This register is used by the MCU in order to clear the PERxLPEN bit.
    byte_offset: 924
    fieldset: MC_AHB6LPENCLRR
  - name: BR_RSTSCLRR
    description: 'This register is used by the BOOTROM to check the reset source. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). Refer to Section10.3.13: Reset source identification for details.This register except MPUP[1:0]RSTF flags is located into VDD domain, and is reset by por_rst reset. The MPUP[1:0]RSTF flags are located into VDDCORE and are reset by nreset. If TZEN = , this register can only be modified in secure mode.'
    byte_offset: 1024
    fieldset: BR_RSTSCLRR
  - name: MP_GRSTCSETR
    description: This register is used by the MPU in order to generate either a MCU reset or a system reset or a reset of one of the two MPU processors. Writing has no effect, reading returns the effective values of the corresponding bits. Writing a activates the reset.
    byte_offset: 1028
    fieldset: MP_GRSTCSETR
  - name: MP_RSTSCLRR
    description: 'This register is used by the MPU to check the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode.'
    byte_offset: 1032
    fieldset: MP_RSTSCLRR
  - name: MP_IWDGFZSETR
    description: This register is used by the BOOTROM in order to freeze the IWDGs clocks. After a system reset or Standby reset (nreset), or a CStandby reset (cstby_rst) the MPU is allowed to write it once.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
    byte_offset: 1036
    fieldset: MP_IWDGFZSETR
  - name: MP_IWDGFZCLRR
    description: This register is used by the BOOTROM in order to unfreeze the IWDGs clocks. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
    byte_offset: 1040
    fieldset: MP_IWDGFZCLRR
  - name: MP_CIER
    description: 'This register shall be used by the MPU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode.'
    byte_offset: 1044
    fieldset: MP_CIER
  - name: MP_CIFR
    description: 'This register shall be used by the MPU in order to read and clear the interrupt flags.Writing has no effect, writing will clear the corresponding flag.Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode.'
    byte_offset: 1048
    fieldset: MP_CIFR
  - name: PWRLPDLYCR
    description: This register is used to program the delay between the moment where the system exits from one of the Stop modes, and the moment where it is allowed to enable the PLLs and provide a clock to bridges and processors. If TZEN = , this register can only be modified in secure mode.
    byte_offset: 1052
    fieldset: PWRLPDLYCR
  - name: MP_RSTSSETR
    description: 'This register is dedicated to the BOOTROM code in order to update the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby. The application software shall not use this register. In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR).Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode.'
    byte_offset: 1056
    fieldset: MP_RSTSSETR
  - name: MCO1CFGR
    description: This register is used to select the clock generated on MCO1 output.
    byte_offset: 2048
    fieldset: MCO1CFGR
  - name: MCO2CFGR
    description: This register is used to select the clock generated on MCO2 output.
    byte_offset: 2052
    fieldset: MCO2CFGR
  - name: OCRDYR
    description: This is a read-only access register, It contains the status flags of oscillators. Writing has no effect.
    byte_offset: 2056
    access: Read
    fieldset: OCRDYR
  - name: DBGCFGR
    description: This is register contains the enable control of the debug and trace function, and the clock divider for the trace function.
    byte_offset: 2060
    fieldset: DBGCFGR
  - name: RCK3SELR
    description: This register is used to select the reference clock for PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
    byte_offset: 2080
    fieldset: RCK3SELR
  - name: RCK4SELR
    description: This register is used to select the reference clock for PLL4.
    byte_offset: 2084
    fieldset: RCK4SELR
  - name: TIMG1PRER
    description: 'This register is used to control the prescaler value of timers located into APB1 domain. It concerns TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13 and TIM14. Refer to Section: Sub-system clock generation for additional information.'
    byte_offset: 2088
    fieldset: TIMG1PRER
  - name: TIMG2PRER
    description: 'This register is used to control the prescaler value of timers located into APB2 domain. It concerns TIM1, TIM8, TIM15, TIM16, and TIM17. Refer to Section: Sub-system clock generation for additional information.'
    byte_offset: 2092
    fieldset: TIMG2PRER
  - name: MCUDIVR
    description: 'This register is used to control the MCU sub-system clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.'
    byte_offset: 2096
    fieldset: MCUDIVR
  - name: APB1DIVR
    description: 'This register is used to control the APB1 clock prescaler. Refer to section Section1.4.6.3: Sub-System Clock Generation for additional information.'
    byte_offset: 2100
    fieldset: APB1DIVR
  - name: APB2DIVR
    description: 'This register is used to control the APB2 clock prescaler. Refer to Section: Sub-system clock generation for additional information.'
    byte_offset: 2104
    fieldset: APB2DIVR
  - name: APB3DIVR
    description: 'This register is used to control the APB3 clock prescaler. Refer to Section: Sub-system clock generation for additional information.'
    byte_offset: 2108
    fieldset: APB3DIVR
  - name: PLL3CR
    description: This register is used to control the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
    byte_offset: 2176
    fieldset: PLL3CR
  - name: PLL3CFGR1
    description: This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
    byte_offset: 2180
    fieldset: PLL3CFGR1
  - name: PLL3CFGR2
    description: This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
    byte_offset: 2184
    fieldset: PLL3CFGR2
  - name: PLL3FRACR
    description: This register is used to fine-tune the frequency of the PLL3 VCO. If TZEN = MCKPROT = , this register can only be modified in secure mode.
    byte_offset: 2188
    fieldset: PLL3FRACR
  - name: PLL3CSGR
    description: 'This register is used to configure the PLL3.It is not recommended to change the content of this register when the PLL3 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode.'
    byte_offset: 2192
    fieldset: PLL3CSGR
  - name: PLL4CR
    description: This register is used to control the PLL4.
    byte_offset: 2196
    fieldset: PLL4CR
  - name: PLL4CFGR1
    description: This register is used to configure the PLL4.
    byte_offset: 2200
    fieldset: PLL4CFGR1
  - name: PLL4CFGR2
    description: This register is used to configure the PLL4.
    byte_offset: 2204
    fieldset: PLL4CFGR2
  - name: PLL4FRACR
    description: This register is used to fine-tune the frequency of the PLL4 VCO.
    byte_offset: 2208
    fieldset: PLL4FRACR
  - name: PLL4CSGR
    description: 'This register is used to configure the PLL4.It is not recommended to change the content of this register when the PLL4 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode.'
    byte_offset: 2212
    fieldset: PLL4CSGR
  - name: I2C12CKSELR
    description: 'This register is used to control the selection of the kernel clock for the I2C1 and I2C2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2240
    fieldset: I2C12CKSELR
  - name: I2C35CKSELR
    description: 'This register is used to control the selection of the kernel clock for the I2C3 and I2C5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2244
    fieldset: I2C35CKSELR
  - name: SAI1CKSELR
    description: 'This register is used to control the selection of the kernel clock for the SAI1 and DFSDM audio clock. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2248
    fieldset: SAI1CKSELR
  - name: SAI2CKSELR
    description: 'This register is used to control the selection of the kernel clock for the SAI2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2252
    fieldset: SAI2CKSELR
  - name: SAI3CKSELR
    description: 'This register is used to control the selection of the kernel clock for the SAI3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2256
    fieldset: SAI3CKSELR
  - name: SAI4CKSELR
    description: 'This register is used to control the selection of the kernel clock for the SAI4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2260
    fieldset: SAI4CKSELR
  - name: SPI2S1CKSELR
    description: 'This register is used to control the selection of the kernel clock for the SPI/I2S1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2264
    fieldset: SPI2S1CKSELR
  - name: SPI2S23CKSELR
    description: 'This register is used to control the selection of the kernel clock for the SPI/I2S2,3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2268
    fieldset: SPI2S23CKSELR
  - name: SPI45CKSELR
    description: 'This register is used to control the selection of the kernel clock for the SPI4,5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2272
    fieldset: SPI45CKSELR
  - name: UART6CKSELR
    description: 'This register is used to control the selection of the kernel clock for the USART6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2276
    fieldset: UART6CKSELR
  - name: UART24CKSELR
    description: 'This register is used to control the selection of the kernel clock for the USART2 and UART4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2280
    fieldset: UART24CKSELR
  - name: UART35CKSELR
    description: 'This register is used to control the selection of the kernel clock for the USART3 and UART5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2284
    fieldset: UART35CKSELR
  - name: UART78CKSELR
    description: 'This register is used to control the selection of the kernel clock for the UART7 and UART8. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2288
    fieldset: UART78CKSELR
  - name: SDMMC12CKSELR
    description: 'This register is used to control the selection of the kernel clock for the SDMMC1 and SDMMC2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2292
    fieldset: SDMMC12CKSELR
  - name: SDMMC3CKSELR
    description: 'This register is used to control the selection of the kernel clock for the SDMMC3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2296
    fieldset: SDMMC3CKSELR
  - name: ETHCKSELR
    description: 'This register is used to control the selection of the kernel clock for the ETH block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2300
    fieldset: ETHCKSELR
  - name: QSPICKSELR
    description: 'This register is used to control the selection of the kernel clock for the QUADSPI. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2304
    fieldset: QSPICKSELR
  - name: FMCCKSELR
    description: 'This register is used to control the selection of the kernel clock for the FMC block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2308
    fieldset: FMCCKSELR
  - name: FDCANCKSELR
    description: 'This register is used to control the selection of the kernel clock for the FDCAN block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2316
    fieldset: FDCANCKSELR
  - name: SPDIFCKSELR
    description: 'This register is used to control the selection of the kernel clock for the SPDIFRX. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
    byte_offset: 2324
    fieldset: SPDIFCKSELR
  - name: CECCKSELR
    description: This register is used to control the selection of the kernel clock for the CEC-HDMI.
    byte_offset: 2328
    fieldset: CECCKSELR
  - name: USBCKSELR
    description: This register is used to control the selection of the kernel clock for the USBPHY PLL of the USB HOST and USB OTG.
    byte_offset: 2332
    fieldset: USBCKSELR
  - name: RNG2CKSELR
    description: This register is used to control the selection of the kernel clock for the RNG2.
    byte_offset: 2336
    fieldset: RNG2CKSELR
  - name: DSICKSELR
    description: This register is used to control the selection of the kernel clock for the DSI block.
    byte_offset: 2340
    fieldset: DSICKSELR
  - name: ADCCKSELR
    description: This register is used to control the selection of the kernel clock for the ADC block.
    byte_offset: 2344
    fieldset: ADCCKSELR
  - name: LPTIM45CKSELR
    description: This register is used to control the selection of the kernel clock for the LPTIM4 and LPTIM5 blocks.
    byte_offset: 2348
    fieldset: LPTIM45CKSELR
  - name: LPTIM23CKSELR
    description: This register is used to control the selection of the kernel clock for the LPTIM2 and LPTIM3 blocks.
    byte_offset: 2352
    fieldset: LPTIM23CKSELR
  - name: LPTIM1CKSELR
    description: This register is used to control the selection of the kernel clock for the LPTIM1 block.
    byte_offset: 2356
    fieldset: LPTIM1CKSELR
  - name: APB1RSTSETR
    description: This register is used to activate the reset of the corresponding peripheral.
    byte_offset: 2432
    fieldset: APB1RSTSETR
  - name: APB1RSTCLRR
    description: This register is used to release the reset of the corresponding peripheral.
    byte_offset: 2436
    fieldset: APB1RSTCLRR
  - name: APB2RSTSETR
    description: This register is used to activate the reset of the corresponding peripheral.
    byte_offset: 2440
    fieldset: APB2RSTSETR
  - name: APB2RSTCLRR
    description: This register is used to release the reset of the corresponding peripheral.
    byte_offset: 2444
    fieldset: APB2RSTCLRR
  - name: APB3RSTSETR
    description: This register is used to activate the reset of the corresponding peripheral.
    byte_offset: 2448
    fieldset: APB3RSTSETR
  - name: APB3RSTCLRR
    description: This register is used to release the reset of the corresponding peripheral.
    byte_offset: 2452
    fieldset: APB3RSTCLRR
  - name: AHB2RSTSETR
    description: This register is used to activate the reset of the corresponding peripheral.
    byte_offset: 2456
    fieldset: AHB2RSTSETR
  - name: AHB2RSTCLRR
    description: This register is used to release the reset of the corresponding peripheral.
    byte_offset: 2460
    fieldset: AHB2RSTCLRR
  - name: AHB3RSTSETR
    description: This register is used to activate the reset of the corresponding peripheral.
    byte_offset: 2464
    fieldset: AHB3RSTSETR
  - name: AHB3RSTCLRR
    description: This register is used to release the reset of the corresponding peripheral.
    byte_offset: 2468
    fieldset: AHB3RSTCLRR
  - name: AHB4RSTSETR
    description: This register is used to activate the reset of the corresponding peripheral.
    byte_offset: 2472
    fieldset: AHB4RSTSETR
  - name: AHB4RSTCLRR
    description: This register is used to release the reset of the corresponding peripheral.
    byte_offset: 2476
    fieldset: AHB4RSTCLRR
  - name: MP_APB1ENSETR
    description: This register is used to set the peripheral clock enable bit.
    byte_offset: 2560
    fieldset: MP_APB1ENSETR
  - name: MP_APB1ENCLRR
    description: This register is used to clear the peripheral clock enable bit.
    byte_offset: 2564
    fieldset: MP_APB1ENCLRR
  - name: MP_APB2ENSETR
    description: This register is used to set the peripheral clock enable bit.
    byte_offset: 2568
    fieldset: MP_APB2ENSETR
  - name: MP_APB2ENCLRR
    description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
    byte_offset: 2572
    fieldset: MP_APB2ENCLRR
  - name: MP_APB3ENSETR
    description: This register is used to set the peripheral clock enable bit.
    byte_offset: 2576
    fieldset: MP_APB3ENSETR
  - name: MP_APB3ENCLRR
    description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
    byte_offset: 2580
    fieldset: MP_APB3ENCLRR
  - name: MP_AHB2ENSETR
    description: This register is used to set the peripheral clock enable bit of the corresponding peripheral.
    byte_offset: 2584
    fieldset: MP_AHB2ENSETR
  - name: MP_AHB2ENCLRR
    description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
    byte_offset: 2588
    fieldset: MP_AHB2ENCLRR
  - name: MP_AHB3ENSETR
    description: This register is used to set the peripheral clock enable bit of the corresponding peripheral.
    byte_offset: 2592
    fieldset: MP_AHB3ENSETR
  - name: MP_AHB3ENCLRR
    description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
    byte_offset: 2596
    fieldset: MP_AHB3ENCLRR
  - name: MP_AHB4ENSETR
    description: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU.
    byte_offset: 2600
    fieldset: MP_AHB4ENSETR
  - name: MP_AHB4ENCLRR
    description: This register is used to clear the peripheral clock enable bit.
    byte_offset: 2604
    fieldset: MP_AHB4ENCLRR
  - name: MP_MLAHBENSETR
    description: This register is used to set the peripheral clock enable bit.
    byte_offset: 2616
    fieldset: MP_MLAHBENSETR
  - name: MP_MLAHBENCLRR
    description: This register is used to clear the peripheral clock enable bit.
    byte_offset: 2620
    fieldset: MP_MLAHBENCLRR
  - name: MC_APB1ENSETR
    description: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return . Writing a sets the corresponding bit to.
    byte_offset: 2688
    fieldset: MC_APB1ENSETR
  - name: MC_APB1ENCLRR
    description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
    byte_offset: 2692
    fieldset: MC_APB1ENCLRR
  - name: MC_APB2ENSETR
    description: This register is used to set the peripheral clock enable bit.
    byte_offset: 2696
    fieldset: MC_APB2ENSETR
  - name: MC_APB2ENCLRR
    description: This register is used to clear the peripheral clock enable bit.
    byte_offset: 2700
    fieldset: MC_APB2ENCLRR
  - name: MC_APB3ENSETR
    description: This register is used to set the peripheral clock enable bit.
    byte_offset: 2704
    fieldset: MC_APB3ENSETR
  - name: MC_APB3ENCLRR
    description: This register is used to clear the peripheral clock enable bit.
    byte_offset: 2708
    fieldset: MC_APB3ENCLRR
  - name: MC_AHB2ENSETR
    description: This register is used to set the peripheral clock enable bit.
    byte_offset: 2712
    fieldset: MC_AHB2ENSETR
  - name: MC_AHB2ENCLRR
    description: This register is used to clear the peripheral clock enable bit.
    byte_offset: 2716
    fieldset: MC_AHB2ENCLRR
  - name: MC_AHB3ENSETR
    description: This register is used to set the peripheral clock enable bit.
    byte_offset: 2720
    fieldset: MC_AHB3ENSETR
  - name: MC_AHB3ENCLRR
    description: This register is used to clear the peripheral clock enable bit.
    byte_offset: 2724
    fieldset: MC_AHB3ENCLRR
  - name: MC_AHB4ENSETR
    description: This register is used to set the peripheral clock enable bit.
    byte_offset: 2728
    fieldset: MC_AHB4ENSETR
  - name: MC_AHB4ENCLRR
    description: This register is used to clear the peripheral clock enable bit.
    byte_offset: 2732
    fieldset: MC_AHB4ENCLRR
  - name: MC_AXIMENSETR
    description: This register is used to set the peripheral clock enable bit.
    byte_offset: 2736
    fieldset: MC_AXIMENSETR
  - name: MC_AXIMENCLRR
    description: This register is used to clear the peripheral clock enable bit.
    byte_offset: 2740
    fieldset: MC_AXIMENCLRR
  - name: MC_MLAHBENSETR
    description: This register is used to set the peripheral clock enable bit.
    byte_offset: 2744
    fieldset: MC_MLAHBENSETR
  - name: MC_MLAHBENCLRR
    description: This register is used to clear the peripheral clock enable bit.
    byte_offset: 2748
    fieldset: MC_MLAHBENCLRR
  - name: MP_APB1LPENSETR
    description: This register is used by the MCU in order to clear the PERxLPEN bits.
    byte_offset: 2816
    fieldset: MP_APB1LPENSETR
  - name: MP_APB1LPENCLRR
    description: This register is used by the MPU in order to clear the PERxLPEN bits.
    byte_offset: 2820
    fieldset: MP_APB1LPENCLRR
  - name: MP_APB2LPENSETR
    description: This register is used by the MCU in order to clear the PERxLPEN bits.
    byte_offset: 2824
    fieldset: MP_APB2LPENSETR
  - name: MP_APB2LPENCLRR
    description: This register is used by the MCU in order to clear the PERxLPEN bits.
    byte_offset: 2828
    fieldset: MP_APB2LPENCLRR
  - name: MP_APB3LPENSETR
    description: This register is used by the MCU in order to clear the PERxLPEN bits.
    byte_offset: 2832
    fieldset: MP_APB3LPENSETR
  - name: MP_APB3LPENCLRR
    description: This register is used by the MCU in order to clear the PERxLPEN bits.
    byte_offset: 2836
    fieldset: MP_APB3LPENCLRR
  - name: MP_AHB2LPENSETR
    description: This register is used by the MPU in order to set the PERxLPEN bit.
    byte_offset: 2840
    fieldset: MP_AHB2LPENSETR
  - name: MP_AHB2LPENCLRR
    description: This register is used by the MCU in order to clear the PERxLPEN bits.
    byte_offset: 2844
    fieldset: MP_AHB2LPENCLRR
  - name: MP_AHB3LPENSETR
    description: This register is used by the MPU.
    byte_offset: 2848
    fieldset: MP_AHB3LPENSETR
  - name: MP_AHB3LPENCLRR
    description: This register is used by the MPU in order to clear the PERxLPEN bit.
    byte_offset: 2852
    fieldset: MP_AHB3LPENCLRR
  - name: MP_AHB4LPENSETR
    description: This register is used by the MPU.
    byte_offset: 2856
    fieldset: MP_AHB4LPENSETR
  - name: MP_AHB4LPENCLRR
    description: This register is used by the MPU.
    byte_offset: 2860
    fieldset: MP_AHB4LPENCLRR
  - name: MP_AXIMLPENSETR
    description: This register is used by the MPU.
    byte_offset: 2864
    fieldset: MP_AXIMLPENSETR
  - name: MP_AXIMLPENCLRR
    description: This register is used by the MPU.
    byte_offset: 2868
    fieldset: MP_AXIMLPENCLRR
  - name: MP_MLAHBLPENSETR
    description: This register is used by the MPU in order to set the PERxLPEN bit.
    byte_offset: 2872
    fieldset: MP_MLAHBLPENSETR
  - name: MP_MLAHBLPENCLRR
    description: This register is used by the MPU in order to clear the PERxLPEN bit.
    byte_offset: 2876
    fieldset: MP_MLAHBLPENCLRR
  - name: MC_APB1LPENSETR
    description: This register is used by the MCU in order to set the PERxLPEN bit.
    byte_offset: 2944
    fieldset: MC_APB1LPENSETR
  - name: MC_APB1LPENCLRR
    description: This register is used by the MCU in order to clear the PERxLPEN bits.
    byte_offset: 2948
    fieldset: MC_APB1LPENCLRR
  - name: MC_APB2LPENSETR
    description: This register is used by the MCU in order to set the PERxLPEN bit.
    byte_offset: 2952
    fieldset: MC_APB2LPENSETR
  - name: MC_APB2LPENCLRR
    description: This register is used by the MCU in order to clear the PERxLPEN bit.
    byte_offset: 2956
    fieldset: MC_APB2LPENCLRR
  - name: MC_APB3LPENSETR
    description: This register is used by the MCU in order to set the PERxLPEN bit.
    byte_offset: 2960
    fieldset: MC_APB3LPENSETR
  - name: MC_APB3LPENCLRR
    description: This register is used by the MCU in order to clear the PERxLPEN bit.
    byte_offset: 2964
    fieldset: MC_APB3LPENCLRR
  - name: MC_AHB2LPENSETR
    description: This register is used by the MCU in order to set the PERxLPEN bit.
    byte_offset: 2968
    fieldset: MC_AHB2LPENSETR
  - name: MC_AHB2LPENCLRR
    description: This register is used by the MCU in order to clear the PERxLPEN bit.
    byte_offset: 2972
    fieldset: MC_AHB2LPENCLRR
  - name: MC_AHB3LPENSETR
    description: This register is used by the MCU in order to set the PERxLPEN bit.
    byte_offset: 2976
    fieldset: MC_AHB3LPENSETR
  - name: MC_AHB3LPENCLRR
    description: This register is used by the MCU in order to clear the PERxLPEN bit.
    byte_offset: 2980
    fieldset: MC_AHB3LPENCLRR
  - name: MC_AHB4LPENSETR
    description: This register is used by the MCU in order to set the PERxLPEN bit.
    byte_offset: 2984
    fieldset: MC_AHB4LPENSETR
  - name: MC_AHB4LPENCLRR
    description: This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral.
    byte_offset: 2988
    fieldset: MC_AHB4LPENCLRR
  - name: MC_AXIMLPENSETR
    description: This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral.
    byte_offset: 2992
    fieldset: MC_AXIMLPENSETR
  - name: MC_AXIMLPENCLRR
    description: This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral.
    byte_offset: 2996
    fieldset: MC_AXIMLPENCLRR
  - name: MC_MLAHBLPENSETR
    description: This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral.
    byte_offset: 3000
    fieldset: MC_MLAHBLPENSETR
  - name: MC_MLAHBLPENCLRR
    description: This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral.
    byte_offset: 3004
    fieldset: MC_MLAHBLPENCLRR
  - name: MC_RSTSCLRR
    description: This register is used by the MCU to check the reset source.
    byte_offset: 3072
    fieldset: MC_RSTSCLRR
  - name: MC_CIER
    description: 'This register shall be used by the MCU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details.'
    byte_offset: 3092
    fieldset: MC_CIER
  - name: MC_CIFR
    description: This register shall be used by the MCU in order to read and clear the interrupt flags.
    byte_offset: 3096
    fieldset: MC_CIFR
  - name: VERR
    description: This register gives the IP version.
    byte_offset: 4084
    access: Read
    fieldset: VERR
  - name: IDR
    description: This register gives the unique identifier of the RCC.
    byte_offset: 4088
    access: Read
    fieldset: IDR
  - name: SIDR
    description: This register gives the decoding space, which is for the RCC of 4 kB.
    byte_offset: 4092
    access: Read
    fieldset: SIDR
fieldset/ADCCKSELR:
  description: This register is used to control the selection of the kernel clock for the ADC block.
  fields:
  - name: ADCSRC
    description: ADCSRC.
    bit_offset: 0
    bit_size: 2
fieldset/AHB2RSTCLRR:
  description: This register is used to release the reset of the corresponding peripheral.
  fields:
  - name: DMA1RST
    description: DMA1RST.
    bit_offset: 0
    bit_size: 1
  - name: DMA2RST
    description: DMA2RST.
    bit_offset: 1
    bit_size: 1
  - name: DMAMUXRST
    description: DMAMUXRST.
    bit_offset: 2
    bit_size: 1
  - name: ADC12RST
    description: ADC12RST.
    bit_offset: 5
    bit_size: 1
  - name: USBORST
    description: USBORST.
    bit_offset: 8
    bit_size: 1
  - name: SDMMC3RST
    description: SDMMC3RST.
    bit_offset: 16
    bit_size: 1
fieldset/AHB2RSTSETR:
  description: This register is used to activate the reset of the corresponding peripheral.
  fields:
  - name: DMA1RST
    description: DMA1RST.
    bit_offset: 0
    bit_size: 1
  - name: DMA2RST
    description: DMA2RST.
    bit_offset: 1
    bit_size: 1
  - name: DMAMUXRST
    description: DMAMUXRST.
    bit_offset: 2
    bit_size: 1
  - name: ADC12RST
    description: ADC12RST.
    bit_offset: 5
    bit_size: 1
  - name: USBORST
    description: USBORST.
    bit_offset: 8
    bit_size: 1
  - name: SDMMC3RST
    description: SDMMC3RST.
    bit_offset: 16
    bit_size: 1
fieldset/AHB3RSTCLRR:
  description: This register is used to release the reset of the corresponding peripheral.
  fields:
  - name: DCMIRST
    description: DCMIRST.
    bit_offset: 0
    bit_size: 1
  - name: CRYP2RST
    description: CRYP2RST.
    bit_offset: 4
    bit_size: 1
  - name: HASH2RST
    description: HASH2RST.
    bit_offset: 5
    bit_size: 1
  - name: RNG2RST
    description: RNG2RST.
    bit_offset: 6
    bit_size: 1
  - name: CRC2RST
    description: CRC2RST.
    bit_offset: 7
    bit_size: 1
  - name: HSEMRST
    description: HSEMRST.
    bit_offset: 11
    bit_size: 1
  - name: IPCCRST
    description: IPCCRST.
    bit_offset: 12
    bit_size: 1
fieldset/AHB3RSTSETR:
  description: This register is used to activate the reset of the corresponding peripheral.
  fields:
  - name: DCMIRST
    description: DCMIRST.
    bit_offset: 0
    bit_size: 1
  - name: CRYP2RST
    description: CRYP2RST.
    bit_offset: 4
    bit_size: 1
  - name: HASH2RST
    description: HASH2RST.
    bit_offset: 5
    bit_size: 1
  - name: RNG2RST
    description: RNG2RST.
    bit_offset: 6
    bit_size: 1
  - name: CRC2RST
    description: CRC2RST.
    bit_offset: 7
    bit_size: 1
  - name: HSEMRST
    description: HSEMRST.
    bit_offset: 11
    bit_size: 1
  - name: IPCCRST
    description: IPCCRST.
    bit_offset: 12
    bit_size: 1
fieldset/AHB4RSTCLRR:
  description: This register is used to release the reset of the corresponding peripheral.
  fields:
  - name: GPIOARST
    description: GPIOARST.
    bit_offset: 0
    bit_size: 1
  - name: GPIOBRST
    description: GPIOBRST.
    bit_offset: 1
    bit_size: 1
  - name: GPIOCRST
    description: GPIOCRST.
    bit_offset: 2
    bit_size: 1
  - name: GPIODRST
    description: GPIODRST.
    bit_offset: 3
    bit_size: 1
  - name: GPIOERST
    description: GPIOERST.
    bit_offset: 4
    bit_size: 1
  - name: GPIOFRST
    description: GPIOFRST.
    bit_offset: 5
    bit_size: 1
  - name: GPIOGRST
    description: GPIOGRST.
    bit_offset: 6
    bit_size: 1
  - name: GPIOHRST
    description: GPIOHRST.
    bit_offset: 7
    bit_size: 1
  - name: GPIOIRST
    description: GPIOIRST.
    bit_offset: 8
    bit_size: 1
  - name: GPIOJRST
    description: GPIOJRST.
    bit_offset: 9
    bit_size: 1
  - name: GPIOKRST
    description: GPIOKRST.
    bit_offset: 10
    bit_size: 1
fieldset/AHB4RSTSETR:
  description: This register is used to activate the reset of the corresponding peripheral.
  fields:
  - name: GPIOARST
    description: GPIOARST.
    bit_offset: 0
    bit_size: 1
  - name: GPIOBRST
    description: GPIOBRST.
    bit_offset: 1
    bit_size: 1
  - name: GPIOCRST
    description: GPIOCRST.
    bit_offset: 2
    bit_size: 1
  - name: GPIODRST
    description: GPIODRST.
    bit_offset: 3
    bit_size: 1
  - name: GPIOERST
    description: GPIOERST.
    bit_offset: 4
    bit_size: 1
  - name: GPIOFRST
    description: GPIOFRST.
    bit_offset: 5
    bit_size: 1
  - name: GPIOGRST
    description: GPIOGRST.
    bit_offset: 6
    bit_size: 1
  - name: GPIOHRST
    description: GPIOHRST.
    bit_offset: 7
    bit_size: 1
  - name: GPIOIRST
    description: GPIOIRST.
    bit_offset: 8
    bit_size: 1
  - name: GPIOJRST
    description: GPIOJRST.
    bit_offset: 9
    bit_size: 1
  - name: GPIOKRST
    description: GPIOKRST.
    bit_offset: 10
    bit_size: 1
fieldset/AHB5RSTCLRR:
  description: This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: GPIOZRST
    description: GPIOZRST.
    bit_offset: 0
    bit_size: 1
  - name: CRYP1RST
    description: CRYP1RST.
    bit_offset: 4
    bit_size: 1
  - name: HASH1RST
    description: HASH1RST.
    bit_offset: 5
    bit_size: 1
  - name: RNG1RST
    description: RNG1RST.
    bit_offset: 6
    bit_size: 1
  - name: AXIMCRST
    description: AXIMCRST.
    bit_offset: 16
    bit_size: 1
fieldset/AHB5RSTSETR:
  description: This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: GPIOZRST
    description: GPIOZRST.
    bit_offset: 0
    bit_size: 1
  - name: CRYP1RST
    description: CRYP1RST.
    bit_offset: 4
    bit_size: 1
  - name: HASH1RST
    description: HASH1RST.
    bit_offset: 5
    bit_size: 1
  - name: RNG1RST
    description: RNG1RST.
    bit_offset: 6
    bit_size: 1
  - name: AXIMCRST
    description: AXIMCRST.
    bit_offset: 16
    bit_size: 1
fieldset/AHB6RSTCLRR:
  description: This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.
  fields:
  - name: ETHMACRST
    description: ETHMACRST.
    bit_offset: 10
    bit_size: 1
  - name: FMCRST
    description: FMCRST.
    bit_offset: 12
    bit_size: 1
  - name: QSPIRST
    description: QSPIRST.
    bit_offset: 14
    bit_size: 1
  - name: SDMMC1RST
    description: SDMMC1RST.
    bit_offset: 16
    bit_size: 1
  - name: SDMMC2RST
    description: SDMMC2RST.
    bit_offset: 17
    bit_size: 1
  - name: CRC1RST
    description: CRC1RST.
    bit_offset: 20
    bit_size: 1
  - name: USBHRST
    description: USBHRST.
    bit_offset: 24
    bit_size: 1
fieldset/AHB6RSTSETR:
  description: This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
  fields:
  - name: GPURST
    description: GPURST.
    bit_offset: 5
    bit_size: 1
  - name: ETHMACRST
    description: ETHMACRST.
    bit_offset: 10
    bit_size: 1
  - name: FMCRST
    description: FMCRST.
    bit_offset: 12
    bit_size: 1
  - name: QSPIRST
    description: QSPIRST.
    bit_offset: 14
    bit_size: 1
  - name: SDMMC1RST
    description: SDMMC1RST.
    bit_offset: 16
    bit_size: 1
  - name: SDMMC2RST
    description: SDMMC2RST.
    bit_offset: 17
    bit_size: 1
  - name: CRC1RST
    description: CRC1RST.
    bit_offset: 20
    bit_size: 1
  - name: USBHRST
    description: USBHRST.
    bit_offset: 24
    bit_size: 1
fieldset/APB1DIVR:
  description: 'This register is used to control the APB1 clock prescaler. Refer to section Section1.4.6.3: Sub-System Clock Generation for additional information.'
  fields:
  - name: APB1DIV
    description: APB1DIV.
    bit_offset: 0
    bit_size: 3
  - name: APB1DIVRDY
    description: APB1DIVRDY.
    bit_offset: 31
    bit_size: 1
fieldset/APB1RSTCLRR:
  description: This register is used to release the reset of the corresponding peripheral.
  fields:
  - name: TIM2RST
    description: TIM2RST.
    bit_offset: 0
    bit_size: 1
  - name: TIM3RST
    description: TIM3RST.
    bit_offset: 1
    bit_size: 1
  - name: TIM4RST
    description: TIM4RST.
    bit_offset: 2
    bit_size: 1
  - name: TIM5RST
    description: TIM5RST.
    bit_offset: 3
    bit_size: 1
  - name: TIM6RST
    description: TIM6RST.
    bit_offset: 4
    bit_size: 1
  - name: TIM7RST
    description: TIM7RST.
    bit_offset: 5
    bit_size: 1
  - name: TIM12RST
    description: TIM12RST.
    bit_offset: 6
    bit_size: 1
  - name: TIM13RST
    description: TIM13RST.
    bit_offset: 7
    bit_size: 1
  - name: TIM14RST
    description: TIM14RST.
    bit_offset: 8
    bit_size: 1
  - name: LPTIM1RST
    description: LPTIM1RST.
    bit_offset: 9
    bit_size: 1
  - name: SPI2RST
    description: SPI2RST.
    bit_offset: 11
    bit_size: 1
  - name: SPI3RST
    description: SPI3RST.
    bit_offset: 12
    bit_size: 1
  - name: USART2RST
    description: USART2RST.
    bit_offset: 14
    bit_size: 1
  - name: USART3RST
    description: USART3RST.
    bit_offset: 15
    bit_size: 1
  - name: UART4RST
    description: UART4RST.
    bit_offset: 16
    bit_size: 1
  - name: UART5RST
    description: UART5RST.
    bit_offset: 17
    bit_size: 1
  - name: UART7RST
    description: UART7RST.
    bit_offset: 18
    bit_size: 1
  - name: UART8RST
    description: UART8RST.
    bit_offset: 19
    bit_size: 1
  - name: I2C1RST
    description: I2C1RST.
    bit_offset: 21
    bit_size: 1
  - name: I2C2RST
    description: I2C2RST.
    bit_offset: 22
    bit_size: 1
  - name: I2C3RST
    description: I2C3RST.
    bit_offset: 23
    bit_size: 1
  - name: I2C5RST
    description: I2C5RST.
    bit_offset: 24
    bit_size: 1
  - name: SPDIFRST
    description: SPDIFRST.
    bit_offset: 26
    bit_size: 1
  - name: CECRST
    description: CECRST.
    bit_offset: 27
    bit_size: 1
  - name: DAC12RST
    description: DAC12RST.
    bit_offset: 29
    bit_size: 1
  - name: MDIOSRST
    description: MDIOSRST.
    bit_offset: 31
    bit_size: 1
fieldset/APB1RSTSETR:
  description: This register is used to activate the reset of the corresponding peripheral.
  fields:
  - name: TIM2RST
    description: TIM2RST.
    bit_offset: 0
    bit_size: 1
  - name: TIM3RST
    description: TIM3RST.
    bit_offset: 1
    bit_size: 1
  - name: TIM4RST
    description: TIM4RST.
    bit_offset: 2
    bit_size: 1
  - name: TIM5RST
    description: TIM5RST.
    bit_offset: 3
    bit_size: 1
  - name: TIM6RST
    description: TIM6RST.
    bit_offset: 4
    bit_size: 1
  - name: TIM7RST
    description: TIM7RST.
    bit_offset: 5
    bit_size: 1
  - name: TIM12RST
    description: TIM12RST.
    bit_offset: 6
    bit_size: 1
  - name: TIM13RST
    description: TIM13RST.
    bit_offset: 7
    bit_size: 1
  - name: TIM14RST
    description: TIM14RST.
    bit_offset: 8
    bit_size: 1
  - name: LPTIM1RST
    description: LPTIM1RST.
    bit_offset: 9
    bit_size: 1
  - name: SPI2RST
    description: SPI2RST.
    bit_offset: 11
    bit_size: 1
  - name: SPI3RST
    description: SPI3RST.
    bit_offset: 12
    bit_size: 1
  - name: USART2RST
    description: USART2RST.
    bit_offset: 14
    bit_size: 1
  - name: USART3RST
    description: USART3RST.
    bit_offset: 15
    bit_size: 1
  - name: UART4RST
    description: UART4RST.
    bit_offset: 16
    bit_size: 1
  - name: UART5RST
    description: UART5RST.
    bit_offset: 17
    bit_size: 1
  - name: UART7RST
    description: UART7RST.
    bit_offset: 18
    bit_size: 1
  - name: UART8RST
    description: UART8RST.
    bit_offset: 19
    bit_size: 1
  - name: I2C1RST
    description: I2C1RST.
    bit_offset: 21
    bit_size: 1
  - name: I2C2RST
    description: I2C2RST.
    bit_offset: 22
    bit_size: 1
  - name: I2C3RST
    description: I2C3RST.
    bit_offset: 23
    bit_size: 1
  - name: I2C5RST
    description: I2C5RST.
    bit_offset: 24
    bit_size: 1
  - name: SPDIFRST
    description: SPDIFRST.
    bit_offset: 26
    bit_size: 1
  - name: CECRST
    description: CECRST.
    bit_offset: 27
    bit_size: 1
  - name: DAC12RST
    description: DAC12RST.
    bit_offset: 29
    bit_size: 1
  - name: MDIOSRST
    description: MDIOSRST.
    bit_offset: 31
    bit_size: 1
fieldset/APB2DIVR:
  description: 'This register is used to control the APB2 clock prescaler. Refer to Section: Sub-system clock generation for additional information.'
  fields:
  - name: APB2DIV
    description: APB2DIV.
    bit_offset: 0
    bit_size: 3
  - name: APB2DIVRDY
    description: APB2DIVRDY.
    bit_offset: 31
    bit_size: 1
fieldset/APB2RSTCLRR:
  description: This register is used to release the reset of the corresponding peripheral.
  fields:
  - name: TIM1RST
    description: TIM1RST.
    bit_offset: 0
    bit_size: 1
  - name: TIM8RST
    description: TIM8RST.
    bit_offset: 1
    bit_size: 1
  - name: TIM15RST
    description: TIM15RST.
    bit_offset: 2
    bit_size: 1
  - name: TIM16RST
    description: TIM16RST.
    bit_offset: 3
    bit_size: 1
  - name: TIM17RST
    description: TIM17RST.
    bit_offset: 4
    bit_size: 1
  - name: SPI1RST
    description: SPI1RST.
    bit_offset: 8
    bit_size: 1
  - name: SPI4RST
    description: SPI4RST.
    bit_offset: 9
    bit_size: 1
  - name: SPI5RST
    description: SPI5RST.
    bit_offset: 10
    bit_size: 1
  - name: USART6RST
    description: USART6RST.
    bit_offset: 13
    bit_size: 1
  - name: SAI1RST
    description: SAI1RST.
    bit_offset: 16
    bit_size: 1
  - name: SAI2RST
    description: SAI2RST.
    bit_offset: 17
    bit_size: 1
  - name: SAI3RST
    description: SAI3RST.
    bit_offset: 18
    bit_size: 1
  - name: DFSDMRST
    description: DFSDMRST.
    bit_offset: 20
    bit_size: 1
  - name: FDCANRST
    description: FDCANRST.
    bit_offset: 24
    bit_size: 1
fieldset/APB2RSTSETR:
  description: This register is used to activate the reset of the corresponding peripheral.
  fields:
  - name: TIM1RST
    description: TIM1RST.
    bit_offset: 0
    bit_size: 1
  - name: TIM8RST
    description: TIM8RST.
    bit_offset: 1
    bit_size: 1
  - name: TIM15RST
    description: TIM15RST.
    bit_offset: 2
    bit_size: 1
  - name: TIM16RST
    description: TIM16RST.
    bit_offset: 3
    bit_size: 1
  - name: TIM17RST
    description: TIM17RST.
    bit_offset: 4
    bit_size: 1
  - name: SPI1RST
    description: SPI1RST.
    bit_offset: 8
    bit_size: 1
  - name: SPI4RST
    description: SPI4RST.
    bit_offset: 9
    bit_size: 1
  - name: SPI5RST
    description: SPI5RST.
    bit_offset: 10
    bit_size: 1
  - name: USART6RST
    description: USART6RST.
    bit_offset: 13
    bit_size: 1
  - name: SAI1RST
    description: SAI1RST.
    bit_offset: 16
    bit_size: 1
  - name: SAI2RST
    description: SAI2RST.
    bit_offset: 17
    bit_size: 1
  - name: SAI3RST
    description: SAI3RST.
    bit_offset: 18
    bit_size: 1
  - name: DFSDMRST
    description: DFSDMRST.
    bit_offset: 20
    bit_size: 1
  - name: FDCANRST
    description: FDCANRST.
    bit_offset: 24
    bit_size: 1
fieldset/APB3DIVR:
  description: 'This register is used to control the APB3 clock prescaler. Refer to Section: Sub-system clock generation for additional information.'
  fields:
  - name: APB3DIV
    description: APB3DIV.
    bit_offset: 0
    bit_size: 3
  - name: APB3DIVRDY
    description: APB3DIVRDY.
    bit_offset: 31
    bit_size: 1
fieldset/APB3RSTCLRR:
  description: This register is used to release the reset of the corresponding peripheral.
  fields:
  - name: LPTIM2RST
    description: LPTIM2RST.
    bit_offset: 0
    bit_size: 1
  - name: LPTIM3RST
    description: LPTIM3RST.
    bit_offset: 1
    bit_size: 1
  - name: LPTIM4RST
    description: LPTIM4RST.
    bit_offset: 2
    bit_size: 1
  - name: LPTIM5RST
    description: LPTIM5RST.
    bit_offset: 3
    bit_size: 1
  - name: SAI4RST
    description: SAI4RST.
    bit_offset: 8
    bit_size: 1
  - name: SYSCFGRST
    description: SYSCFGRST.
    bit_offset: 11
    bit_size: 1
  - name: VREFRST
    description: VREFRST.
    bit_offset: 13
    bit_size: 1
  - name: DTSRST
    description: DTSRST.
    bit_offset: 16
    bit_size: 1
fieldset/APB3RSTSETR:
  description: This register is used to activate the reset of the corresponding peripheral.
  fields:
  - name: LPTIM2RST
    description: LPTIM2RST.
    bit_offset: 0
    bit_size: 1
  - name: LPTIM3RST
    description: LPTIM3RST.
    bit_offset: 1
    bit_size: 1
  - name: LPTIM4RST
    description: LPTIM4RST.
    bit_offset: 2
    bit_size: 1
  - name: LPTIM5RST
    description: LPTIM5RST.
    bit_offset: 3
    bit_size: 1
  - name: SAI4RST
    description: SAI4RST.
    bit_offset: 8
    bit_size: 1
  - name: SYSCFGRST
    description: SYSCFGRST.
    bit_offset: 11
    bit_size: 1
  - name: VREFRST
    description: VREFRST.
    bit_offset: 13
    bit_size: 1
  - name: DTSRST
    description: DTSRST.
    bit_offset: 16
    bit_size: 1
fieldset/APB4DIVR:
  description: 'This register is used to control the APB4 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.'
  fields:
  - name: APB4DIV
    description: APB4DIV.
    bit_offset: 0
    bit_size: 3
  - name: APB4DIVRDY
    description: APB4DIVRDY.
    bit_offset: 31
    bit_size: 1
fieldset/APB4RSTCLRR:
  description: This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.
  fields:
  - name: LTDCRST
    description: LTDCRST.
    bit_offset: 0
    bit_size: 1
  - name: DSIRST
    description: DSIRST.
    bit_offset: 4
    bit_size: 1
  - name: DDRPERFMRST
    description: DDRPERFMRST.
    bit_offset: 8
    bit_size: 1
  - name: USBPHYRST
    description: USBPHYRST.
    bit_offset: 16
    bit_size: 1
fieldset/APB4RSTSETR:
  description: This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
  fields:
  - name: LTDCRST
    description: LTDCRST.
    bit_offset: 0
    bit_size: 1
  - name: DSIRST
    description: DSIRST.
    bit_offset: 4
    bit_size: 1
  - name: DDRPERFMRST
    description: DDRPERFMRST.
    bit_offset: 8
    bit_size: 1
  - name: USBPHYRST
    description: USBPHYRST.
    bit_offset: 16
    bit_size: 1
fieldset/APB5DIVR:
  description: 'This register is used to control the APB5 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.'
  fields:
  - name: APB5DIV
    description: APB5DIV.
    bit_offset: 0
    bit_size: 3
  - name: APB5DIVRDY
    description: APB5DIVRDY.
    bit_offset: 31
    bit_size: 1
fieldset/APB5RSTCLRR:
  description: This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: SPI6RST
    description: SPI6RST.
    bit_offset: 0
    bit_size: 1
  - name: I2C4RST
    description: I2C4RST.
    bit_offset: 2
    bit_size: 1
  - name: I2C6RST
    description: I2C6RST.
    bit_offset: 3
    bit_size: 1
  - name: USART1RST
    description: USART1RST.
    bit_offset: 4
    bit_size: 1
  - name: STGENRST
    description: STGENRST.
    bit_offset: 20
    bit_size: 1
fieldset/APB5RSTSETR:
  description: This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: SPI6RST
    description: SPI6RST.
    bit_offset: 0
    bit_size: 1
  - name: I2C4RST
    description: I2C4RST.
    bit_offset: 2
    bit_size: 1
  - name: I2C6RST
    description: I2C6RST.
    bit_offset: 3
    bit_size: 1
  - name: USART1RST
    description: USART1RST.
    bit_offset: 4
    bit_size: 1
  - name: STGENRST
    description: STGENRST.
    bit_offset: 20
    bit_size: 1
fieldset/ASSCKSELR:
  description: 'This register is used to select the clock source for the AXI sub-system. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
  fields:
  - name: AXISSRC
    description: AXISSRC.
    bit_offset: 0
    bit_size: 3
  - name: AXISSRCRDY
    description: AXISSRCRDY.
    bit_offset: 31
    bit_size: 1
fieldset/AXIDIVR:
  description: 'This register is used to control the AXI Matrix clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.'
  fields:
  - name: AXIDIV
    description: AXIDIV.
    bit_offset: 0
    bit_size: 3
  - name: AXIDIVRDY
    description: AXIDIVRDY.
    bit_offset: 31
    bit_size: 1
fieldset/BDCR:
  description: 'This register is used to control the LSE function. Wait states are inserted in case of successive write accesses to this register. The number of wait states may be up to 7 cycles of AHB4 clock.After a system reset, the register RCC_BDCR is write-protected. In order to modify this register, the DBP bit in the PWR control register 1 (PWR_CR1) has to be set to . Bits of RCC_BDCR register are only reset after a backup domain reset: nreset_vsw (see Section10.3.6: Backup domain reset). Any other internal or external reset will not have any effect on these bits.This register is located into the VSW domain. If TZEN = , this register can only be modified in secure mode.'
  fields:
  - name: LSEON
    description: LSEON.
    bit_offset: 0
    bit_size: 1
  - name: LSEBYP
    description: LSEBYP.
    bit_offset: 1
    bit_size: 1
  - name: LSERDY
    description: LSERDY.
    bit_offset: 2
    bit_size: 1
  - name: DIGBYP
    description: DIGBYP.
    bit_offset: 3
    bit_size: 1
  - name: LSEDRV
    description: LSEDRV.
    bit_offset: 4
    bit_size: 2
  - name: LSECSSON
    description: LSECSSON.
    bit_offset: 8
    bit_size: 1
  - name: LSECSSD
    description: LSECSSD.
    bit_offset: 9
    bit_size: 1
  - name: RTCSRC
    description: RTCSRC.
    bit_offset: 16
    bit_size: 2
  - name: RTCCKEN
    description: RTCCKEN.
    bit_offset: 20
    bit_size: 1
  - name: VSWRST
    description: VSWRST.
    bit_offset: 31
    bit_size: 1
fieldset/BR_RSTSCLRR:
  description: 'This register is used by the BOOTROM to check the reset source. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). Refer to Section10.3.13: Reset source identification for details.This register except MPUP[1:0]RSTF flags is located into VDD domain, and is reset by por_rst reset. The MPUP[1:0]RSTF flags are located into VDDCORE and are reset by nreset. If TZEN = , this register can only be modified in secure mode.'
  fields:
  - name: PORRSTF
    description: PORRSTF.
    bit_offset: 0
    bit_size: 1
  - name: BORRSTF
    description: BORRSTF.
    bit_offset: 1
    bit_size: 1
  - name: PADRSTF
    description: PADRSTF.
    bit_offset: 2
    bit_size: 1
  - name: HCSSRSTF
    description: HCSSRSTF.
    bit_offset: 3
    bit_size: 1
  - name: VCORERSTF
    description: VCORERSTF.
    bit_offset: 4
    bit_size: 1
  - name: MPSYSRSTF
    description: MPSYSRSTF.
    bit_offset: 6
    bit_size: 1
  - name: MCSYSRSTF
    description: MCSYSRSTF.
    bit_offset: 7
    bit_size: 1
  - name: IWDG1RSTF
    description: IWDG1RSTF.
    bit_offset: 8
    bit_size: 1
  - name: IWDG2RSTF
    description: IWDG2RSTF.
    bit_offset: 9
    bit_size: 1
  - name: MPUP0RSTF
    description: MPUP0RSTF.
    bit_offset: 13
    bit_size: 1
  - name: MPUP1RSTF
    description: MPUP1RSTF.
    bit_offset: 14
    bit_size: 1
fieldset/CECCKSELR:
  description: This register is used to control the selection of the kernel clock for the CEC-HDMI.
  fields:
  - name: CECSRC
    description: CECSRC.
    bit_offset: 0
    bit_size: 2
fieldset/CPERCKSELR:
  description: 'This register is used to select an oscillator source as kernel clock for the per_ck clock. The per_ck clock is distributed to several peripherals. Refer to Section: Clock enabling delays.'
  fields:
  - name: CKPERSRC
    description: CKPERSRC.
    bit_offset: 0
    bit_size: 2
fieldset/CSICFGR:
  description: This register is used to fine-tune the CSI frequency. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See The clock restore sequence description for details.
  fields:
  - name: CSITRIM
    description: CSITRIM.
    bit_offset: 8
    bit_size: 5
  - name: CSICAL
    description: CSICAL.
    bit_offset: 16
    bit_size: 8
fieldset/DBGCFGR:
  description: This is register contains the enable control of the debug and trace function, and the clock divider for the trace function.
  fields:
  - name: TRACEDIV
    description: TRACEDIV.
    bit_offset: 0
    bit_size: 3
  - name: DBGCKEN
    description: DBGCKEN.
    bit_offset: 8
    bit_size: 1
  - name: TRACECKEN
    description: TRACECKEN.
    bit_offset: 9
    bit_size: 1
  - name: DBGRST
    description: DBGRST.
    bit_offset: 12
    bit_size: 1
fieldset/DDRITFCR:
  description: This register is used to control the DDR interface, including the DDRC and DDRPHYC. If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: DDRC1EN
    description: DDRC1EN.
    bit_offset: 0
    bit_size: 1
  - name: DDRC1LPEN
    description: DDRC1LPEN.
    bit_offset: 1
    bit_size: 1
  - name: DDRC2EN
    description: DDRC2EN.
    bit_offset: 2
    bit_size: 1
  - name: DDRC2LPEN
    description: DDRC2LPEN.
    bit_offset: 3
    bit_size: 1
  - name: DDRPHYCEN
    description: DDRPHYCEN.
    bit_offset: 4
    bit_size: 1
  - name: DDRPHYCLPEN
    description: DDRPHYCLPEN.
    bit_offset: 5
    bit_size: 1
  - name: DDRCAPBEN
    description: DDRCAPBEN.
    bit_offset: 6
    bit_size: 1
  - name: DDRCAPBLPEN
    description: DDRCAPBLPEN.
    bit_offset: 7
    bit_size: 1
  - name: AXIDCGEN
    description: AXIDCGEN.
    bit_offset: 8
    bit_size: 1
  - name: DDRPHYCAPBEN
    description: DDRPHYCAPBEN.
    bit_offset: 9
    bit_size: 1
  - name: DDRPHYCAPBLPEN
    description: DDRPHYCAPBLPEN.
    bit_offset: 10
    bit_size: 1
  - name: KERDCG_DLY
    description: KERDCG_DLY.
    bit_offset: 11
    bit_size: 3
  - name: DDRCAPBRST
    description: DDRCAPBRST.
    bit_offset: 14
    bit_size: 1
  - name: DDRCAXIRST
    description: DDRCAXIRST.
    bit_offset: 15
    bit_size: 1
  - name: DDRCORERST
    description: DDRCORERST.
    bit_offset: 16
    bit_size: 1
  - name: DPHYAPBRST
    description: DPHYAPBRST.
    bit_offset: 17
    bit_size: 1
  - name: DPHYRST
    description: DPHYRST.
    bit_offset: 18
    bit_size: 1
  - name: DPHYCTLRST
    description: DPHYCTLRST.
    bit_offset: 19
    bit_size: 1
  - name: DDRCKMOD
    description: DDRCKMOD.
    bit_offset: 20
    bit_size: 3
  - name: GSKPMOD
    description: GSKPMOD.
    bit_offset: 23
    bit_size: 1
  - name: GSKPCTRL
    description: GSKPCTRL.
    bit_offset: 24
    bit_size: 1
  - name: DFILP_WIDTH
    description: DFILP_WIDTH.
    bit_offset: 25
    bit_size: 3
  - name: GSKP_DUR
    description: GSKP_DUR.
    bit_offset: 28
    bit_size: 4
fieldset/DSICKSELR:
  description: This register is used to control the selection of the kernel clock for the DSI block.
  fields:
  - name: DSISRC
    description: DSISRC.
    bit_offset: 0
    bit_size: 1
fieldset/ETHCKSELR:
  description: 'This register is used to control the selection of the kernel clock for the ETH block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: ETHSRC
    description: ETHSRC.
    bit_offset: 0
    bit_size: 2
  - name: ETHPTPDIV
    description: ETHPTPDIV.
    bit_offset: 4
    bit_size: 4
fieldset/FDCANCKSELR:
  description: 'This register is used to control the selection of the kernel clock for the FDCAN block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: FDCANSRC
    description: FDCANSRC.
    bit_offset: 0
    bit_size: 2
fieldset/FMCCKSELR:
  description: 'This register is used to control the selection of the kernel clock for the FMC block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: FMCSRC
    description: FMCSRC.
    bit_offset: 0
    bit_size: 2
fieldset/HSICFGR:
  description: 'This register is used to configure the HSI. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
  fields:
  - name: HSIDIV
    description: HSIDIV.
    bit_offset: 0
    bit_size: 2
  - name: HSITRIM
    description: HSITRIM.
    bit_offset: 8
    bit_size: 7
  - name: HSICAL
    description: HSICAL.
    bit_offset: 16
    bit_size: 12
fieldset/I2C12CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the I2C1 and I2C2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: I2C12SRC
    description: I2C12SRC.
    bit_offset: 0
    bit_size: 3
fieldset/I2C35CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the I2C3 and I2C5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: I2C35SRC
    description: I2C35SRC.
    bit_offset: 0
    bit_size: 3
fieldset/I2C46CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the I2C4 and I2C6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.'
  fields:
  - name: I2C46SRC
    description: I2C46SRC.
    bit_offset: 0
    bit_size: 3
fieldset/IDR:
  description: This register gives the unique identifier of the RCC.
  fields:
  - name: ID
    description: ID.
    bit_offset: 0
    bit_size: 32
fieldset/LPTIM1CKSELR:
  description: This register is used to control the selection of the kernel clock for the LPTIM1 block.
  fields:
  - name: LPTIM1SRC
    description: LPTIM1SRC.
    bit_offset: 0
    bit_size: 3
fieldset/LPTIM23CKSELR:
  description: This register is used to control the selection of the kernel clock for the LPTIM2 and LPTIM3 blocks.
  fields:
  - name: LPTIM23SRC
    description: LPTIM23SRC.
    bit_offset: 0
    bit_size: 3
fieldset/LPTIM45CKSELR:
  description: This register is used to control the selection of the kernel clock for the LPTIM4 and LPTIM5 blocks.
  fields:
  - name: LPTIM45SRC
    description: LPTIM45SRC.
    bit_offset: 0
    bit_size: 3
fieldset/MCO1CFGR:
  description: This register is used to select the clock generated on MCO1 output.
  fields:
  - name: MCO1SEL
    description: MCO1SEL.
    bit_offset: 0
    bit_size: 3
  - name: MCO1DIV
    description: MCO1DIV.
    bit_offset: 4
    bit_size: 4
  - name: MCO1ON
    description: MCO1ON.
    bit_offset: 12
    bit_size: 1
fieldset/MCO2CFGR:
  description: This register is used to select the clock generated on MCO2 output.
  fields:
  - name: MCO2SEL
    description: MCO2SEL.
    bit_offset: 0
    bit_size: 3
  - name: MCO2DIV
    description: MCO2DIV.
    bit_offset: 4
    bit_size: 4
  - name: MCO2ON
    description: MCO2ON.
    bit_offset: 12
    bit_size: 1
fieldset/MCUDIVR:
  description: 'This register is used to control the MCU sub-system clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.'
  fields:
  - name: MCUDIV
    description: MCUDIV.
    bit_offset: 0
    bit_size: 4
  - name: MCUDIVRDY
    description: MCUDIVRDY.
    bit_offset: 31
    bit_size: 1
fieldset/MC_AHB2ENCLRR:
  description: This register is used to clear the peripheral clock enable bit.
  fields:
  - name: DMA1EN
    description: DMA1EN.
    bit_offset: 0
    bit_size: 1
  - name: DMA2EN
    description: DMA2EN.
    bit_offset: 1
    bit_size: 1
  - name: DMAMUXEN
    description: DMAMUXEN.
    bit_offset: 2
    bit_size: 1
  - name: ADC12EN
    description: ADC12EN.
    bit_offset: 5
    bit_size: 1
  - name: USBOEN
    description: USBOEN.
    bit_offset: 8
    bit_size: 1
  - name: SDMMC3EN
    description: SDMMC3EN.
    bit_offset: 16
    bit_size: 1
fieldset/MC_AHB2ENSETR:
  description: This register is used to set the peripheral clock enable bit.
  fields:
  - name: DMA1EN
    description: DMA1EN.
    bit_offset: 0
    bit_size: 1
  - name: DMA2EN
    description: DMA2EN.
    bit_offset: 1
    bit_size: 1
  - name: DMAMUXEN
    description: DMAMUXEN.
    bit_offset: 2
    bit_size: 1
  - name: ADC12EN
    description: ADC12EN.
    bit_offset: 5
    bit_size: 1
  - name: USBOEN
    description: USBOEN.
    bit_offset: 8
    bit_size: 1
  - name: SDMMC3EN
    description: SDMMC3EN.
    bit_offset: 16
    bit_size: 1
fieldset/MC_AHB2LPENCLRR:
  description: This register is used by the MCU in order to clear the PERxLPEN bit.
  fields:
  - name: DMA1LPEN
    description: DMA1LPEN.
    bit_offset: 0
    bit_size: 1
  - name: DMA2LPEN
    description: DMA2LPEN.
    bit_offset: 1
    bit_size: 1
  - name: DMAMUXLPEN
    description: DMAMUXLPEN.
    bit_offset: 2
    bit_size: 1
  - name: ADC12LPEN
    description: ADC12LPEN.
    bit_offset: 5
    bit_size: 1
  - name: USBOLPEN
    description: USBOLPEN.
    bit_offset: 8
    bit_size: 1
  - name: SDMMC3LPEN
    description: SDMMC3LPEN.
    bit_offset: 16
    bit_size: 1
fieldset/MC_AHB2LPENSETR:
  description: This register is used by the MCU in order to set the PERxLPEN bit.
  fields:
  - name: DMA1LPEN
    description: DMA1LPEN.
    bit_offset: 0
    bit_size: 1
  - name: DMA2LPEN
    description: DMA2LPEN.
    bit_offset: 1
    bit_size: 1
  - name: DMAMUXLPEN
    description: DMAMUXLPEN.
    bit_offset: 2
    bit_size: 1
  - name: ADC12LPEN
    description: ADC12LPEN.
    bit_offset: 5
    bit_size: 1
  - name: USBOLPEN
    description: USBOLPEN.
    bit_offset: 8
    bit_size: 1
  - name: SDMMC3LPEN
    description: SDMMC3LPEN.
    bit_offset: 16
    bit_size: 1
fieldset/MC_AHB3ENCLRR:
  description: This register is used to clear the peripheral clock enable bit.
  fields:
  - name: DCMIEN
    description: DCMIEN.
    bit_offset: 0
    bit_size: 1
  - name: CRYP2EN
    description: CRYP2EN.
    bit_offset: 4
    bit_size: 1
  - name: HASH2EN
    description: HASH2EN.
    bit_offset: 5
    bit_size: 1
  - name: RNG2EN
    description: RNG2EN.
    bit_offset: 6
    bit_size: 1
  - name: CRC2EN
    description: CRC2EN.
    bit_offset: 7
    bit_size: 1
  - name: HSEMEN
    description: HSEMEN.
    bit_offset: 11
    bit_size: 1
  - name: IPCCEN
    description: IPCCEN.
    bit_offset: 12
    bit_size: 1
fieldset/MC_AHB3ENSETR:
  description: This register is used to set the peripheral clock enable bit.
  fields:
  - name: DCMIEN
    description: DCMIEN.
    bit_offset: 0
    bit_size: 1
  - name: CRYP2EN
    description: CRYP2EN.
    bit_offset: 4
    bit_size: 1
  - name: HASH2EN
    description: HASH2EN.
    bit_offset: 5
    bit_size: 1
  - name: RNG2EN
    description: RNG2EN.
    bit_offset: 6
    bit_size: 1
  - name: CRC2EN
    description: CRC2EN.
    bit_offset: 7
    bit_size: 1
  - name: HSEMEN
    description: HSEMEN.
    bit_offset: 11
    bit_size: 1
  - name: IPCCEN
    description: IPCCEN.
    bit_offset: 12
    bit_size: 1
fieldset/MC_AHB3LPENCLRR:
  description: This register is used by the MCU in order to clear the PERxLPEN bit.
  fields:
  - name: DCMILPEN
    description: DCMILPEN.
    bit_offset: 0
    bit_size: 1
  - name: CRYP2LPEN
    description: CRYP2LPEN.
    bit_offset: 4
    bit_size: 1
  - name: HASH2LPEN
    description: HASH2LPEN.
    bit_offset: 5
    bit_size: 1
  - name: RNG2LPEN
    description: RNG2LPEN.
    bit_offset: 6
    bit_size: 1
  - name: CRC2LPEN
    description: CRC2LPEN.
    bit_offset: 7
    bit_size: 1
  - name: HSEMLPEN
    description: HSEMLPEN.
    bit_offset: 11
    bit_size: 1
  - name: IPCCLPEN
    description: IPCCLPEN.
    bit_offset: 12
    bit_size: 1
fieldset/MC_AHB3LPENSETR:
  description: This register is used by the MCU in order to set the PERxLPEN bit.
  fields:
  - name: DCMILPEN
    description: DCMILPEN.
    bit_offset: 0
    bit_size: 1
  - name: CRYP2LPEN
    description: CRYP2LPEN.
    bit_offset: 4
    bit_size: 1
  - name: HASH2LPEN
    description: HASH2LPEN.
    bit_offset: 5
    bit_size: 1
  - name: RNG2LPEN
    description: RNG2LPEN.
    bit_offset: 6
    bit_size: 1
  - name: CRC2LPEN
    description: CRC2LPEN.
    bit_offset: 7
    bit_size: 1
  - name: HSEMLPEN
    description: HSEMLPEN.
    bit_offset: 11
    bit_size: 1
  - name: IPCCLPEN
    description: IPCCLPEN.
    bit_offset: 12
    bit_size: 1
fieldset/MC_AHB4ENCLRR:
  description: This register is used to clear the peripheral clock enable bit.
  fields:
  - name: GPIOAEN
    description: GPIOAEN.
    bit_offset: 0
    bit_size: 1
  - name: GPIOBEN
    description: GPIOBEN.
    bit_offset: 1
    bit_size: 1
  - name: GPIOCEN
    description: GPIOCEN.
    bit_offset: 2
    bit_size: 1
  - name: GPIODEN
    description: GPIODEN.
    bit_offset: 3
    bit_size: 1
  - name: GPIOEEN
    description: GPIOEEN.
    bit_offset: 4
    bit_size: 1
  - name: GPIOFEN
    description: GPIOFEN.
    bit_offset: 5
    bit_size: 1
  - name: GPIOGEN
    description: GPIOGEN.
    bit_offset: 6
    bit_size: 1
  - name: GPIOHEN
    description: GPIOHEN.
    bit_offset: 7
    bit_size: 1
  - name: GPIOIEN
    description: GPIOIEN.
    bit_offset: 8
    bit_size: 1
  - name: GPIOJEN
    description: GPIOJEN.
    bit_offset: 9
    bit_size: 1
  - name: GPIOKEN
    description: GPIOKEN.
    bit_offset: 10
    bit_size: 1
fieldset/MC_AHB4ENSETR:
  description: This register is used to set the peripheral clock enable bit.
  fields:
  - name: GPIOAEN
    description: GPIOAEN.
    bit_offset: 0
    bit_size: 1
  - name: GPIOBEN
    description: GPIOBEN.
    bit_offset: 1
    bit_size: 1
  - name: GPIOCEN
    description: GPIOCEN.
    bit_offset: 2
    bit_size: 1
  - name: GPIODEN
    description: GPIODEN.
    bit_offset: 3
    bit_size: 1
  - name: GPIOEEN
    description: GPIOEEN.
    bit_offset: 4
    bit_size: 1
  - name: GPIOFEN
    description: GPIOFEN.
    bit_offset: 5
    bit_size: 1
  - name: GPIOGEN
    description: GPIOGEN.
    bit_offset: 6
    bit_size: 1
  - name: GPIOHEN
    description: GPIOHEN.
    bit_offset: 7
    bit_size: 1
  - name: GPIOIEN
    description: GPIOIEN.
    bit_offset: 8
    bit_size: 1
  - name: GPIOJEN
    description: GPIOJEN.
    bit_offset: 9
    bit_size: 1
  - name: GPIOKEN
    description: GPIOKEN.
    bit_offset: 10
    bit_size: 1
fieldset/MC_AHB4LPENCLRR:
  description: This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral.
  fields:
  - name: GPIOALPEN
    description: GPIOALPEN.
    bit_offset: 0
    bit_size: 1
  - name: GPIOBLPEN
    description: GPIOBLPEN.
    bit_offset: 1
    bit_size: 1
  - name: GPIOCLPEN
    description: GPIOCLPEN.
    bit_offset: 2
    bit_size: 1
  - name: GPIODLPEN
    description: GPIODLPEN.
    bit_offset: 3
    bit_size: 1
  - name: GPIOELPEN
    description: GPIOELPEN.
    bit_offset: 4
    bit_size: 1
  - name: GPIOFLPEN
    description: GPIOFLPEN.
    bit_offset: 5
    bit_size: 1
  - name: GPIOGLPEN
    description: GPIOGLPEN.
    bit_offset: 6
    bit_size: 1
  - name: GPIOHLPEN
    description: GPIOHLPEN.
    bit_offset: 7
    bit_size: 1
  - name: GPIOILPEN
    description: GPIOILPEN.
    bit_offset: 8
    bit_size: 1
  - name: GPIOJLPEN
    description: GPIOJLPEN.
    bit_offset: 9
    bit_size: 1
  - name: GPIOKLPEN
    description: GPIOKLPEN.
    bit_offset: 10
    bit_size: 1
fieldset/MC_AHB4LPENSETR:
  description: This register is used by the MCU in order to set the PERxLPEN bit.
  fields:
  - name: GPIOALPEN
    description: GPIOALPEN.
    bit_offset: 0
    bit_size: 1
  - name: GPIOBLPEN
    description: GPIOBLPEN.
    bit_offset: 1
    bit_size: 1
  - name: GPIOCLPEN
    description: GPIOCLPEN.
    bit_offset: 2
    bit_size: 1
  - name: GPIODLPEN
    description: GPIODLPEN.
    bit_offset: 3
    bit_size: 1
  - name: GPIOELPEN
    description: GPIOELPEN.
    bit_offset: 4
    bit_size: 1
  - name: GPIOFLPEN
    description: GPIOFLPEN.
    bit_offset: 5
    bit_size: 1
  - name: GPIOGLPEN
    description: GPIOGLPEN.
    bit_offset: 6
    bit_size: 1
  - name: GPIOHLPEN
    description: GPIOHLPEN.
    bit_offset: 7
    bit_size: 1
  - name: GPIOILPEN
    description: GPIOILPEN.
    bit_offset: 8
    bit_size: 1
  - name: GPIOJLPEN
    description: GPIOJLPEN.
    bit_offset: 9
    bit_size: 1
  - name: GPIOKLPEN
    description: GPIOKLPEN.
    bit_offset: 10
    bit_size: 1
fieldset/MC_AHB5ENCLRR:
  description: This register is used to clear the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: GPIOZEN
    description: GPIOZEN.
    bit_offset: 0
    bit_size: 1
  - name: CRYP1EN
    description: CRYP1EN.
    bit_offset: 4
    bit_size: 1
  - name: HASH1EN
    description: HASH1EN.
    bit_offset: 5
    bit_size: 1
  - name: RNG1EN
    description: RNG1EN.
    bit_offset: 6
    bit_size: 1
  - name: BKPSRAMEN
    description: BKPSRAMEN.
    bit_offset: 8
    bit_size: 1
fieldset/MC_AHB5ENSETR:
  description: This register is used to set the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: GPIOZEN
    description: GPIOZEN.
    bit_offset: 0
    bit_size: 1
  - name: CRYP1EN
    description: CRYP1EN.
    bit_offset: 4
    bit_size: 1
  - name: HASH1EN
    description: HASH1EN.
    bit_offset: 5
    bit_size: 1
  - name: RNG1EN
    description: RNG1EN.
    bit_offset: 6
    bit_size: 1
  - name: BKPSRAMEN
    description: BKPSRAMEN.
    bit_offset: 8
    bit_size: 1
fieldset/MC_AHB5LPENCLRR:
  description: This register is used by the MCU in order to clear the PERxLPEN bit If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: GPIOZLPEN
    description: GPIOZLPEN.
    bit_offset: 0
    bit_size: 1
  - name: CRYP1LPEN
    description: CRYP1LPEN.
    bit_offset: 4
    bit_size: 1
  - name: HASH1LPEN
    description: HASH1LPEN.
    bit_offset: 5
    bit_size: 1
  - name: RNG1LPEN
    description: RNG1LPEN.
    bit_offset: 6
    bit_size: 1
  - name: BKPSRAMLPEN
    description: BKPSRAMLPEN.
    bit_offset: 8
    bit_size: 1
fieldset/MC_AHB5LPENSETR:
  description: This register is used by the MCU in order to set the PERxLPEN bit. If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: GPIOZLPEN
    description: GPIOZLPEN.
    bit_offset: 0
    bit_size: 1
  - name: CRYP1LPEN
    description: CRYP1LPEN.
    bit_offset: 4
    bit_size: 1
  - name: HASH1LPEN
    description: HASH1LPEN.
    bit_offset: 5
    bit_size: 1
  - name: RNG1LPEN
    description: RNG1LPEN.
    bit_offset: 6
    bit_size: 1
  - name: BKPSRAMLPEN
    description: BKPSRAMLPEN.
    bit_offset: 8
    bit_size: 1
fieldset/MC_AHB6ENCLRR:
  description: This register is used to clear the peripheral clock enable bit.
  fields:
  - name: MDMAEN
    description: MDMAEN.
    bit_offset: 0
    bit_size: 1
  - name: GPUEN
    description: GPUEN.
    bit_offset: 5
    bit_size: 1
  - name: ETHCKEN
    description: ETHCKEN.
    bit_offset: 7
    bit_size: 1
  - name: ETHTXEN
    description: ETHTXEN.
    bit_offset: 8
    bit_size: 1
  - name: ETHRXEN
    description: ETHRXEN.
    bit_offset: 9
    bit_size: 1
  - name: ETHMACEN
    description: ETHMACEN.
    bit_offset: 10
    bit_size: 1
  - name: FMCEN
    description: FMCEN.
    bit_offset: 12
    bit_size: 1
  - name: QSPIEN
    description: QSPIEN.
    bit_offset: 14
    bit_size: 1
  - name: SDMMC1EN
    description: SDMMC1EN.
    bit_offset: 16
    bit_size: 1
  - name: SDMMC2EN
    description: SDMMC2EN.
    bit_offset: 17
    bit_size: 1
  - name: CRC1EN
    description: CRC1EN.
    bit_offset: 20
    bit_size: 1
  - name: USBHEN
    description: USBHEN.
    bit_offset: 24
    bit_size: 1
fieldset/MC_AHB6ENSETR:
  description: This register is used to set the peripheral clock enable bit.
  fields:
  - name: MDMAEN
    description: MDMAEN.
    bit_offset: 0
    bit_size: 1
  - name: GPUEN
    description: GPUEN.
    bit_offset: 5
    bit_size: 1
  - name: ETHCKEN
    description: ETHCKEN.
    bit_offset: 7
    bit_size: 1
  - name: ETHTXEN
    description: ETHTXEN.
    bit_offset: 8
    bit_size: 1
  - name: ETHRXEN
    description: ETHRXEN.
    bit_offset: 9
    bit_size: 1
  - name: ETHMACEN
    description: ETHMACEN.
    bit_offset: 10
    bit_size: 1
  - name: FMCEN
    description: FMCEN.
    bit_offset: 12
    bit_size: 1
  - name: QSPIEN
    description: QSPIEN.
    bit_offset: 14
    bit_size: 1
  - name: SDMMC1EN
    description: SDMMC1EN.
    bit_offset: 16
    bit_size: 1
  - name: SDMMC2EN
    description: SDMMC2EN.
    bit_offset: 17
    bit_size: 1
  - name: CRC1EN
    description: CRC1EN.
    bit_offset: 20
    bit_size: 1
  - name: USBHEN
    description: USBHEN.
    bit_offset: 24
    bit_size: 1
fieldset/MC_AHB6LPENCLRR:
  description: This register is used by the MCU in order to clear the PERxLPEN bit.
  fields:
  - name: MDMALPEN
    description: MDMALPEN.
    bit_offset: 0
    bit_size: 1
  - name: GPULPEN
    description: GPULPEN.
    bit_offset: 5
    bit_size: 1
  - name: ETHCKLPEN
    description: ETHCKLPEN.
    bit_offset: 7
    bit_size: 1
  - name: ETHTXLPEN
    description: ETHTXLPEN.
    bit_offset: 8
    bit_size: 1
  - name: ETHRXLPEN
    description: ETHRXLPEN.
    bit_offset: 9
    bit_size: 1
  - name: ETHMACLPEN
    description: ETHMACLPEN.
    bit_offset: 10
    bit_size: 1
  - name: ETHSTPEN
    description: ETHSTPEN.
    bit_offset: 11
    bit_size: 1
  - name: FMCLPEN
    description: FMCLPEN.
    bit_offset: 12
    bit_size: 1
  - name: QSPILPEN
    description: QSPILPEN.
    bit_offset: 14
    bit_size: 1
  - name: SDMMC1LPEN
    description: SDMMC1LPEN.
    bit_offset: 16
    bit_size: 1
  - name: SDMMC2LPEN
    description: SDMMC2LPEN.
    bit_offset: 17
    bit_size: 1
  - name: CRC1LPEN
    description: CRC1LPEN.
    bit_offset: 20
    bit_size: 1
  - name: USBHLPEN
    description: USBHLPEN.
    bit_offset: 24
    bit_size: 1
fieldset/MC_AHB6LPENSETR:
  description: This register is used by the MCU in order to set the PERxLPEN bit.
  fields:
  - name: MDMALPEN
    description: MDMALPEN.
    bit_offset: 0
    bit_size: 1
  - name: GPULPEN
    description: GPULPEN.
    bit_offset: 5
    bit_size: 1
  - name: ETHCKLPEN
    description: ETHCKLPEN.
    bit_offset: 7
    bit_size: 1
  - name: ETHTXLPEN
    description: ETHTXLPEN.
    bit_offset: 8
    bit_size: 1
  - name: ETHRXLPEN
    description: ETHRXLPEN.
    bit_offset: 9
    bit_size: 1
  - name: ETHMACLPEN
    description: ETHMACLPEN.
    bit_offset: 10
    bit_size: 1
  - name: ETHSTPEN
    description: ETHSTPEN.
    bit_offset: 11
    bit_size: 1
  - name: FMCLPEN
    description: FMCLPEN.
    bit_offset: 12
    bit_size: 1
  - name: QSPILPEN
    description: QSPILPEN.
    bit_offset: 14
    bit_size: 1
  - name: SDMMC1LPEN
    description: SDMMC1LPEN.
    bit_offset: 16
    bit_size: 1
  - name: SDMMC2LPEN
    description: SDMMC2LPEN.
    bit_offset: 17
    bit_size: 1
  - name: CRC1LPEN
    description: CRC1LPEN.
    bit_offset: 20
    bit_size: 1
  - name: USBHLPEN
    description: USBHLPEN.
    bit_offset: 24
    bit_size: 1
fieldset/MC_APB1ENCLRR:
  description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
  fields:
  - name: TIM2EN
    description: TIM2EN.
    bit_offset: 0
    bit_size: 1
  - name: TIM3EN
    description: TIM3EN.
    bit_offset: 1
    bit_size: 1
  - name: TIM4EN
    description: TIM4EN.
    bit_offset: 2
    bit_size: 1
  - name: TIM5EN
    description: TIM5EN.
    bit_offset: 3
    bit_size: 1
  - name: TIM6EN
    description: TIM6EN.
    bit_offset: 4
    bit_size: 1
  - name: TIM7EN
    description: TIM7EN.
    bit_offset: 5
    bit_size: 1
  - name: TIM12EN
    description: TIM12EN.
    bit_offset: 6
    bit_size: 1
  - name: TIM13EN
    description: TIM13EN.
    bit_offset: 7
    bit_size: 1
  - name: TIM14EN
    description: TIM14EN.
    bit_offset: 8
    bit_size: 1
  - name: LPTIM1EN
    description: LPTIM1EN.
    bit_offset: 9
    bit_size: 1
  - name: SPI2EN
    description: SPI2EN.
    bit_offset: 11
    bit_size: 1
  - name: SPI3EN
    description: SPI3EN.
    bit_offset: 12
    bit_size: 1
  - name: USART2EN
    description: USART2EN.
    bit_offset: 14
    bit_size: 1
  - name: USART3EN
    description: USART3EN.
    bit_offset: 15
    bit_size: 1
  - name: UART4EN
    description: UART4EN.
    bit_offset: 16
    bit_size: 1
  - name: UART5EN
    description: UART5EN.
    bit_offset: 17
    bit_size: 1
  - name: UART7EN
    description: UART7EN.
    bit_offset: 18
    bit_size: 1
  - name: UART8EN
    description: UART8EN.
    bit_offset: 19
    bit_size: 1
  - name: I2C1EN
    description: I2C1EN.
    bit_offset: 21
    bit_size: 1
  - name: I2C2EN
    description: I2C2EN.
    bit_offset: 22
    bit_size: 1
  - name: I2C3EN
    description: I2C3EN.
    bit_offset: 23
    bit_size: 1
  - name: I2C5EN
    description: I2C5EN.
    bit_offset: 24
    bit_size: 1
  - name: SPDIFEN
    description: SPDIFEN.
    bit_offset: 26
    bit_size: 1
  - name: CECEN
    description: CECEN.
    bit_offset: 27
    bit_size: 1
  - name: DAC12EN
    description: DAC12EN.
    bit_offset: 29
    bit_size: 1
  - name: MDIOSEN
    description: MDIOSEN.
    bit_offset: 31
    bit_size: 1
fieldset/MC_APB1ENSETR:
  description: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return . Writing a sets the corresponding bit to.
  fields:
  - name: TIM2EN
    description: TIM2EN.
    bit_offset: 0
    bit_size: 1
  - name: TIM3EN
    description: TIM3EN.
    bit_offset: 1
    bit_size: 1
  - name: TIM4EN
    description: TIM4EN.
    bit_offset: 2
    bit_size: 1
  - name: TIM5EN
    description: TIM5EN.
    bit_offset: 3
    bit_size: 1
  - name: TIM6EN
    description: TIM6EN.
    bit_offset: 4
    bit_size: 1
  - name: TIM7EN
    description: TIM7EN.
    bit_offset: 5
    bit_size: 1
  - name: TIM12EN
    description: TIM12EN.
    bit_offset: 6
    bit_size: 1
  - name: TIM13EN
    description: TIM13EN.
    bit_offset: 7
    bit_size: 1
  - name: TIM14EN
    description: TIM14EN.
    bit_offset: 8
    bit_size: 1
  - name: LPTIM1EN
    description: LPTIM1EN.
    bit_offset: 9
    bit_size: 1
  - name: SPI2EN
    description: SPI2EN.
    bit_offset: 11
    bit_size: 1
  - name: SPI3EN
    description: SPI3EN.
    bit_offset: 12
    bit_size: 1
  - name: USART2EN
    description: USART2EN.
    bit_offset: 14
    bit_size: 1
  - name: USART3EN
    description: USART3EN.
    bit_offset: 15
    bit_size: 1
  - name: UART4EN
    description: UART4EN.
    bit_offset: 16
    bit_size: 1
  - name: UART5EN
    description: UART5EN.
    bit_offset: 17
    bit_size: 1
  - name: UART7EN
    description: UART7EN.
    bit_offset: 18
    bit_size: 1
  - name: UART8EN
    description: UART8EN.
    bit_offset: 19
    bit_size: 1
  - name: I2C1EN
    description: I2C1EN.
    bit_offset: 21
    bit_size: 1
  - name: I2C2EN
    description: I2C2EN.
    bit_offset: 22
    bit_size: 1
  - name: I2C3EN
    description: I2C3EN.
    bit_offset: 23
    bit_size: 1
  - name: I2C5EN
    description: I2C5EN.
    bit_offset: 24
    bit_size: 1
  - name: SPDIFEN
    description: SPDIFEN.
    bit_offset: 26
    bit_size: 1
  - name: CECEN
    description: CECEN.
    bit_offset: 27
    bit_size: 1
  - name: WWDG1EN
    description: WWDG1EN.
    bit_offset: 28
    bit_size: 1
  - name: DAC12EN
    description: DAC12EN.
    bit_offset: 29
    bit_size: 1
  - name: MDIOSEN
    description: MDIOSEN.
    bit_offset: 31
    bit_size: 1
fieldset/MC_APB1LPENCLRR:
  description: This register is used by the MCU in order to clear the PERxLPEN bits.
  fields:
  - name: TIM2LPEN
    description: TIM2LPEN.
    bit_offset: 0
    bit_size: 1
  - name: TIM3LPEN
    description: TIM3LPEN.
    bit_offset: 1
    bit_size: 1
  - name: TIM4LPEN
    description: TIM4LPEN.
    bit_offset: 2
    bit_size: 1
  - name: TIM5LPEN
    description: TIM5LPEN.
    bit_offset: 3
    bit_size: 1
  - name: TIM6LPEN
    description: TIM6LPEN.
    bit_offset: 4
    bit_size: 1
  - name: TIM7LPEN
    description: TIM7LPEN.
    bit_offset: 5
    bit_size: 1
  - name: TIM12LPEN
    description: TIM12LPEN.
    bit_offset: 6
    bit_size: 1
  - name: TIM13LPEN
    description: TIM13LPEN.
    bit_offset: 7
    bit_size: 1
  - name: TIM14LPEN
    description: TIM14LPEN.
    bit_offset: 8
    bit_size: 1
  - name: LPTIM1LPEN
    description: LPTIM1LPEN.
    bit_offset: 9
    bit_size: 1
  - name: SPI2LPEN
    description: SPI2LPEN.
    bit_offset: 11
    bit_size: 1
  - name: SPI3LPEN
    description: SPI3LPEN.
    bit_offset: 12
    bit_size: 1
  - name: USART2LPEN
    description: USART2LPEN.
    bit_offset: 14
    bit_size: 1
  - name: USART3LPEN
    description: USART3LPEN.
    bit_offset: 15
    bit_size: 1
  - name: UART4LPEN
    description: UART4LPEN.
    bit_offset: 16
    bit_size: 1
  - name: UART5LPEN
    description: UART5LPEN.
    bit_offset: 17
    bit_size: 1
  - name: UART7LPEN
    description: UART7LPEN.
    bit_offset: 18
    bit_size: 1
  - name: UART8LPEN
    description: UART8LPEN.
    bit_offset: 19
    bit_size: 1
  - name: I2C1LPEN
    description: I2C1LPEN.
    bit_offset: 21
    bit_size: 1
  - name: I2C2LPEN
    description: I2C2LPEN.
    bit_offset: 22
    bit_size: 1
  - name: I2C3LPEN
    description: I2C3LPEN.
    bit_offset: 23
    bit_size: 1
  - name: I2C5LPEN
    description: I2C5LPEN.
    bit_offset: 24
    bit_size: 1
  - name: SPDIFLPEN
    description: SPDIFLPEN.
    bit_offset: 26
    bit_size: 1
  - name: CECLPEN
    description: CECLPEN.
    bit_offset: 27
    bit_size: 1
  - name: WWDG1LPEN
    description: WWDG1LPEN.
    bit_offset: 28
    bit_size: 1
  - name: DAC12LPEN
    description: DAC12LPEN.
    bit_offset: 29
    bit_size: 1
  - name: MDIOSLPEN
    description: MDIOSLPEN.
    bit_offset: 31
    bit_size: 1
fieldset/MC_APB1LPENSETR:
  description: This register is used by the MCU in order to set the PERxLPEN bit.
  fields:
  - name: TIM2LPEN
    description: TIM2LPEN.
    bit_offset: 0
    bit_size: 1
  - name: TIM3LPEN
    description: TIM3LPEN.
    bit_offset: 1
    bit_size: 1
  - name: TIM4LPEN
    description: TIM4LPEN.
    bit_offset: 2
    bit_size: 1
  - name: TIM5LPEN
    description: TIM5LPEN.
    bit_offset: 3
    bit_size: 1
  - name: TIM6LPEN
    description: TIM6LPEN.
    bit_offset: 4
    bit_size: 1
  - name: TIM7LPEN
    description: TIM7LPEN.
    bit_offset: 5
    bit_size: 1
  - name: TIM12LPEN
    description: TIM12LPEN.
    bit_offset: 6
    bit_size: 1
  - name: TIM13LPEN
    description: TIM13LPEN.
    bit_offset: 7
    bit_size: 1
  - name: TIM14LPEN
    description: TIM14LPEN.
    bit_offset: 8
    bit_size: 1
  - name: LPTIM1LPEN
    description: LPTIM1LPEN.
    bit_offset: 9
    bit_size: 1
  - name: SPI2LPEN
    description: SPI2LPEN.
    bit_offset: 11
    bit_size: 1
  - name: SPI3LPEN
    description: SPI3LPEN.
    bit_offset: 12
    bit_size: 1
  - name: USART2LPEN
    description: USART2LPEN.
    bit_offset: 14
    bit_size: 1
  - name: USART3LPEN
    description: USART3LPEN.
    bit_offset: 15
    bit_size: 1
  - name: UART4LPEN
    description: UART4LPEN.
    bit_offset: 16
    bit_size: 1
  - name: UART5LPEN
    description: UART5LPEN.
    bit_offset: 17
    bit_size: 1
  - name: UART7LPEN
    description: UART7LPEN.
    bit_offset: 18
    bit_size: 1
  - name: UART8LPEN
    description: UART8LPEN.
    bit_offset: 19
    bit_size: 1
  - name: I2C1LPEN
    description: I2C1LPEN.
    bit_offset: 21
    bit_size: 1
  - name: I2C2LPEN
    description: I2C2LPEN.
    bit_offset: 22
    bit_size: 1
  - name: I2C3LPEN
    description: I2C3LPEN.
    bit_offset: 23
    bit_size: 1
  - name: I2C5LPEN
    description: I2C5LPEN.
    bit_offset: 24
    bit_size: 1
  - name: SPDIFLPEN
    description: SPDIFLPEN.
    bit_offset: 26
    bit_size: 1
  - name: CECLPEN
    description: CECLPEN.
    bit_offset: 27
    bit_size: 1
  - name: WWDG1LPEN
    description: WWDG1LPEN.
    bit_offset: 28
    bit_size: 1
  - name: DAC12LPEN
    description: DAC12LPEN.
    bit_offset: 29
    bit_size: 1
  - name: MDIOSLPEN
    description: MDIOSLPEN.
    bit_offset: 31
    bit_size: 1
fieldset/MC_APB2ENCLRR:
  description: This register is used to clear the peripheral clock enable bit.
  fields:
  - name: TIM1EN
    description: TIM1EN.
    bit_offset: 0
    bit_size: 1
  - name: TIM8EN
    description: TIM8EN.
    bit_offset: 1
    bit_size: 1
  - name: TIM15EN
    description: TIM15EN.
    bit_offset: 2
    bit_size: 1
  - name: TIM16EN
    description: TIM16EN.
    bit_offset: 3
    bit_size: 1
  - name: TIM17EN
    description: TIM17EN.
    bit_offset: 4
    bit_size: 1
  - name: SPI1EN
    description: SPI1EN.
    bit_offset: 8
    bit_size: 1
  - name: SPI4EN
    description: SPI4EN.
    bit_offset: 9
    bit_size: 1
  - name: SPI5EN
    description: SPI5EN.
    bit_offset: 10
    bit_size: 1
  - name: USART6EN
    description: USART6EN.
    bit_offset: 13
    bit_size: 1
  - name: SAI1EN
    description: SAI1EN.
    bit_offset: 16
    bit_size: 1
  - name: SAI2EN
    description: SAI2EN.
    bit_offset: 17
    bit_size: 1
  - name: SAI3EN
    description: SAI3EN.
    bit_offset: 18
    bit_size: 1
  - name: DFSDMEN
    description: DFSDMEN.
    bit_offset: 20
    bit_size: 1
  - name: ADFSDMEN
    description: ADFSDMEN.
    bit_offset: 21
    bit_size: 1
  - name: FDCANEN
    description: FDCANEN.
    bit_offset: 24
    bit_size: 1
fieldset/MC_APB2ENSETR:
  description: This register is used to set the peripheral clock enable bit.
  fields:
  - name: TIM1EN
    description: TIM1EN.
    bit_offset: 0
    bit_size: 1
  - name: TIM8EN
    description: TIM8EN.
    bit_offset: 1
    bit_size: 1
  - name: TIM15EN
    description: TIM15EN.
    bit_offset: 2
    bit_size: 1
  - name: TIM16EN
    description: TIM16EN.
    bit_offset: 3
    bit_size: 1
  - name: TIM17EN
    description: TIM17EN.
    bit_offset: 4
    bit_size: 1
  - name: SPI1EN
    description: SPI1EN.
    bit_offset: 8
    bit_size: 1
  - name: SPI4EN
    description: SPI4EN.
    bit_offset: 9
    bit_size: 1
  - name: SPI5EN
    description: SPI5EN.
    bit_offset: 10
    bit_size: 1
  - name: USART6EN
    description: USART6EN.
    bit_offset: 13
    bit_size: 1
  - name: SAI1EN
    description: SAI1EN.
    bit_offset: 16
    bit_size: 1
  - name: SAI2EN
    description: SAI2EN.
    bit_offset: 17
    bit_size: 1
  - name: SAI3EN
    description: SAI3EN.
    bit_offset: 18
    bit_size: 1
  - name: DFSDMEN
    description: DFSDMEN.
    bit_offset: 20
    bit_size: 1
  - name: ADFSDMEN
    description: ADFSDMEN.
    bit_offset: 21
    bit_size: 1
  - name: FDCANEN
    description: FDCANEN.
    bit_offset: 24
    bit_size: 1
fieldset/MC_APB2LPENCLRR:
  description: This register is used by the MCU in order to clear the PERxLPEN bit.
  fields:
  - name: TIM1LPEN
    description: TIM1LPEN.
    bit_offset: 0
    bit_size: 1
  - name: TIM8LPEN
    description: TIM8LPEN.
    bit_offset: 1
    bit_size: 1
  - name: TIM15LPEN
    description: TIM15LPEN.
    bit_offset: 2
    bit_size: 1
  - name: TIM16LPEN
    description: TIM16LPEN.
    bit_offset: 3
    bit_size: 1
  - name: TIM17LPEN
    description: TIM17LPEN.
    bit_offset: 4
    bit_size: 1
  - name: SPI1LPEN
    description: SPI1LPEN.
    bit_offset: 8
    bit_size: 1
  - name: SPI4LPEN
    description: SPI4LPEN.
    bit_offset: 9
    bit_size: 1
  - name: SPI5LPEN
    description: SPI5LPEN.
    bit_offset: 10
    bit_size: 1
  - name: USART6LPEN
    description: USART6LPEN.
    bit_offset: 13
    bit_size: 1
  - name: SAI1LPEN
    description: SAI1LPEN.
    bit_offset: 16
    bit_size: 1
  - name: SAI2LPEN
    description: SAI2LPEN.
    bit_offset: 17
    bit_size: 1
  - name: SAI3LPEN
    description: SAI3LPEN.
    bit_offset: 18
    bit_size: 1
  - name: DFSDMLPEN
    description: DFSDMLPEN.
    bit_offset: 20
    bit_size: 1
  - name: ADFSDMLPEN
    description: ADFSDMLPEN.
    bit_offset: 21
    bit_size: 1
  - name: FDCANLPEN
    description: FDCANLPEN.
    bit_offset: 24
    bit_size: 1
fieldset/MC_APB2LPENSETR:
  description: This register is used by the MCU in order to set the PERxLPEN bit.
  fields:
  - name: TIM1LPEN
    description: TIM1LPEN.
    bit_offset: 0
    bit_size: 1
  - name: TIM8LPEN
    description: TIM8LPEN.
    bit_offset: 1
    bit_size: 1
  - name: TIM15LPEN
    description: TIM15LPEN.
    bit_offset: 2
    bit_size: 1
  - name: TIM16LPEN
    description: TIM16LPEN.
    bit_offset: 3
    bit_size: 1
  - name: TIM17LPEN
    description: TIM17LPEN.
    bit_offset: 4
    bit_size: 1
  - name: SPI1LPEN
    description: SPI1LPEN.
    bit_offset: 8
    bit_size: 1
  - name: SPI4LPEN
    description: SPI4LPEN.
    bit_offset: 9
    bit_size: 1
  - name: SPI5LPEN
    description: SPI5LPEN.
    bit_offset: 10
    bit_size: 1
  - name: USART6LPEN
    description: USART6LPEN.
    bit_offset: 13
    bit_size: 1
  - name: SAI1LPEN
    description: SAI1LPEN.
    bit_offset: 16
    bit_size: 1
  - name: SAI2LPEN
    description: SAI2LPEN.
    bit_offset: 17
    bit_size: 1
  - name: SAI3LPEN
    description: SAI3LPEN.
    bit_offset: 18
    bit_size: 1
  - name: DFSDMLPEN
    description: DFSDMLPEN.
    bit_offset: 20
    bit_size: 1
  - name: ADFSDMLPEN
    description: ADFSDMLPEN.
    bit_offset: 21
    bit_size: 1
  - name: FDCANLPEN
    description: FDCANLPEN.
    bit_offset: 24
    bit_size: 1
fieldset/MC_APB3ENCLRR:
  description: This register is used to clear the peripheral clock enable bit.
  fields:
  - name: LPTIM2EN
    description: LPTIM2EN.
    bit_offset: 0
    bit_size: 1
  - name: LPTIM3EN
    description: LPTIM3EN.
    bit_offset: 1
    bit_size: 1
  - name: LPTIM4EN
    description: LPTIM4EN.
    bit_offset: 2
    bit_size: 1
  - name: LPTIM5EN
    description: LPTIM5EN.
    bit_offset: 3
    bit_size: 1
  - name: SAI4EN
    description: SAI4EN.
    bit_offset: 8
    bit_size: 1
  - name: SYSCFGEN
    description: SYSCFGEN.
    bit_offset: 11
    bit_size: 1
  - name: VREFEN
    description: VREFEN.
    bit_offset: 13
    bit_size: 1
  - name: DTSEN
    description: DTSEN.
    bit_offset: 16
    bit_size: 1
  - name: HDPEN
    description: HDPEN.
    bit_offset: 20
    bit_size: 1
fieldset/MC_APB3ENSETR:
  description: This register is used to set the peripheral clock enable bit.
  fields:
  - name: LPTIM2EN
    description: LPTIM2EN.
    bit_offset: 0
    bit_size: 1
  - name: LPTIM3EN
    description: LPTIM3EN.
    bit_offset: 1
    bit_size: 1
  - name: LPTIM4EN
    description: LPTIM4EN.
    bit_offset: 2
    bit_size: 1
  - name: LPTIM5EN
    description: LPTIM5EN.
    bit_offset: 3
    bit_size: 1
  - name: SAI4EN
    description: SAI4EN.
    bit_offset: 8
    bit_size: 1
  - name: SYSCFGEN
    description: SYSCFGEN.
    bit_offset: 11
    bit_size: 1
  - name: VREFEN
    description: VREFEN.
    bit_offset: 13
    bit_size: 1
  - name: DTSEN
    description: DTSEN.
    bit_offset: 16
    bit_size: 1
  - name: HDPEN
    description: HDPEN.
    bit_offset: 20
    bit_size: 1
fieldset/MC_APB3LPENCLRR:
  description: This register is used by the MCU in order to clear the PERxLPEN bit.
  fields:
  - name: LPTIM2LPEN
    description: LPTIM2LPEN.
    bit_offset: 0
    bit_size: 1
  - name: LPTIM3LPEN
    description: LPTIM3LPEN.
    bit_offset: 1
    bit_size: 1
  - name: LPTIM4LPEN
    description: LPTIM4LPEN.
    bit_offset: 2
    bit_size: 1
  - name: LPTIM5LPEN
    description: LPTIM5LPEN.
    bit_offset: 3
    bit_size: 1
  - name: SAI4LPEN
    description: SAI4LPEN.
    bit_offset: 8
    bit_size: 1
  - name: SYSCFGLPEN
    description: SYSCFGLPEN.
    bit_offset: 11
    bit_size: 1
  - name: VREFLPEN
    description: VREFLPEN.
    bit_offset: 13
    bit_size: 1
  - name: DTSLPEN
    description: DTSLPEN.
    bit_offset: 16
    bit_size: 1
fieldset/MC_APB3LPENSETR:
  description: This register is used by the MCU in order to set the PERxLPEN bit.
  fields:
  - name: LPTIM2LPEN
    description: LPTIM2LPEN.
    bit_offset: 0
    bit_size: 1
  - name: LPTIM3LPEN
    description: LPTIM3LPEN.
    bit_offset: 1
    bit_size: 1
  - name: LPTIM4LPEN
    description: LPTIM4LPEN.
    bit_offset: 2
    bit_size: 1
  - name: LPTIM5LPEN
    description: LPTIM5LPEN.
    bit_offset: 3
    bit_size: 1
  - name: SAI4LPEN
    description: SAI4LPEN.
    bit_offset: 8
    bit_size: 1
  - name: SYSCFGLPEN
    description: SYSCFGLPEN.
    bit_offset: 11
    bit_size: 1
  - name: VREFLPEN
    description: VREFLPEN.
    bit_offset: 13
    bit_size: 1
  - name: DTSLPEN
    description: DTSLPEN.
    bit_offset: 16
    bit_size: 1
fieldset/MC_APB4ENCLRR:
  description: This register is used to clear the peripheral clock enable bit.
  fields:
  - name: LTDCEN
    description: LTDCEN.
    bit_offset: 0
    bit_size: 1
  - name: DSIEN
    description: DSIEN.
    bit_offset: 4
    bit_size: 1
  - name: DDRPERFMEN
    description: DDRPERFMEN.
    bit_offset: 8
    bit_size: 1
  - name: USBPHYEN
    description: USBPHYEN.
    bit_offset: 16
    bit_size: 1
  - name: STGENROEN
    description: STGENROEN.
    bit_offset: 20
    bit_size: 1
fieldset/MC_APB4ENSETR:
  description: This register is used to set the peripheral clock enable bit.
  fields:
  - name: LTDCEN
    description: LTDCEN.
    bit_offset: 0
    bit_size: 1
  - name: DSIEN
    description: DSIEN.
    bit_offset: 4
    bit_size: 1
  - name: DDRPERFMEN
    description: DDRPERFMEN.
    bit_offset: 8
    bit_size: 1
  - name: USBPHYEN
    description: USBPHYEN.
    bit_offset: 16
    bit_size: 1
  - name: STGENROEN
    description: STGENROEN.
    bit_offset: 20
    bit_size: 1
fieldset/MC_APB4LPENCLRR:
  description: This register is used by the MCU in order to clear the PERxLPEN bit.
  fields:
  - name: LTDCLPEN
    description: LTDCLPEN.
    bit_offset: 0
    bit_size: 1
  - name: DSILPEN
    description: DSILPEN.
    bit_offset: 4
    bit_size: 1
  - name: DDRPERFMLPEN
    description: DDRPERFMLPEN.
    bit_offset: 8
    bit_size: 1
  - name: USBPHYLPEN
    description: USBPHYLPEN.
    bit_offset: 16
    bit_size: 1
  - name: STGENROLPEN
    description: STGENROLPEN.
    bit_offset: 20
    bit_size: 1
  - name: STGENROSTPEN
    description: STGENROSTPEN.
    bit_offset: 21
    bit_size: 1
fieldset/MC_APB4LPENSETR:
  description: This register is used by the MCU in order to set the PERxLPEN bit.
  fields:
  - name: LTDCLPEN
    description: LTDCLPEN.
    bit_offset: 0
    bit_size: 1
  - name: DSILPEN
    description: DSILPEN.
    bit_offset: 4
    bit_size: 1
  - name: DDRPERFMLPEN
    description: DDRPERFMLPEN.
    bit_offset: 8
    bit_size: 1
  - name: USBPHYLPEN
    description: USBPHYLPEN.
    bit_offset: 16
    bit_size: 1
  - name: STGENROLPEN
    description: STGENROLPEN.
    bit_offset: 20
    bit_size: 1
  - name: STGENROSTPEN
    description: STGENROSTPEN.
    bit_offset: 21
    bit_size: 1
fieldset/MC_APB5ENCLRR:
  description: This register is used to clear the peripheral clock enable bit.
  fields:
  - name: SPI6EN
    description: SPI6EN.
    bit_offset: 0
    bit_size: 1
  - name: I2C4EN
    description: I2C4EN.
    bit_offset: 2
    bit_size: 1
  - name: I2C6EN
    description: I2C6EN.
    bit_offset: 3
    bit_size: 1
  - name: USART1EN
    description: USART1EN.
    bit_offset: 4
    bit_size: 1
  - name: RTCAPBEN
    description: RTCAPBEN.
    bit_offset: 8
    bit_size: 1
  - name: TZC1EN
    description: TZC1EN.
    bit_offset: 11
    bit_size: 1
  - name: TZC2EN
    description: TZC2EN.
    bit_offset: 12
    bit_size: 1
  - name: TZPCEN
    description: TZPCEN.
    bit_offset: 13
    bit_size: 1
  - name: BSECEN
    description: BSECEN.
    bit_offset: 16
    bit_size: 1
  - name: STGENEN
    description: STGENEN.
    bit_offset: 20
    bit_size: 1
fieldset/MC_APB5ENSETR:
  description: This register is used to set the peripheral clock enable bit.
  fields:
  - name: SPI6EN
    description: SPI6EN.
    bit_offset: 0
    bit_size: 1
  - name: I2C4EN
    description: I2C4EN.
    bit_offset: 2
    bit_size: 1
  - name: I2C6EN
    description: I2C6EN.
    bit_offset: 3
    bit_size: 1
  - name: USART1EN
    description: USART1EN.
    bit_offset: 4
    bit_size: 1
  - name: RTCAPBEN
    description: RTCAPBEN.
    bit_offset: 8
    bit_size: 1
  - name: TZC1EN
    description: TZC1EN.
    bit_offset: 11
    bit_size: 1
  - name: TZC2EN
    description: TZC2EN.
    bit_offset: 12
    bit_size: 1
  - name: TZPCEN
    description: TZPCEN.
    bit_offset: 13
    bit_size: 1
  - name: BSECEN
    description: BSECEN.
    bit_offset: 16
    bit_size: 1
  - name: STGENEN
    description: STGENEN.
    bit_offset: 20
    bit_size: 1
fieldset/MC_APB5LPENCLRR:
  description: This register is used by the MCU in order to clear the PERxLPEN bit.
  fields:
  - name: SPI6LPEN
    description: SPI6LPEN.
    bit_offset: 0
    bit_size: 1
  - name: I2C4LPEN
    description: I2C4LPEN.
    bit_offset: 2
    bit_size: 1
  - name: I2C6LPEN
    description: I2C6LPEN.
    bit_offset: 3
    bit_size: 1
  - name: USART1LPEN
    description: USART1LPEN.
    bit_offset: 4
    bit_size: 1
  - name: RTCAPBLPEN
    description: RTCAPBLPEN.
    bit_offset: 8
    bit_size: 1
  - name: TZC1LPEN
    description: TZC1LPEN.
    bit_offset: 11
    bit_size: 1
  - name: TZC2LPEN
    description: TZC2LPEN.
    bit_offset: 12
    bit_size: 1
  - name: TZPCLPEN
    description: TZPCLPEN.
    bit_offset: 13
    bit_size: 1
  - name: BSECLPEN
    description: BSECLPEN.
    bit_offset: 16
    bit_size: 1
  - name: STGENLPEN
    description: STGENLPEN.
    bit_offset: 20
    bit_size: 1
  - name: STGENSTPEN
    description: STGENSTPEN.
    bit_offset: 21
    bit_size: 1
fieldset/MC_APB5LPENSETR:
  description: This register is used by the MCU in order to set the PERxLPEN bit.
  fields:
  - name: SPI6LPEN
    description: SPI6LPEN.
    bit_offset: 0
    bit_size: 1
  - name: I2C4LPEN
    description: I2C4LPEN.
    bit_offset: 2
    bit_size: 1
  - name: I2C6LPEN
    description: I2C6LPEN.
    bit_offset: 3
    bit_size: 1
  - name: USART1LPEN
    description: USART1LPEN.
    bit_offset: 4
    bit_size: 1
  - name: RTCAPBLPEN
    description: RTCAPBLPEN.
    bit_offset: 8
    bit_size: 1
  - name: TZC1LPEN
    description: TZC1LPEN.
    bit_offset: 11
    bit_size: 1
  - name: TZC2LPEN
    description: TZC2LPEN.
    bit_offset: 12
    bit_size: 1
  - name: TZPCLPEN
    description: TZPCLPEN.
    bit_offset: 13
    bit_size: 1
  - name: BSECLPEN
    description: BSECLPEN.
    bit_offset: 16
    bit_size: 1
  - name: STGENLPEN
    description: STGENLPEN.
    bit_offset: 20
    bit_size: 1
  - name: STGENSTPEN
    description: STGENSTPEN.
    bit_offset: 21
    bit_size: 1
fieldset/MC_AXIMENCLRR:
  description: This register is used to clear the peripheral clock enable bit.
  fields:
  - name: SYSRAMEN
    description: SYSRAMEN.
    bit_offset: 0
    bit_size: 1
fieldset/MC_AXIMENSETR:
  description: This register is used to set the peripheral clock enable bit.
  fields:
  - name: SYSRAMEN
    description: SYSRAMEN.
    bit_offset: 0
    bit_size: 1
fieldset/MC_AXIMLPENCLRR:
  description: This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral.
  fields:
  - name: SYSRAMLPEN
    description: SYSRAMLPEN.
    bit_offset: 0
    bit_size: 1
fieldset/MC_AXIMLPENSETR:
  description: This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral.
  fields:
  - name: SYSRAMLPEN
    description: SYSRAMLPEN.
    bit_offset: 0
    bit_size: 1
fieldset/MC_CIER:
  description: 'This register shall be used by the MCU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details.'
  fields:
  - name: LSIRDYIE
    description: LSIRDYIE.
    bit_offset: 0
    bit_size: 1
  - name: LSERDYIE
    description: LSERDYIE.
    bit_offset: 1
    bit_size: 1
  - name: HSIRDYIE
    description: HSIRDYIE.
    bit_offset: 2
    bit_size: 1
  - name: HSERDYIE
    description: HSERDYIE.
    bit_offset: 3
    bit_size: 1
  - name: CSIRDYIE
    description: CSIRDYIE.
    bit_offset: 4
    bit_size: 1
  - name: PLL1DYIE
    description: PLL1DYIE.
    bit_offset: 8
    bit_size: 1
  - name: PLL2DYIE
    description: PLL2DYIE.
    bit_offset: 9
    bit_size: 1
  - name: PLL3DYIE
    description: PLL3DYIE.
    bit_offset: 10
    bit_size: 1
  - name: PLL4DYIE
    description: PLL4DYIE.
    bit_offset: 11
    bit_size: 1
  - name: LSECSSIE
    description: LSECSSIE.
    bit_offset: 16
    bit_size: 1
  - name: WKUPIE
    description: WKUPIE.
    bit_offset: 20
    bit_size: 1
fieldset/MC_CIFR:
  description: This register shall be used by the MCU in order to read and clear the interrupt flags.
  fields:
  - name: LSIRDYF
    description: LSIRDYF.
    bit_offset: 0
    bit_size: 1
  - name: LSERDYF
    description: LSERDYF.
    bit_offset: 1
    bit_size: 1
  - name: HSIRDYF
    description: HSIRDYF.
    bit_offset: 2
    bit_size: 1
  - name: HSERDYF
    description: HSERDYF.
    bit_offset: 3
    bit_size: 1
  - name: CSIRDYF
    description: CSIRDYF.
    bit_offset: 4
    bit_size: 1
  - name: PLL1DYF
    description: PLL1DYF.
    bit_offset: 8
    bit_size: 1
  - name: PLL2DYF
    description: PLL2DYF.
    bit_offset: 9
    bit_size: 1
  - name: PLL3DYF
    description: PLL3DYF.
    bit_offset: 10
    bit_size: 1
  - name: PLL4DYF
    description: PLL4DYF.
    bit_offset: 11
    bit_size: 1
  - name: LSECSSF
    description: LSECSSF.
    bit_offset: 16
    bit_size: 1
  - name: WKUPF
    description: WKUPF.
    bit_offset: 20
    bit_size: 1
fieldset/MC_MLAHBENCLRR:
  description: This register is used to clear the peripheral clock enable bit.
  fields:
  - name: RETRAMEN
    description: RETRAMEN.
    bit_offset: 4
    bit_size: 1
fieldset/MC_MLAHBENSETR:
  description: This register is used to set the peripheral clock enable bit.
  fields:
  - name: RETRAMEN
    description: RETRAMEN.
    bit_offset: 4
    bit_size: 1
fieldset/MC_MLAHBLPENCLRR:
  description: This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral.
  fields:
  - name: SRAM1LPEN
    description: SRAM1LPEN.
    bit_offset: 0
    bit_size: 1
  - name: SRAM2LPEN
    description: SRAM2LPEN.
    bit_offset: 1
    bit_size: 1
  - name: SRAM34LPEN
    description: SRAM34LPEN.
    bit_offset: 2
    bit_size: 1
  - name: RETRAMLPEN
    description: RETRAMLPEN.
    bit_offset: 4
    bit_size: 1
fieldset/MC_MLAHBLPENSETR:
  description: This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral.
  fields:
  - name: SRAM1LPEN
    description: SRAM1LPEN.
    bit_offset: 0
    bit_size: 1
  - name: SRAM2LPEN
    description: SRAM2LPEN.
    bit_offset: 1
    bit_size: 1
  - name: SRAM34LPEN
    description: SRAM34LPEN.
    bit_offset: 2
    bit_size: 1
  - name: RETRAMLPEN
    description: RETRAMLPEN.
    bit_offset: 4
    bit_size: 1
fieldset/MC_RSTSCLRR:
  description: This register is used by the MCU to check the reset source.
  fields:
  - name: PORRSTF
    description: PORRSTF.
    bit_offset: 0
    bit_size: 1
  - name: BORRSTF
    description: BORRSTF.
    bit_offset: 1
    bit_size: 1
  - name: PADRSTF
    description: PADRSTF.
    bit_offset: 2
    bit_size: 1
  - name: HCSSRSTF
    description: HCSSRSTF.
    bit_offset: 3
    bit_size: 1
  - name: VCORERSTF
    description: VCORERSTF.
    bit_offset: 4
    bit_size: 1
  - name: MCURSTF
    description: MCURSTF.
    bit_offset: 5
    bit_size: 1
  - name: MPSYSRSTF
    description: MPSYSRSTF.
    bit_offset: 6
    bit_size: 1
  - name: MCSYSRSTF
    description: MCSYSRSTF.
    bit_offset: 7
    bit_size: 1
  - name: IWDG1RSTF
    description: IWDG1RSTF.
    bit_offset: 8
    bit_size: 1
  - name: IWDG2RSTF
    description: IWDG2RSTF.
    bit_offset: 9
    bit_size: 1
  - name: WWDG1RSTF
    description: WWDG1RSTF.
    bit_offset: 10
    bit_size: 1
fieldset/MPCKDIVR:
  description: 'This register is used to control the MPU clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.'
  fields:
  - name: MPUDIV
    description: MPUDIV.
    bit_offset: 0
    bit_size: 3
  - name: MPUDIVRDY
    description: MPUDIVRDY.
    bit_offset: 31
    bit_size: 1
fieldset/MPCKSELR:
  description: 'This register is used to select the clock source for the MPU. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
  fields:
  - name: MPUSRC
    description: MPUSRC.
    bit_offset: 0
    bit_size: 2
  - name: MPUSRCRDY
    description: MPUSRCRDY.
    bit_offset: 31
    bit_size: 1
fieldset/MP_AHB2ENCLRR:
  description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
  fields:
  - name: DMA1EN
    description: DMA1EN.
    bit_offset: 0
    bit_size: 1
  - name: DMA2EN
    description: DMA2EN.
    bit_offset: 1
    bit_size: 1
  - name: DMAMUXEN
    description: DMAMUXEN.
    bit_offset: 2
    bit_size: 1
  - name: ADC12EN
    description: ADC12EN.
    bit_offset: 5
    bit_size: 1
  - name: USBOEN
    description: USBOEN.
    bit_offset: 8
    bit_size: 1
  - name: SDMMC3EN
    description: SDMMC3EN.
    bit_offset: 16
    bit_size: 1
fieldset/MP_AHB2ENSETR:
  description: This register is used to set the peripheral clock enable bit of the corresponding peripheral.
  fields:
  - name: DMA1EN
    description: DMA1EN.
    bit_offset: 0
    bit_size: 1
  - name: DMA2EN
    description: DMA2EN.
    bit_offset: 1
    bit_size: 1
  - name: DMAMUXEN
    description: DMAMUXEN.
    bit_offset: 2
    bit_size: 1
  - name: ADC12EN
    description: ADC12EN.
    bit_offset: 5
    bit_size: 1
  - name: USBOEN
    description: USBOEN.
    bit_offset: 8
    bit_size: 1
  - name: SDMMC3EN
    description: SDMMC3EN.
    bit_offset: 16
    bit_size: 1
fieldset/MP_AHB2LPENCLRR:
  description: This register is used by the MCU in order to clear the PERxLPEN bits.
  fields:
  - name: DMA1LPEN
    description: DMA1LPEN.
    bit_offset: 0
    bit_size: 1
  - name: DMA2LPEN
    description: DMA2LPEN.
    bit_offset: 1
    bit_size: 1
  - name: DMAMUXLPEN
    description: DMAMUXLPEN.
    bit_offset: 2
    bit_size: 1
  - name: ADC12LPEN
    description: ADC12LPEN.
    bit_offset: 5
    bit_size: 1
  - name: USBOLPEN
    description: USBOLPEN.
    bit_offset: 8
    bit_size: 1
  - name: SDMMC3LPEN
    description: SDMMC3LPEN.
    bit_offset: 16
    bit_size: 1
fieldset/MP_AHB2LPENSETR:
  description: This register is used by the MPU in order to set the PERxLPEN bit.
  fields:
  - name: DMA1LPEN
    description: DMA1LPEN.
    bit_offset: 0
    bit_size: 1
  - name: DMA2LPEN
    description: DMA2LPEN.
    bit_offset: 1
    bit_size: 1
  - name: DMAMUXLPEN
    description: DMAMUXLPEN.
    bit_offset: 2
    bit_size: 1
  - name: ADC12LPEN
    description: ADC12LPEN.
    bit_offset: 5
    bit_size: 1
  - name: USBOLPEN
    description: USBOLPEN.
    bit_offset: 8
    bit_size: 1
  - name: SDMMC3LPEN
    description: SDMMC3LPEN.
    bit_offset: 16
    bit_size: 1
fieldset/MP_AHB3ENCLRR:
  description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
  fields:
  - name: DCMIEN
    description: DCMIEN.
    bit_offset: 0
    bit_size: 1
  - name: CRYP2EN
    description: CRYP2EN.
    bit_offset: 4
    bit_size: 1
  - name: HASH2EN
    description: HASH2EN.
    bit_offset: 5
    bit_size: 1
  - name: RNG2EN
    description: RNG2EN.
    bit_offset: 6
    bit_size: 1
  - name: CRC2EN
    description: CRC2EN.
    bit_offset: 7
    bit_size: 1
  - name: HSEMEN
    description: HSEMEN.
    bit_offset: 11
    bit_size: 1
  - name: IPCCEN
    description: IPCCEN.
    bit_offset: 12
    bit_size: 1
fieldset/MP_AHB3ENSETR:
  description: This register is used to set the peripheral clock enable bit of the corresponding peripheral.
  fields:
  - name: DCMIEN
    description: DCMIEN.
    bit_offset: 0
    bit_size: 1
  - name: CRYP2EN
    description: CRYP2EN.
    bit_offset: 4
    bit_size: 1
  - name: HASH2EN
    description: HASH2EN.
    bit_offset: 5
    bit_size: 1
  - name: RNG2EN
    description: RNG2EN.
    bit_offset: 6
    bit_size: 1
  - name: CRC2EN
    description: CRC2EN.
    bit_offset: 7
    bit_size: 1
  - name: HSEMEN
    description: HSEMEN.
    bit_offset: 11
    bit_size: 1
  - name: IPCCEN
    description: IPCCEN.
    bit_offset: 12
    bit_size: 1
fieldset/MP_AHB3LPENCLRR:
  description: This register is used by the MPU in order to clear the PERxLPEN bit.
  fields:
  - name: DCMILPEN
    description: DCMILPEN.
    bit_offset: 0
    bit_size: 1
  - name: CRYP2LPEN
    description: CRYP2LPEN.
    bit_offset: 4
    bit_size: 1
  - name: HASH2LPEN
    description: HASH2LPEN.
    bit_offset: 5
    bit_size: 1
  - name: RNG2LPEN
    description: RNG2LPEN.
    bit_offset: 6
    bit_size: 1
  - name: CRC2LPEN
    description: CRC2LPEN.
    bit_offset: 7
    bit_size: 1
  - name: HSEMLPEN
    description: HSEMLPEN.
    bit_offset: 11
    bit_size: 1
  - name: IPCCLPEN
    description: IPCCLPEN.
    bit_offset: 12
    bit_size: 1
fieldset/MP_AHB3LPENSETR:
  description: This register is used by the MPU.
  fields:
  - name: DCMILPEN
    description: DCMILPEN.
    bit_offset: 0
    bit_size: 1
  - name: CRYP2LPEN
    description: CRYP2LPEN.
    bit_offset: 4
    bit_size: 1
  - name: HASH2LPEN
    description: HASH2LPEN.
    bit_offset: 5
    bit_size: 1
  - name: RNG2LPEN
    description: RNG2LPEN.
    bit_offset: 6
    bit_size: 1
  - name: CRC2LPEN
    description: CRC2LPEN.
    bit_offset: 7
    bit_size: 1
  - name: HSEMLPEN
    description: HSEMLPEN.
    bit_offset: 11
    bit_size: 1
  - name: IPCCLPEN
    description: IPCCLPEN.
    bit_offset: 12
    bit_size: 1
fieldset/MP_AHB4ENCLRR:
  description: This register is used to clear the peripheral clock enable bit.
  fields:
  - name: GPIOAEN
    description: GPIOAEN.
    bit_offset: 0
    bit_size: 1
  - name: GPIOBEN
    description: GPIOBEN.
    bit_offset: 1
    bit_size: 1
  - name: GPIOCEN
    description: GPIOCEN.
    bit_offset: 2
    bit_size: 1
  - name: GPIODEN
    description: GPIODEN.
    bit_offset: 3
    bit_size: 1
  - name: GPIOEEN
    description: GPIOEEN.
    bit_offset: 4
    bit_size: 1
  - name: GPIOFEN
    description: GPIOFEN.
    bit_offset: 5
    bit_size: 1
  - name: GPIOGEN
    description: GPIOGEN.
    bit_offset: 6
    bit_size: 1
  - name: GPIOHEN
    description: GPIOHEN.
    bit_offset: 7
    bit_size: 1
  - name: GPIOIEN
    description: GPIOIEN.
    bit_offset: 8
    bit_size: 1
  - name: GPIOJEN
    description: GPIOJEN.
    bit_offset: 9
    bit_size: 1
  - name: GPIOKEN
    description: GPIOKEN.
    bit_offset: 10
    bit_size: 1
fieldset/MP_AHB4ENSETR:
  description: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU.
  fields:
  - name: GPIOAEN
    description: GPIOAEN.
    bit_offset: 0
    bit_size: 1
  - name: GPIOBEN
    description: GPIOBEN.
    bit_offset: 1
    bit_size: 1
  - name: GPIOCEN
    description: GPIOCEN.
    bit_offset: 2
    bit_size: 1
  - name: GPIODEN
    description: GPIODEN.
    bit_offset: 3
    bit_size: 1
  - name: GPIOEEN
    description: GPIOEEN.
    bit_offset: 4
    bit_size: 1
  - name: GPIOFEN
    description: GPIOFEN.
    bit_offset: 5
    bit_size: 1
  - name: GPIOGEN
    description: GPIOGEN.
    bit_offset: 6
    bit_size: 1
  - name: GPIOHEN
    description: GPIOHEN.
    bit_offset: 7
    bit_size: 1
  - name: GPIOIEN
    description: GPIOIEN.
    bit_offset: 8
    bit_size: 1
  - name: GPIOJEN
    description: GPIOJEN.
    bit_offset: 9
    bit_size: 1
  - name: GPIOKEN
    description: GPIOKEN.
    bit_offset: 10
    bit_size: 1
fieldset/MP_AHB4LPENCLRR:
  description: This register is used by the MPU.
  fields:
  - name: GPIOALPEN
    description: GPIOALPEN.
    bit_offset: 0
    bit_size: 1
  - name: GPIOBLPEN
    description: GPIOBLPEN.
    bit_offset: 1
    bit_size: 1
  - name: GPIOCLPEN
    description: GPIOCLPEN.
    bit_offset: 2
    bit_size: 1
  - name: GPIODLPEN
    description: GPIODLPEN.
    bit_offset: 3
    bit_size: 1
  - name: GPIOELPEN
    description: GPIOELPEN.
    bit_offset: 4
    bit_size: 1
  - name: GPIOFLPEN
    description: GPIOFLPEN.
    bit_offset: 5
    bit_size: 1
  - name: GPIOGLPEN
    description: GPIOGLPEN.
    bit_offset: 6
    bit_size: 1
  - name: GPIOHLPEN
    description: GPIOHLPEN.
    bit_offset: 7
    bit_size: 1
  - name: GPIOILPEN
    description: GPIOILPEN.
    bit_offset: 8
    bit_size: 1
  - name: GPIOJLPEN
    description: GPIOJLPEN.
    bit_offset: 9
    bit_size: 1
  - name: GPIOKLPEN
    description: GPIOKLPEN.
    bit_offset: 10
    bit_size: 1
fieldset/MP_AHB4LPENSETR:
  description: This register is used by the MPU.
  fields:
  - name: GPIOALPEN
    description: GPIOALPEN.
    bit_offset: 0
    bit_size: 1
  - name: GPIOBLPEN
    description: GPIOBLPEN.
    bit_offset: 1
    bit_size: 1
  - name: GPIOCLPEN
    description: GPIOCLPEN.
    bit_offset: 2
    bit_size: 1
  - name: GPIODLPEN
    description: GPIODLPEN.
    bit_offset: 3
    bit_size: 1
  - name: GPIOELPEN
    description: GPIOELPEN.
    bit_offset: 4
    bit_size: 1
  - name: GPIOFLPEN
    description: GPIOFLPEN.
    bit_offset: 5
    bit_size: 1
  - name: GPIOGLPEN
    description: GPIOGLPEN.
    bit_offset: 6
    bit_size: 1
  - name: GPIOHLPEN
    description: GPIOHLPEN.
    bit_offset: 7
    bit_size: 1
  - name: GPIOILPEN
    description: GPIOILPEN.
    bit_offset: 8
    bit_size: 1
  - name: GPIOJLPEN
    description: GPIOJLPEN.
    bit_offset: 9
    bit_size: 1
  - name: GPIOKLPEN
    description: GPIOKLPEN.
    bit_offset: 10
    bit_size: 1
fieldset/MP_AHB5ENCLRR:
  description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: GPIOZEN
    description: GPIOZEN.
    bit_offset: 0
    bit_size: 1
  - name: CRYP1EN
    description: CRYP1EN.
    bit_offset: 4
    bit_size: 1
  - name: HASH1EN
    description: HASH1EN.
    bit_offset: 5
    bit_size: 1
  - name: RNG1EN
    description: RNG1EN.
    bit_offset: 6
    bit_size: 1
  - name: BKPSRAMEN
    description: BKPSRAMEN.
    bit_offset: 8
    bit_size: 1
  - name: AXIMCEN
    description: AXIMCEN.
    bit_offset: 16
    bit_size: 1
fieldset/MP_AHB5ENSETR:
  description: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: GPIOZEN
    description: GPIOZEN.
    bit_offset: 0
    bit_size: 1
  - name: CRYP1EN
    description: CRYP1EN.
    bit_offset: 4
    bit_size: 1
  - name: HASH1EN
    description: HASH1EN.
    bit_offset: 5
    bit_size: 1
  - name: RNG1EN
    description: RNG1EN.
    bit_offset: 6
    bit_size: 1
  - name: BKPSRAMEN
    description: BKPSRAMEN.
    bit_offset: 8
    bit_size: 1
  - name: AXIMCEN
    description: AXIMCEN.
    bit_offset: 16
    bit_size: 1
fieldset/MP_AHB5LPENCLRR:
  description: This register is used by the MCU.
  fields:
  - name: GPIOZLPEN
    description: GPIOZLPEN.
    bit_offset: 0
    bit_size: 1
  - name: CRYP1LPEN
    description: CRYP1LPEN.
    bit_offset: 4
    bit_size: 1
  - name: HASH1LPEN
    description: HASH1LPEN.
    bit_offset: 5
    bit_size: 1
  - name: RNG1LPEN
    description: RNG1LPEN.
    bit_offset: 6
    bit_size: 1
  - name: BKPSRAMLPEN
    description: BKPSRAMLPEN.
    bit_offset: 8
    bit_size: 1
fieldset/MP_AHB5LPENSETR:
  description: This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: GPIOZLPEN
    description: GPIOZLPEN.
    bit_offset: 0
    bit_size: 1
  - name: CRYP1LPEN
    description: CRYP1LPEN.
    bit_offset: 4
    bit_size: 1
  - name: HASH1LPEN
    description: HASH1LPEN.
    bit_offset: 5
    bit_size: 1
  - name: RNG1LPEN
    description: RNG1LPEN.
    bit_offset: 6
    bit_size: 1
  - name: BKPSRAMLPEN
    description: BKPSRAMLPEN.
    bit_offset: 8
    bit_size: 1
fieldset/MP_AHB6ENCLRR:
  description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to.
  fields:
  - name: MDMAEN
    description: MDMAEN.
    bit_offset: 0
    bit_size: 1
  - name: GPUEN
    description: GPUEN.
    bit_offset: 5
    bit_size: 1
  - name: ETHCKEN
    description: ETHCKEN.
    bit_offset: 7
    bit_size: 1
  - name: ETHTXEN
    description: ETHTXEN.
    bit_offset: 8
    bit_size: 1
  - name: ETHRXEN
    description: ETHRXEN.
    bit_offset: 9
    bit_size: 1
  - name: ETHMACEN
    description: ETHMACEN.
    bit_offset: 10
    bit_size: 1
  - name: FMCEN
    description: FMCEN.
    bit_offset: 12
    bit_size: 1
  - name: QSPIEN
    description: QSPIEN.
    bit_offset: 14
    bit_size: 1
  - name: SDMMC1EN
    description: SDMMC1EN.
    bit_offset: 16
    bit_size: 1
  - name: SDMMC2EN
    description: SDMMC2EN.
    bit_offset: 17
    bit_size: 1
  - name: CRC1EN
    description: CRC1EN.
    bit_offset: 20
    bit_size: 1
  - name: USBHEN
    description: USBHEN.
    bit_offset: 24
    bit_size: 1
fieldset/MP_AHB6ENSETR:
  description: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to.
  fields:
  - name: MDMAEN
    description: MDMAEN.
    bit_offset: 0
    bit_size: 1
  - name: GPUEN
    description: GPUEN.
    bit_offset: 5
    bit_size: 1
  - name: ETHCKEN
    description: ETHCKEN.
    bit_offset: 7
    bit_size: 1
  - name: ETHTXEN
    description: ETHTXEN.
    bit_offset: 8
    bit_size: 1
  - name: ETHRXEN
    description: ETHRXEN.
    bit_offset: 9
    bit_size: 1
  - name: ETHMACEN
    description: ETHMACEN.
    bit_offset: 10
    bit_size: 1
  - name: FMCEN
    description: FMCEN.
    bit_offset: 12
    bit_size: 1
  - name: QSPIEN
    description: QSPIEN.
    bit_offset: 14
    bit_size: 1
  - name: SDMMC1EN
    description: SDMMC1EN.
    bit_offset: 16
    bit_size: 1
  - name: SDMMC2EN
    description: SDMMC2EN.
    bit_offset: 17
    bit_size: 1
  - name: CRC1EN
    description: CRC1EN.
    bit_offset: 20
    bit_size: 1
  - name: USBHEN
    description: USBHEN.
    bit_offset: 24
    bit_size: 1
fieldset/MP_AHB6LPENCLRR:
  description: This register is used by the MCU in order to clear the PERxLPEN bits.
  fields:
  - name: MDMALPEN
    description: MDMALPEN.
    bit_offset: 0
    bit_size: 1
  - name: GPULPEN
    description: GPULPEN.
    bit_offset: 5
    bit_size: 1
  - name: ETHCKLPEN
    description: ETHCKLPEN.
    bit_offset: 7
    bit_size: 1
  - name: ETHTXLPEN
    description: ETHTXLPEN.
    bit_offset: 8
    bit_size: 1
  - name: ETHRXLPEN
    description: ETHRXLPEN.
    bit_offset: 9
    bit_size: 1
  - name: ETHMACLPEN
    description: ETHMACLPEN.
    bit_offset: 10
    bit_size: 1
  - name: ETHSTPEN
    description: ETHSTPEN.
    bit_offset: 11
    bit_size: 1
  - name: FMCLPEN
    description: FMCLPEN.
    bit_offset: 12
    bit_size: 1
  - name: QSPILPEN
    description: QSPILPEN.
    bit_offset: 14
    bit_size: 1
  - name: SDMMC1LPEN
    description: SDMMC1LPEN.
    bit_offset: 16
    bit_size: 1
  - name: SDMMC2LPEN
    description: SDMMC2LPEN.
    bit_offset: 17
    bit_size: 1
  - name: CRC1LPEN
    description: CRC1LPEN.
    bit_offset: 20
    bit_size: 1
  - name: USBHLPEN
    description: USBHLPEN.
    bit_offset: 24
    bit_size: 1
fieldset/MP_AHB6LPENSETR:
  description: This register is used by the MCU in order to clear the PERxLPEN bits.
  fields:
  - name: MDMALPEN
    description: MDMALPEN.
    bit_offset: 0
    bit_size: 1
  - name: GPULPEN
    description: GPULPEN.
    bit_offset: 5
    bit_size: 1
  - name: ETHCKLPEN
    description: ETHCKLPEN.
    bit_offset: 7
    bit_size: 1
  - name: ETHTXLPEN
    description: ETHTXLPEN.
    bit_offset: 8
    bit_size: 1
  - name: ETHRXLPEN
    description: ETHRXLPEN.
    bit_offset: 9
    bit_size: 1
  - name: ETHMACLPEN
    description: ETHMACLPEN.
    bit_offset: 10
    bit_size: 1
  - name: ETHSTPEN
    description: ETHSTPEN.
    bit_offset: 11
    bit_size: 1
  - name: FMCLPEN
    description: FMCLPEN.
    bit_offset: 12
    bit_size: 1
  - name: QSPILPEN
    description: QSPILPEN.
    bit_offset: 14
    bit_size: 1
  - name: SDMMC1LPEN
    description: SDMMC1LPEN.
    bit_offset: 16
    bit_size: 1
  - name: SDMMC2LPEN
    description: SDMMC2LPEN.
    bit_offset: 17
    bit_size: 1
  - name: CRC1LPEN
    description: CRC1LPEN.
    bit_offset: 20
    bit_size: 1
  - name: USBHLPEN
    description: USBHLPEN.
    bit_offset: 24
    bit_size: 1
fieldset/MP_APB1ENCLRR:
  description: This register is used to clear the peripheral clock enable bit.
  fields:
  - name: TIM2EN
    description: TIM2EN.
    bit_offset: 0
    bit_size: 1
  - name: TIM3EN
    description: TIM3EN.
    bit_offset: 1
    bit_size: 1
  - name: TIM4EN
    description: TIM4EN.
    bit_offset: 2
    bit_size: 1
  - name: TIM5EN
    description: TIM5EN.
    bit_offset: 3
    bit_size: 1
  - name: TIM6EN
    description: TIM6EN.
    bit_offset: 4
    bit_size: 1
  - name: TIM7EN
    description: TIM7EN.
    bit_offset: 5
    bit_size: 1
  - name: TIM12EN
    description: TIM12EN.
    bit_offset: 6
    bit_size: 1
  - name: TIM13EN
    description: TIM13EN.
    bit_offset: 7
    bit_size: 1
  - name: TIM14EN
    description: TIM14EN.
    bit_offset: 8
    bit_size: 1
  - name: LPTIM1EN
    description: LPTIM1EN.
    bit_offset: 9
    bit_size: 1
  - name: SPI2EN
    description: SPI2EN.
    bit_offset: 11
    bit_size: 1
  - name: SPI3EN
    description: SPI3EN.
    bit_offset: 12
    bit_size: 1
  - name: USART2EN
    description: USART2EN.
    bit_offset: 14
    bit_size: 1
  - name: USART3EN
    description: USART3EN.
    bit_offset: 15
    bit_size: 1
  - name: UART4EN
    description: UART4EN.
    bit_offset: 16
    bit_size: 1
  - name: UART5EN
    description: UART5EN.
    bit_offset: 17
    bit_size: 1
  - name: UART7EN
    description: UART7EN.
    bit_offset: 18
    bit_size: 1
  - name: UART8EN
    description: UART8EN.
    bit_offset: 19
    bit_size: 1
  - name: I2C1EN
    description: I2C1EN.
    bit_offset: 21
    bit_size: 1
  - name: I2C2EN
    description: I2C2EN.
    bit_offset: 22
    bit_size: 1
  - name: I2C3EN
    description: I2C3EN.
    bit_offset: 23
    bit_size: 1
  - name: I2C5EN
    description: I2C5EN.
    bit_offset: 24
    bit_size: 1
  - name: SPDIFEN
    description: SPDIFEN.
    bit_offset: 26
    bit_size: 1
  - name: CECEN
    description: CECEN.
    bit_offset: 27
    bit_size: 1
  - name: DAC12EN
    description: DAC12EN.
    bit_offset: 29
    bit_size: 1
  - name: MDIOSEN
    description: MDIOSEN.
    bit_offset: 31
    bit_size: 1
fieldset/MP_APB1ENSETR:
  description: This register is used to set the peripheral clock enable bit.
  fields:
  - name: TIM2EN
    description: TIM2EN.
    bit_offset: 0
    bit_size: 1
  - name: TIM3EN
    description: TIM3EN.
    bit_offset: 1
    bit_size: 1
  - name: TIM4EN
    description: TIM4EN.
    bit_offset: 2
    bit_size: 1
  - name: TIM5EN
    description: TIM5EN.
    bit_offset: 3
    bit_size: 1
  - name: TIM6EN
    description: TIM6EN.
    bit_offset: 4
    bit_size: 1
  - name: TIM7EN
    description: TIM7EN.
    bit_offset: 5
    bit_size: 1
  - name: TIM12EN
    description: TIM12EN.
    bit_offset: 6
    bit_size: 1
  - name: TIM13EN
    description: TIM13EN.
    bit_offset: 7
    bit_size: 1
  - name: TIM14EN
    description: TIM14EN.
    bit_offset: 8
    bit_size: 1
  - name: LPTIM1EN
    description: LPTIM1EN.
    bit_offset: 9
    bit_size: 1
  - name: SPI2EN
    description: SPI2EN.
    bit_offset: 11
    bit_size: 1
  - name: SPI3EN
    description: SPI3EN.
    bit_offset: 12
    bit_size: 1
  - name: USART2EN
    description: USART2EN.
    bit_offset: 14
    bit_size: 1
  - name: USART3EN
    description: USART3EN.
    bit_offset: 15
    bit_size: 1
  - name: UART4EN
    description: UART4EN.
    bit_offset: 16
    bit_size: 1
  - name: UART5EN
    description: UART5EN.
    bit_offset: 17
    bit_size: 1
  - name: UART7EN
    description: UART7EN.
    bit_offset: 18
    bit_size: 1
  - name: UART8EN
    description: UART8EN.
    bit_offset: 19
    bit_size: 1
  - name: I2C1EN
    description: I2C1EN.
    bit_offset: 21
    bit_size: 1
  - name: I2C2EN
    description: I2C2EN.
    bit_offset: 22
    bit_size: 1
  - name: I2C3EN
    description: I2C3EN.
    bit_offset: 23
    bit_size: 1
  - name: I2C5EN
    description: I2C5EN.
    bit_offset: 24
    bit_size: 1
  - name: SPDIFEN
    description: SPDIFEN.
    bit_offset: 26
    bit_size: 1
  - name: CECEN
    description: CECEN.
    bit_offset: 27
    bit_size: 1
  - name: DAC12EN
    description: DAC12EN.
    bit_offset: 29
    bit_size: 1
  - name: MDIOSEN
    description: MDIOSEN.
    bit_offset: 31
    bit_size: 1
fieldset/MP_APB1LPENCLRR:
  description: This register is used by the MPU in order to clear the PERxLPEN bits.
  fields:
  - name: TIM2LPEN
    description: TIM2LPEN.
    bit_offset: 0
    bit_size: 1
  - name: TIM3LPEN
    description: TIM3LPEN.
    bit_offset: 1
    bit_size: 1
  - name: TIM4LPEN
    description: TIM4LPEN.
    bit_offset: 2
    bit_size: 1
  - name: TIM5LPEN
    description: TIM5LPEN.
    bit_offset: 3
    bit_size: 1
  - name: TIM6LPEN
    description: TIM6LPEN.
    bit_offset: 4
    bit_size: 1
  - name: TIM7LPEN
    description: TIM7LPEN.
    bit_offset: 5
    bit_size: 1
  - name: TIM12LPEN
    description: TIM12LPEN.
    bit_offset: 6
    bit_size: 1
  - name: TIM13LPEN
    description: TIM13LPEN.
    bit_offset: 7
    bit_size: 1
  - name: TIM14LPEN
    description: TIM14LPEN.
    bit_offset: 8
    bit_size: 1
  - name: LPTIM1LPEN
    description: LPTIM1LPEN.
    bit_offset: 9
    bit_size: 1
  - name: SPI2LPEN
    description: SPI2LPEN.
    bit_offset: 11
    bit_size: 1
  - name: SPI3LPEN
    description: SPI3LPEN.
    bit_offset: 12
    bit_size: 1
  - name: USART2LPEN
    description: USART2LPEN.
    bit_offset: 14
    bit_size: 1
  - name: USART3LPEN
    description: USART3LPEN.
    bit_offset: 15
    bit_size: 1
  - name: UART4LPEN
    description: UART4LPEN.
    bit_offset: 16
    bit_size: 1
  - name: UART5LPEN
    description: UART5LPEN.
    bit_offset: 17
    bit_size: 1
  - name: UART7LPEN
    description: UART7LPEN.
    bit_offset: 18
    bit_size: 1
  - name: UART8LPEN
    description: UART8LPEN.
    bit_offset: 19
    bit_size: 1
  - name: I2C1LPEN
    description: I2C1LPEN.
    bit_offset: 21
    bit_size: 1
  - name: I2C2LPEN
    description: I2C2LPEN.
    bit_offset: 22
    bit_size: 1
  - name: I2C3LPEN
    description: I2C3LPEN.
    bit_offset: 23
    bit_size: 1
  - name: I2C5LPEN
    description: I2C5LPEN.
    bit_offset: 24
    bit_size: 1
  - name: SPDIFLPEN
    description: SPDIFLPEN.
    bit_offset: 26
    bit_size: 1
  - name: CECLPEN
    description: CECLPEN.
    bit_offset: 27
    bit_size: 1
  - name: DAC12LPEN
    description: DAC12LPEN.
    bit_offset: 29
    bit_size: 1
  - name: MDIOSLPEN
    description: MDIOSLPEN.
    bit_offset: 31
    bit_size: 1
fieldset/MP_APB1LPENSETR:
  description: This register is used by the MCU in order to clear the PERxLPEN bits.
  fields:
  - name: TIM2LPEN
    description: TIM2LPEN.
    bit_offset: 0
    bit_size: 1
  - name: TIM3LPEN
    description: TIM3LPEN.
    bit_offset: 1
    bit_size: 1
  - name: TIM4LPEN
    description: TIM4LPEN.
    bit_offset: 2
    bit_size: 1
  - name: TIM5LPEN
    description: TIM5LPEN.
    bit_offset: 3
    bit_size: 1
  - name: TIM6LPEN
    description: TIM6LPEN.
    bit_offset: 4
    bit_size: 1
  - name: TIM7LPEN
    description: TIM7LPEN.
    bit_offset: 5
    bit_size: 1
  - name: TIM12LPEN
    description: TIM12LPEN.
    bit_offset: 6
    bit_size: 1
  - name: TIM13LPEN
    description: TIM13LPEN.
    bit_offset: 7
    bit_size: 1
  - name: TIM14LPEN
    description: TIM14LPEN.
    bit_offset: 8
    bit_size: 1
  - name: LPTIM1LPEN
    description: LPTIM1LPEN.
    bit_offset: 9
    bit_size: 1
  - name: SPI2LPEN
    description: SPI2LPEN.
    bit_offset: 11
    bit_size: 1
  - name: SPI3LPEN
    description: SPI3LPEN.
    bit_offset: 12
    bit_size: 1
  - name: USART2LPEN
    description: USART2LPEN.
    bit_offset: 14
    bit_size: 1
  - name: USART3LPEN
    description: USART3LPEN.
    bit_offset: 15
    bit_size: 1
  - name: UART4LPEN
    description: UART4LPEN.
    bit_offset: 16
    bit_size: 1
  - name: UART5LPEN
    description: UART5LPEN.
    bit_offset: 17
    bit_size: 1
  - name: UART7LPEN
    description: UART7LPEN.
    bit_offset: 18
    bit_size: 1
  - name: UART8LPEN
    description: UART8LPEN.
    bit_offset: 19
    bit_size: 1
  - name: I2C1LPEN
    description: I2C1LPEN.
    bit_offset: 21
    bit_size: 1
  - name: I2C2LPEN
    description: I2C2LPEN.
    bit_offset: 22
    bit_size: 1
  - name: I2C3LPEN
    description: I2C3LPEN.
    bit_offset: 23
    bit_size: 1
  - name: I2C5LPEN
    description: I2C5LPEN.
    bit_offset: 24
    bit_size: 1
  - name: SPDIFLPEN
    description: SPDIFLPEN.
    bit_offset: 26
    bit_size: 1
  - name: CECLPEN
    description: CECLPEN.
    bit_offset: 27
    bit_size: 1
  - name: DAC12LPEN
    description: DAC12LPEN.
    bit_offset: 29
    bit_size: 1
  - name: MDIOSLPEN
    description: MDIOSLPEN.
    bit_offset: 31
    bit_size: 1
fieldset/MP_APB2ENCLRR:
  description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
  fields:
  - name: TIM1EN
    description: TIM1EN.
    bit_offset: 0
    bit_size: 1
  - name: TIM8EN
    description: TIM8EN.
    bit_offset: 1
    bit_size: 1
  - name: TIM15EN
    description: TIM15EN.
    bit_offset: 2
    bit_size: 1
  - name: TIM16EN
    description: TIM16EN.
    bit_offset: 3
    bit_size: 1
  - name: TIM17EN
    description: TIM17EN.
    bit_offset: 4
    bit_size: 1
  - name: SPI1EN
    description: SPI1EN.
    bit_offset: 8
    bit_size: 1
  - name: SPI4EN
    description: SPI4EN.
    bit_offset: 9
    bit_size: 1
  - name: SPI5EN
    description: SPI5EN.
    bit_offset: 10
    bit_size: 1
  - name: USART6EN
    description: USART6EN.
    bit_offset: 13
    bit_size: 1
  - name: SAI1EN
    description: SAI1EN.
    bit_offset: 16
    bit_size: 1
  - name: SAI2EN
    description: SAI2EN.
    bit_offset: 17
    bit_size: 1
  - name: SAI3EN
    description: SAI3EN.
    bit_offset: 18
    bit_size: 1
  - name: DFSDMEN
    description: DFSDMEN.
    bit_offset: 20
    bit_size: 1
  - name: ADFSDMEN
    description: ADFSDMEN.
    bit_offset: 21
    bit_size: 1
  - name: FDCANEN
    description: FDCANEN.
    bit_offset: 24
    bit_size: 1
fieldset/MP_APB2ENSETR:
  description: This register is used to set the peripheral clock enable bit.
  fields:
  - name: TIM1EN
    description: TIM1EN.
    bit_offset: 0
    bit_size: 1
  - name: TIM8EN
    description: TIM8EN.
    bit_offset: 1
    bit_size: 1
  - name: TIM15EN
    description: TIM15EN.
    bit_offset: 2
    bit_size: 1
  - name: TIM16EN
    description: TIM16EN.
    bit_offset: 3
    bit_size: 1
  - name: TIM17EN
    description: TIM17EN.
    bit_offset: 4
    bit_size: 1
  - name: SPI1EN
    description: SPI1EN.
    bit_offset: 8
    bit_size: 1
  - name: SPI4EN
    description: SPI4EN.
    bit_offset: 9
    bit_size: 1
  - name: SPI5EN
    description: SPI5EN.
    bit_offset: 10
    bit_size: 1
  - name: USART6EN
    description: USART6EN.
    bit_offset: 13
    bit_size: 1
  - name: SAI1EN
    description: SAI1EN.
    bit_offset: 16
    bit_size: 1
  - name: SAI2EN
    description: SAI2EN.
    bit_offset: 17
    bit_size: 1
  - name: SAI3EN
    description: SAI3EN.
    bit_offset: 18
    bit_size: 1
  - name: DFSDMEN
    description: DFSDMEN.
    bit_offset: 20
    bit_size: 1
  - name: ADFSDMEN
    description: ADFSDMEN.
    bit_offset: 21
    bit_size: 1
  - name: FDCANEN
    description: FDCANEN.
    bit_offset: 24
    bit_size: 1
fieldset/MP_APB2LPENCLRR:
  description: This register is used by the MCU in order to clear the PERxLPEN bits.
  fields:
  - name: TIM1LPEN
    description: TIM1LPEN.
    bit_offset: 0
    bit_size: 1
  - name: TIM8LPEN
    description: TIM8LPEN.
    bit_offset: 1
    bit_size: 1
  - name: TIM15LPEN
    description: TIM15LPEN.
    bit_offset: 2
    bit_size: 1
  - name: TIM16LPEN
    description: TIM16LPEN.
    bit_offset: 3
    bit_size: 1
  - name: TIM17LPEN
    description: TIM17LPEN.
    bit_offset: 4
    bit_size: 1
  - name: SPI1LPEN
    description: SPI1LPEN.
    bit_offset: 8
    bit_size: 1
  - name: SPI4LPEN
    description: SPI4LPEN.
    bit_offset: 9
    bit_size: 1
  - name: SPI5LPEN
    description: SPI5LPEN.
    bit_offset: 10
    bit_size: 1
  - name: USART6LPEN
    description: USART6LPEN.
    bit_offset: 13
    bit_size: 1
  - name: SAI1LPEN
    description: SAI1LPEN.
    bit_offset: 16
    bit_size: 1
  - name: SAI2LPEN
    description: SAI2LPEN.
    bit_offset: 17
    bit_size: 1
  - name: SAI3LPEN
    description: SAI3LPEN.
    bit_offset: 18
    bit_size: 1
  - name: DFSDMLPEN
    description: DFSDMLPEN.
    bit_offset: 20
    bit_size: 1
  - name: ADFSDMLPEN
    description: ADFSDMLPEN.
    bit_offset: 21
    bit_size: 1
  - name: FDCANLPEN
    description: FDCANLPEN.
    bit_offset: 24
    bit_size: 1
fieldset/MP_APB2LPENSETR:
  description: This register is used by the MCU in order to clear the PERxLPEN bits.
  fields:
  - name: TIM1LPEN
    description: TIM1LPEN.
    bit_offset: 0
    bit_size: 1
  - name: TIM8LPEN
    description: TIM8LPEN.
    bit_offset: 1
    bit_size: 1
  - name: TIM15LPEN
    description: TIM15LPEN.
    bit_offset: 2
    bit_size: 1
  - name: TIM16LPEN
    description: TIM16LPEN.
    bit_offset: 3
    bit_size: 1
  - name: TIM17LPEN
    description: TIM17LPEN.
    bit_offset: 4
    bit_size: 1
  - name: SPI1LPEN
    description: SPI1LPEN.
    bit_offset: 8
    bit_size: 1
  - name: SPI4LPEN
    description: SPI4LPEN.
    bit_offset: 9
    bit_size: 1
  - name: SPI5LPEN
    description: SPI5LPEN.
    bit_offset: 10
    bit_size: 1
  - name: USART6LPEN
    description: USART6LPEN.
    bit_offset: 13
    bit_size: 1
  - name: SAI1LPEN
    description: SAI1LPEN.
    bit_offset: 16
    bit_size: 1
  - name: SAI2LPEN
    description: SAI2LPEN.
    bit_offset: 17
    bit_size: 1
  - name: SAI3LPEN
    description: SAI3LPEN.
    bit_offset: 18
    bit_size: 1
  - name: DFSDMLPEN
    description: DFSDMLPEN.
    bit_offset: 20
    bit_size: 1
  - name: ADFSDMLPEN
    description: ADFSDMLPEN.
    bit_offset: 21
    bit_size: 1
  - name: FDCANLPEN
    description: FDCANLPEN.
    bit_offset: 24
    bit_size: 1
fieldset/MP_APB3ENCLRR:
  description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
  fields:
  - name: LPTIM2EN
    description: LPTIM2EN.
    bit_offset: 0
    bit_size: 1
  - name: LPTIM3EN
    description: LPTIM3EN.
    bit_offset: 1
    bit_size: 1
  - name: LPTIM4EN
    description: LPTIM4EN.
    bit_offset: 2
    bit_size: 1
  - name: LPTIM5EN
    description: LPTIM5EN.
    bit_offset: 3
    bit_size: 1
  - name: SAI4EN
    description: SAI4EN.
    bit_offset: 8
    bit_size: 1
  - name: SYSCFGEN
    description: SYSCFGEN.
    bit_offset: 11
    bit_size: 1
  - name: VREFEN
    description: VREFEN.
    bit_offset: 13
    bit_size: 1
  - name: DTSEN
    description: DTSEN.
    bit_offset: 16
    bit_size: 1
  - name: HDPEN
    description: HDPEN.
    bit_offset: 20
    bit_size: 1
fieldset/MP_APB3ENSETR:
  description: This register is used to set the peripheral clock enable bit.
  fields:
  - name: LPTIM2EN
    description: LPTIM2EN.
    bit_offset: 0
    bit_size: 1
  - name: LPTIM3EN
    description: LPTIM3EN.
    bit_offset: 1
    bit_size: 1
  - name: LPTIM4EN
    description: LPTIM4EN.
    bit_offset: 2
    bit_size: 1
  - name: LPTIM5EN
    description: LPTIM5EN.
    bit_offset: 3
    bit_size: 1
  - name: SAI4EN
    description: SAI4EN.
    bit_offset: 8
    bit_size: 1
  - name: SYSCFGEN
    description: SYSCFGEN.
    bit_offset: 11
    bit_size: 1
  - name: VREFEN
    description: VREFEN.
    bit_offset: 13
    bit_size: 1
  - name: DTSEN
    description: DTSEN.
    bit_offset: 16
    bit_size: 1
  - name: HDPEN
    description: HDPEN.
    bit_offset: 20
    bit_size: 1
fieldset/MP_APB3LPENCLRR:
  description: This register is used by the MCU in order to clear the PERxLPEN bits.
  fields:
  - name: LPTIM2LPEN
    description: LPTIM2LPEN.
    bit_offset: 0
    bit_size: 1
  - name: LPTIM3LPEN
    description: LPTIM3LPEN.
    bit_offset: 1
    bit_size: 1
  - name: LPTIM4LPEN
    description: LPTIM4LPEN.
    bit_offset: 2
    bit_size: 1
  - name: LPTIM5LPEN
    description: LPTIM5LPEN.
    bit_offset: 3
    bit_size: 1
  - name: SAI4LPEN
    description: SAI4LPEN.
    bit_offset: 8
    bit_size: 1
  - name: SYSCFGLPEN
    description: SYSCFGLPEN.
    bit_offset: 11
    bit_size: 1
  - name: VREFLPEN
    description: VREFLPEN.
    bit_offset: 13
    bit_size: 1
  - name: DTSLPEN
    description: DTSLPEN.
    bit_offset: 16
    bit_size: 1
fieldset/MP_APB3LPENSETR:
  description: This register is used by the MCU in order to clear the PERxLPEN bits.
  fields:
  - name: LPTIM2LPEN
    description: LPTIM2LPEN.
    bit_offset: 0
    bit_size: 1
  - name: LPTIM3LPEN
    description: LPTIM3LPEN.
    bit_offset: 1
    bit_size: 1
  - name: LPTIM4LPEN
    description: LPTIM4LPEN.
    bit_offset: 2
    bit_size: 1
  - name: LPTIM5LPEN
    description: LPTIM5LPEN.
    bit_offset: 3
    bit_size: 1
  - name: SAI4LPEN
    description: SAI4LPEN.
    bit_offset: 8
    bit_size: 1
  - name: SYSCFGLPEN
    description: SYSCFGLPEN.
    bit_offset: 11
    bit_size: 1
  - name: VREFLPEN
    description: VREFLPEN.
    bit_offset: 13
    bit_size: 1
  - name: DTSLPEN
    description: DTSLPEN.
    bit_offset: 16
    bit_size: 1
fieldset/MP_APB4ENCLRR:
  description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to.
  fields:
  - name: LTDCEN
    description: LTDCEN.
    bit_offset: 0
    bit_size: 1
  - name: DSIEN
    description: DSIEN.
    bit_offset: 4
    bit_size: 1
  - name: DDRPERFMEN
    description: DDRPERFMEN.
    bit_offset: 8
    bit_size: 1
  - name: IWDG2APBEN
    description: IWDG2APBEN.
    bit_offset: 15
    bit_size: 1
  - name: USBPHYEN
    description: USBPHYEN.
    bit_offset: 16
    bit_size: 1
  - name: STGENROEN
    description: STGENROEN.
    bit_offset: 20
    bit_size: 1
fieldset/MP_APB4ENSETR:
  description: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to.
  fields:
  - name: LTDCEN
    description: LTDCEN.
    bit_offset: 0
    bit_size: 1
  - name: DSIEN
    description: DSIEN.
    bit_offset: 4
    bit_size: 1
  - name: DDRPERFMEN
    description: DDRPERFMEN.
    bit_offset: 8
    bit_size: 1
  - name: IWDG2APBEN
    description: IWDG2APBEN.
    bit_offset: 15
    bit_size: 1
  - name: USBPHYEN
    description: USBPHYEN.
    bit_offset: 16
    bit_size: 1
  - name: STGENROEN
    description: STGENROEN.
    bit_offset: 20
    bit_size: 1
fieldset/MP_APB4LPENCLRR:
  description: This register is used by the MCU.
  fields:
  - name: LTDCLPEN
    description: LTDCLPEN.
    bit_offset: 0
    bit_size: 1
  - name: DSILPEN
    description: DSILPEN.
    bit_offset: 4
    bit_size: 1
  - name: DDRPERFMLPEN
    description: DDRPERFMLPEN.
    bit_offset: 8
    bit_size: 1
  - name: IWDG2APBLPEN
    description: IWDG2APBLPEN.
    bit_offset: 15
    bit_size: 1
  - name: USBPHYLPEN
    description: USBPHYLPEN.
    bit_offset: 16
    bit_size: 1
  - name: STGENROLPEN
    description: STGENROLPEN.
    bit_offset: 20
    bit_size: 1
  - name: STGENROSTPEN
    description: STGENROSTPEN.
    bit_offset: 21
    bit_size: 1
fieldset/MP_APB4LPENSETR:
  description: This register is used by the MCU in order to clear the PERxLPEN bits.
  fields:
  - name: LTDCLPEN
    description: LTDCLPEN.
    bit_offset: 0
    bit_size: 1
  - name: DSILPEN
    description: DSILPEN.
    bit_offset: 4
    bit_size: 1
  - name: DDRPERFMLPEN
    description: DDRPERFMLPEN.
    bit_offset: 8
    bit_size: 1
  - name: IWDG2APBLPEN
    description: IWDG2APBLPEN.
    bit_offset: 15
    bit_size: 1
  - name: USBPHYLPEN
    description: USBPHYLPEN.
    bit_offset: 16
    bit_size: 1
  - name: STGENROLPEN
    description: STGENROLPEN.
    bit_offset: 20
    bit_size: 1
  - name: STGENROSTPEN
    description: STGENROSTPEN.
    bit_offset: 21
    bit_size: 1
fieldset/MP_APB5ENCLRR:
  description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to.
  fields:
  - name: SPI6EN
    description: SPI6EN.
    bit_offset: 0
    bit_size: 1
  - name: I2C4EN
    description: I2C4EN.
    bit_offset: 2
    bit_size: 1
  - name: I2C6EN
    description: I2C6EN.
    bit_offset: 3
    bit_size: 1
  - name: USART1EN
    description: USART1EN.
    bit_offset: 4
    bit_size: 1
  - name: RTCAPBEN
    description: RTCAPBEN.
    bit_offset: 8
    bit_size: 1
  - name: TZC1EN
    description: TZC1EN.
    bit_offset: 11
    bit_size: 1
  - name: TZC2EN
    description: TZC2EN.
    bit_offset: 12
    bit_size: 1
  - name: TZPCEN
    description: TZPCEN.
    bit_offset: 13
    bit_size: 1
  - name: IWDG1APBEN
    description: IWDG1APBEN.
    bit_offset: 15
    bit_size: 1
  - name: BSECEN
    description: BSECEN.
    bit_offset: 16
    bit_size: 1
  - name: STGENEN
    description: STGENEN.
    bit_offset: 20
    bit_size: 1
fieldset/MP_APB5ENSETR:
  description: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to.
  fields:
  - name: SPI6EN
    description: SPI6EN.
    bit_offset: 0
    bit_size: 1
  - name: I2C4EN
    description: I2C4EN.
    bit_offset: 2
    bit_size: 1
  - name: I2C6EN
    description: I2C6EN.
    bit_offset: 3
    bit_size: 1
  - name: USART1EN
    description: USART1EN.
    bit_offset: 4
    bit_size: 1
  - name: RTCAPBEN
    description: RTCAPBEN.
    bit_offset: 8
    bit_size: 1
  - name: TZC1EN
    description: TZC1EN.
    bit_offset: 11
    bit_size: 1
  - name: TZC2EN
    description: TZC2EN.
    bit_offset: 12
    bit_size: 1
  - name: TZPCEN
    description: TZPCEN.
    bit_offset: 13
    bit_size: 1
  - name: IWDG1APBEN
    description: IWDG1APBEN.
    bit_offset: 15
    bit_size: 1
  - name: BSECEN
    description: BSECEN.
    bit_offset: 16
    bit_size: 1
  - name: STGENEN
    description: STGENEN.
    bit_offset: 20
    bit_size: 1
fieldset/MP_APB5LPENCLRR:
  description: This register is used by the Mpu.
  fields:
  - name: SPI6LPEN
    description: SPI6LPEN.
    bit_offset: 0
    bit_size: 1
  - name: I2C4LPEN
    description: I2C4LPEN.
    bit_offset: 2
    bit_size: 1
  - name: I2C6LPEN
    description: I2C6LPEN.
    bit_offset: 3
    bit_size: 1
  - name: USART1LPEN
    description: USART1LPEN.
    bit_offset: 4
    bit_size: 1
  - name: RTCAPBLPEN
    description: RTCAPBLPEN.
    bit_offset: 8
    bit_size: 1
  - name: TZC1LPEN
    description: TZC1LPEN.
    bit_offset: 11
    bit_size: 1
  - name: TZC2LPEN
    description: TZC2LPEN.
    bit_offset: 12
    bit_size: 1
  - name: TZPCLPEN
    description: TZPCLPEN.
    bit_offset: 13
    bit_size: 1
  - name: IWDG1APBLPEN
    description: IWDG1APBLPEN.
    bit_offset: 15
    bit_size: 1
  - name: BSECLPEN
    description: BSECLPEN.
    bit_offset: 16
    bit_size: 1
  - name: STGENLPEN
    description: STGENLPEN.
    bit_offset: 20
    bit_size: 1
  - name: STGENSTPEN
    description: STGENSTPEN.
    bit_offset: 21
    bit_size: 1
fieldset/MP_APB5LPENSETR:
  description: This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: SPI6LPEN
    description: SPI6LPEN.
    bit_offset: 0
    bit_size: 1
  - name: I2C4LPEN
    description: I2C4LPEN.
    bit_offset: 2
    bit_size: 1
  - name: I2C6LPEN
    description: I2C6LPEN.
    bit_offset: 3
    bit_size: 1
  - name: USART1LPEN
    description: USART1LPEN.
    bit_offset: 4
    bit_size: 1
  - name: RTCAPBLPEN
    description: RTCAPBLPEN.
    bit_offset: 8
    bit_size: 1
  - name: TZC1LPEN
    description: TZC1LPEN.
    bit_offset: 11
    bit_size: 1
  - name: TZC2LPEN
    description: TZC2LPEN.
    bit_offset: 12
    bit_size: 1
  - name: TZPCLPEN
    description: TZPCLPEN.
    bit_offset: 13
    bit_size: 1
  - name: IWDG1APBLPEN
    description: IWDG1APBLPEN.
    bit_offset: 15
    bit_size: 1
  - name: BSECLPEN
    description: BSECLPEN.
    bit_offset: 16
    bit_size: 1
  - name: STGENLPEN
    description: STGENLPEN.
    bit_offset: 20
    bit_size: 1
  - name: STGENSTPEN
    description: STGENSTPEN.
    bit_offset: 21
    bit_size: 1
fieldset/MP_APRSTCR:
  description: This register is used to control the behavior of the warm reset. If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: RDCTLEN
    description: RDCTLEN.
    bit_offset: 0
    bit_size: 1
  - name: RSTTO
    description: RSTTO.
    bit_offset: 8
    bit_size: 7
fieldset/MP_APRSTSR:
  description: This register provides a status of the RDCTL. If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: RSTTOV
    description: RSTTOV.
    bit_offset: 8
    bit_size: 7
fieldset/MP_AXIMLPENCLRR:
  description: This register is used by the MPU.
  fields:
  - name: SYSRAMLPEN
    description: SYSRAMLPEN.
    bit_offset: 0
    bit_size: 1
fieldset/MP_AXIMLPENSETR:
  description: This register is used by the MPU.
  fields:
  - name: SYSRAMLPEN
    description: SYSRAMLPEN.
    bit_offset: 0
    bit_size: 1
fieldset/MP_BOOTCR:
  description: 'This register is used to control the HOLD boot function when the system exits from Standby. Refer to Section: MCU HOLD_BOOT after processor reset. This register is reset when a system reset occurs, but not when the circuit exits from Standby (app_rst reset).If TZEN = , this register can only be modified in secure mode. This register can only be accessed by the MPU.'
  fields:
  - name: MCU_BEN
    description: MCU_BEN.
    bit_offset: 0
    bit_size: 1
  - name: MPU_BEN
    description: MPU_BEN.
    bit_offset: 1
    bit_size: 1
fieldset/MP_CIER:
  description: 'This register shall be used by the MPU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode.'
  fields:
  - name: LSIRDYIE
    description: LSIRDYIE.
    bit_offset: 0
    bit_size: 1
  - name: LSERDYIE
    description: LSERDYIE.
    bit_offset: 1
    bit_size: 1
  - name: HSIRDYIE
    description: HSIRDYIE.
    bit_offset: 2
    bit_size: 1
  - name: HSERDYIE
    description: HSERDYIE.
    bit_offset: 3
    bit_size: 1
  - name: CSIRDYIE
    description: CSIRDYIE.
    bit_offset: 4
    bit_size: 1
  - name: PLL1DYIE
    description: PLL1DYIE.
    bit_offset: 8
    bit_size: 1
  - name: PLL2DYIE
    description: PLL2DYIE.
    bit_offset: 9
    bit_size: 1
  - name: PLL3DYIE
    description: PLL3DYIE.
    bit_offset: 10
    bit_size: 1
  - name: PLL4DYIE
    description: PLL4DYIE.
    bit_offset: 11
    bit_size: 1
  - name: LSECSSIE
    description: LSECSSIE.
    bit_offset: 16
    bit_size: 1
  - name: WKUPIE
    description: WKUPIE.
    bit_offset: 20
    bit_size: 1
fieldset/MP_CIFR:
  description: 'This register shall be used by the MPU in order to read and clear the interrupt flags.Writing has no effect, writing will clear the corresponding flag.Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode.'
  fields:
  - name: LSIRDYF
    description: LSIRDYF.
    bit_offset: 0
    bit_size: 1
  - name: LSERDYF
    description: LSERDYF.
    bit_offset: 1
    bit_size: 1
  - name: HSIRDYF
    description: HSIRDYF.
    bit_offset: 2
    bit_size: 1
  - name: HSERDYF
    description: HSERDYF.
    bit_offset: 3
    bit_size: 1
  - name: CSIRDYF
    description: CSIRDYF.
    bit_offset: 4
    bit_size: 1
  - name: PLL1DYF
    description: PLL1DYF.
    bit_offset: 8
    bit_size: 1
  - name: PLL2DYF
    description: PLL2DYF.
    bit_offset: 9
    bit_size: 1
  - name: PLL3DYF
    description: PLL3DYF.
    bit_offset: 10
    bit_size: 1
  - name: PLL4DYF
    description: PLL4DYF.
    bit_offset: 11
    bit_size: 1
  - name: LSECSSF
    description: LSECSSF.
    bit_offset: 16
    bit_size: 1
  - name: WKUPF
    description: WKUPF.
    bit_offset: 20
    bit_size: 1
fieldset/MP_GCR:
  description: The register contains global control bits. If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: BOOT_MCU
    description: BOOT_MCU.
    bit_offset: 0
    bit_size: 1
fieldset/MP_GRSTCSETR:
  description: This register is used by the MPU in order to generate either a MCU reset or a system reset or a reset of one of the two MPU processors. Writing has no effect, reading returns the effective values of the corresponding bits. Writing a activates the reset.
  fields:
  - name: MPSYSRST
    description: MPSYSRST.
    bit_offset: 0
    bit_size: 1
  - name: MCURST
    description: MCURST.
    bit_offset: 1
    bit_size: 1
  - name: MPUP0RST
    description: MPUP0RST.
    bit_offset: 4
    bit_size: 1
  - name: MPUP1RST
    description: MPUP1RST.
    bit_offset: 5
    bit_size: 1
fieldset/MP_IWDGFZCLRR:
  description: This register is used by the BOOTROM in order to unfreeze the IWDGs clocks. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: FZ_IWDG1
    description: FZ_IWDG1.
    bit_offset: 0
    bit_size: 1
  - name: FZ_IWDG2
    description: FZ_IWDG2.
    bit_offset: 1
    bit_size: 1
fieldset/MP_IWDGFZSETR:
  description: This register is used by the BOOTROM in order to freeze the IWDGs clocks. After a system reset or Standby reset (nreset), or a CStandby reset (cstby_rst) the MPU is allowed to write it once.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: FZ_IWDG1
    description: FZ_IWDG1.
    bit_offset: 0
    bit_size: 1
  - name: FZ_IWDG2
    description: FZ_IWDG2.
    bit_offset: 1
    bit_size: 1
fieldset/MP_MLAHBENCLRR:
  description: This register is used to clear the peripheral clock enable bit.
  fields:
  - name: RETRAMEN
    description: RETRAMEN.
    bit_offset: 4
    bit_size: 1
fieldset/MP_MLAHBENSETR:
  description: This register is used to set the peripheral clock enable bit.
  fields:
  - name: RETRAMEN
    description: RETRAMEN.
    bit_offset: 4
    bit_size: 1
fieldset/MP_MLAHBLPENCLRR:
  description: This register is used by the MPU in order to clear the PERxLPEN bit.
  fields:
  - name: SRAM1LPEN
    description: SRAM1LPEN.
    bit_offset: 0
    bit_size: 1
  - name: SRAM2LPEN
    description: SRAM2LPEN.
    bit_offset: 1
    bit_size: 1
  - name: SRAM34LPEN
    description: SRAM34LPEN.
    bit_offset: 2
    bit_size: 1
  - name: RETRAMLPEN
    description: RETRAMLPEN.
    bit_offset: 4
    bit_size: 1
fieldset/MP_MLAHBLPENSETR:
  description: This register is used by the MPU in order to set the PERxLPEN bit.
  fields:
  - name: SRAM1LPEN
    description: SRAM1LPEN.
    bit_offset: 0
    bit_size: 1
  - name: SRAM2LPEN
    description: SRAM2LPEN.
    bit_offset: 1
    bit_size: 1
  - name: SRAM34LPEN
    description: SRAM34LPEN.
    bit_offset: 2
    bit_size: 1
  - name: RETRAMLPEN
    description: RETRAMLPEN.
    bit_offset: 4
    bit_size: 1
fieldset/MP_RSTSCLRR:
  description: 'This register is used by the MPU to check the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode.'
  fields:
  - name: PORRSTF
    description: PORRSTF.
    bit_offset: 0
    bit_size: 1
  - name: BORRSTF
    description: BORRSTF.
    bit_offset: 1
    bit_size: 1
  - name: PADRSTF
    description: PADRSTF.
    bit_offset: 2
    bit_size: 1
  - name: HCSSRSTF
    description: HCSSRSTF.
    bit_offset: 3
    bit_size: 1
  - name: VCORERSTF
    description: VCORERSTF.
    bit_offset: 4
    bit_size: 1
  - name: MPSYSRSTF
    description: MPSYSRSTF.
    bit_offset: 6
    bit_size: 1
  - name: MCSYSRSTF
    description: MCSYSRSTF.
    bit_offset: 7
    bit_size: 1
  - name: IWDG1RSTF
    description: IWDG1RSTF.
    bit_offset: 8
    bit_size: 1
  - name: IWDG2RSTF
    description: IWDG2RSTF.
    bit_offset: 9
    bit_size: 1
  - name: STDBYRSTF
    description: STDBYRSTF.
    bit_offset: 11
    bit_size: 1
  - name: CSTDBYRSTF
    description: CSTDBYRSTF.
    bit_offset: 12
    bit_size: 1
  - name: MPUP0RSTF
    description: MPUP0RSTF.
    bit_offset: 13
    bit_size: 1
  - name: MPUP1RSTF
    description: MPUP1RSTF.
    bit_offset: 14
    bit_size: 1
  - name: SPARE
    description: SPARE.
    bit_offset: 15
    bit_size: 1
fieldset/MP_RSTSSETR:
  description: 'This register is dedicated to the BOOTROM code in order to update the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby. The application software shall not use this register. In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR).Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode.'
  fields:
  - name: PORRSTF
    description: PORRSTF.
    bit_offset: 0
    bit_size: 1
  - name: BORRSTF
    description: BORRSTF.
    bit_offset: 1
    bit_size: 1
  - name: PADRSTF
    description: PADRSTF.
    bit_offset: 2
    bit_size: 1
  - name: HCSSRSTF
    description: HCSSRSTF.
    bit_offset: 3
    bit_size: 1
  - name: VCORERSTF
    description: VCORERSTF.
    bit_offset: 4
    bit_size: 1
  - name: MPSYSRSTF
    description: MPSYSRSTF.
    bit_offset: 6
    bit_size: 1
  - name: MCSYSRSTF
    description: MCSYSRSTF.
    bit_offset: 7
    bit_size: 1
  - name: IWDG1RSTF
    description: IWDG1RSTF.
    bit_offset: 8
    bit_size: 1
  - name: IWDG2RSTF
    description: IWDG2RSTF.
    bit_offset: 9
    bit_size: 1
  - name: STDBYRSTF
    description: STDBYRSTF.
    bit_offset: 11
    bit_size: 1
  - name: CSTDBYRSTF
    description: CSTDBYRSTF.
    bit_offset: 12
    bit_size: 1
  - name: MPUP0RSTF
    description: MPUP0RSTF.
    bit_offset: 13
    bit_size: 1
  - name: MPUP1RSTF
    description: MPUP1RSTF.
    bit_offset: 14
    bit_size: 1
  - name: SPARE
    description: SPARE.
    bit_offset: 15
    bit_size: 1
fieldset/MP_SREQCLRR:
  description: Writing has no effect, reading will return the effective values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: STPREQ_P0
    description: STPREQ_P0.
    bit_offset: 0
    bit_size: 1
  - name: STPREQ_P1
    description: STPREQ_P1.
    bit_offset: 1
    bit_size: 1
fieldset/MP_SREQSETR:
  description: Writing has no effect, reading will return the values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: STPREQ_P0
    description: STPREQ_P0.
    bit_offset: 0
    bit_size: 1
  - name: STPREQ_P1
    description: STPREQ_P1.
    bit_offset: 1
    bit_size: 1
fieldset/MP_TZAHB6ENCLRR:
  description: This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: MDMAEN
    description: MDMAEN.
    bit_offset: 0
    bit_size: 1
fieldset/MP_TZAHB6ENSETR:
  description: This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: MDMAEN
    description: MDMAEN.
    bit_offset: 0
    bit_size: 1
fieldset/MP_TZAHB6LPENCLRR:
  description: This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: MDMALPEN
    description: MDMALPEN.
    bit_offset: 0
    bit_size: 1
fieldset/MP_TZAHB6LPENSETR:
  description: This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: MDMALPEN
    description: MDMALPEN.
    bit_offset: 0
    bit_size: 1
fieldset/MSSCKSELR:
  description: 'This register is used to select the clock source for the MCU sub-system, including the MCU itself. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
  fields:
  - name: MCUSSRC
    description: MCUSSRC.
    bit_offset: 0
    bit_size: 2
  - name: MCUSSRCRDY
    description: MCUSSRCRDY.
    bit_offset: 31
    bit_size: 1
fieldset/OCENCLRR:
  description: 'This register is used to control the oscillators.Writing to this register has no effect, writing will clear the corresponding bits. Reading will give the effective values of the enable bits.If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
  fields:
  - name: HSION
    description: HSION.
    bit_offset: 0
    bit_size: 1
  - name: HSIKERON
    description: HSIKERON.
    bit_offset: 1
    bit_size: 1
  - name: CSION
    description: CSION.
    bit_offset: 4
    bit_size: 1
  - name: CSIKERON
    description: CSIKERON.
    bit_offset: 5
    bit_size: 1
  - name: DIGBYP
    description: DIGBYP.
    bit_offset: 7
    bit_size: 1
  - name: HSEON
    description: HSEON.
    bit_offset: 8
    bit_size: 1
  - name: HSEKERON
    description: HSEKERON.
    bit_offset: 9
    bit_size: 1
  - name: HSEBYP
    description: HSEBYP.
    bit_offset: 10
    bit_size: 1
fieldset/OCENSETR:
  description: 'This register is used to control the oscillators.Writing to this register has no effect, writing will set the corresponding bits. Reading will give the effective values of each bit.If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
  fields:
  - name: HSION
    description: HSION.
    bit_offset: 0
    bit_size: 1
  - name: HSIKERON
    description: HSIKERON.
    bit_offset: 1
    bit_size: 1
  - name: CSION
    description: CSION.
    bit_offset: 4
    bit_size: 1
  - name: CSIKERON
    description: CSIKERON.
    bit_offset: 5
    bit_size: 1
  - name: DIGBYP
    description: DIGBYP.
    bit_offset: 7
    bit_size: 1
  - name: HSEON
    description: HSEON.
    bit_offset: 8
    bit_size: 1
  - name: HSEKERON
    description: HSEKERON.
    bit_offset: 9
    bit_size: 1
  - name: HSEBYP
    description: HSEBYP.
    bit_offset: 10
    bit_size: 1
  - name: HSECSSON
    description: HSECSSON.
    bit_offset: 11
    bit_size: 1
fieldset/OCRDYR:
  description: This is a read-only access register, It contains the status flags of oscillators. Writing has no effect.
  fields:
  - name: HSIRDY
    description: HSIRDY.
    bit_offset: 0
    bit_size: 1
  - name: HSIDIVRDY
    description: HSIDIVRDY.
    bit_offset: 2
    bit_size: 1
  - name: CSIRDY
    description: CSIRDY.
    bit_offset: 4
    bit_size: 1
  - name: HSERDY
    description: HSERDY.
    bit_offset: 8
    bit_size: 1
  - name: MPUCKRDY
    description: MPUCKRDY.
    bit_offset: 23
    bit_size: 1
  - name: AXICKRDY
    description: AXICKRDY.
    bit_offset: 24
    bit_size: 1
  - name: CKREST
    description: CKREST.
    bit_offset: 25
    bit_size: 1
fieldset/PLL1CFGR1:
  description: 'This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
  fields:
  - name: DIVN
    description: DIVN.
    bit_offset: 0
    bit_size: 9
  - name: DIVM1
    description: DIVM1.
    bit_offset: 16
    bit_size: 6
fieldset/PLL1CFGR2:
  description: 'This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
  fields:
  - name: DIVP
    description: DIVP.
    bit_offset: 0
    bit_size: 7
  - name: DIVQ
    description: DIVQ.
    bit_offset: 8
    bit_size: 7
  - name: DIVR
    description: DIVR.
    bit_offset: 16
    bit_size: 7
fieldset/PLL1CR:
  description: 'This register is used to control the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
  fields:
  - name: PLLON
    description: PLLON.
    bit_offset: 0
    bit_size: 1
  - name: PLL1RDY
    description: PLL1RDY.
    bit_offset: 1
    bit_size: 1
  - name: SSCG_CTRL
    description: SSCG_CTRL.
    bit_offset: 2
    bit_size: 1
  - name: DIVPEN
    description: DIVPEN.
    bit_offset: 4
    bit_size: 1
  - name: DIVQEN
    description: DIVQEN.
    bit_offset: 5
    bit_size: 1
  - name: DIVREN
    description: DIVREN.
    bit_offset: 6
    bit_size: 1
fieldset/PLL1CSGR:
  description: 'This register is used to configure the PLL1.It is not recommended to change the content of this register when the PLL1 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
  fields:
  - name: MOD_PER
    description: MOD_PER.
    bit_offset: 0
    bit_size: 13
  - name: TPDFN_DIS
    description: TPDFN_DIS.
    bit_offset: 13
    bit_size: 1
  - name: RPDFN_DIS
    description: RPDFN_DIS.
    bit_offset: 14
    bit_size: 1
  - name: SSCG_MODE
    description: SSCG_MODE.
    bit_offset: 15
    bit_size: 1
  - name: INC_STEP
    description: INC_STEP.
    bit_offset: 16
    bit_size: 15
fieldset/PLL1FRACR:
  description: 'This register is used to fine-tune the frequency of the PLL1 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
  fields:
  - name: FRACV
    description: FRACV.
    bit_offset: 3
    bit_size: 13
  - name: FRACLE
    description: FRACLE.
    bit_offset: 16
    bit_size: 1
fieldset/PLL2CFGR1:
  description: 'This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
  fields:
  - name: DIVN
    description: DIVN.
    bit_offset: 0
    bit_size: 9
  - name: DIVM2
    description: DIVM2.
    bit_offset: 16
    bit_size: 6
fieldset/PLL2CFGR2:
  description: 'This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
  fields:
  - name: DIVP
    description: DIVP.
    bit_offset: 0
    bit_size: 7
  - name: DIVQ
    description: DIVQ.
    bit_offset: 8
    bit_size: 7
  - name: DIVR
    description: DIVR.
    bit_offset: 16
    bit_size: 7
fieldset/PLL2CR:
  description: 'This register is used to control the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
  fields:
  - name: PLLON
    description: PLLON.
    bit_offset: 0
    bit_size: 1
  - name: PLL2RDY
    description: PLL2RDY.
    bit_offset: 1
    bit_size: 1
  - name: SSCG_CTRL
    description: SSCG_CTRL.
    bit_offset: 2
    bit_size: 1
  - name: DIVPEN
    description: DIVPEN.
    bit_offset: 4
    bit_size: 1
  - name: DIVQEN
    description: DIVQEN.
    bit_offset: 5
    bit_size: 1
  - name: DIVREN
    description: DIVREN.
    bit_offset: 6
    bit_size: 1
fieldset/PLL2CSGR:
  description: 'This register is used to configure the PLL2. It is not recommended to change the content of this register when the PLL2 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
  fields:
  - name: MOD_PER
    description: MOD_PER.
    bit_offset: 0
    bit_size: 13
  - name: TPDFN_DIS
    description: TPDFN_DIS.
    bit_offset: 13
    bit_size: 1
  - name: RPDFN_DIS
    description: RPDFN_DIS.
    bit_offset: 14
    bit_size: 1
  - name: SSCG_MODE
    description: SSCG_MODE.
    bit_offset: 15
    bit_size: 1
  - name: INC_STEP
    description: INC_STEP.
    bit_offset: 16
    bit_size: 15
fieldset/PLL2FRACR:
  description: 'This register is used to fine-tune the frequency of the PLL2 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
  fields:
  - name: FRACV
    description: FRACV.
    bit_offset: 3
    bit_size: 13
  - name: FRACLE
    description: FRACLE.
    bit_offset: 16
    bit_size: 1
fieldset/PLL3CFGR1:
  description: This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
  fields:
  - name: DIVN
    description: DIVN.
    bit_offset: 0
    bit_size: 9
  - name: DIVM3
    description: DIVM3.
    bit_offset: 16
    bit_size: 6
  - name: IFRGE
    description: IFRGE.
    bit_offset: 24
    bit_size: 2
fieldset/PLL3CFGR2:
  description: This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
  fields:
  - name: DIVP
    description: DIVP.
    bit_offset: 0
    bit_size: 7
  - name: DIVQ
    description: DIVQ.
    bit_offset: 8
    bit_size: 7
  - name: DIVR
    description: DIVR.
    bit_offset: 16
    bit_size: 7
fieldset/PLL3CR:
  description: This register is used to control the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
  fields:
  - name: PLLON
    description: PLLON.
    bit_offset: 0
    bit_size: 1
  - name: PLL3RDY
    description: PLL3RDY.
    bit_offset: 1
    bit_size: 1
  - name: SSCG_CTRL
    description: SSCG_CTRL.
    bit_offset: 2
    bit_size: 1
  - name: DIVPEN
    description: DIVPEN.
    bit_offset: 4
    bit_size: 1
  - name: DIVQEN
    description: DIVQEN.
    bit_offset: 5
    bit_size: 1
  - name: DIVREN
    description: DIVREN.
    bit_offset: 6
    bit_size: 1
fieldset/PLL3CSGR:
  description: 'This register is used to configure the PLL3.It is not recommended to change the content of this register when the PLL3 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode.'
  fields:
  - name: MOD_PER
    description: MOD_PER.
    bit_offset: 0
    bit_size: 13
  - name: TPDFN_DIS
    description: TPDFN_DIS.
    bit_offset: 13
    bit_size: 1
  - name: RPDFN_DIS
    description: RPDFN_DIS.
    bit_offset: 14
    bit_size: 1
  - name: SSCG_MODE
    description: SSCG_MODE.
    bit_offset: 15
    bit_size: 1
  - name: INC_STEP
    description: INC_STEP.
    bit_offset: 16
    bit_size: 15
fieldset/PLL3FRACR:
  description: This register is used to fine-tune the frequency of the PLL3 VCO. If TZEN = MCKPROT = , this register can only be modified in secure mode.
  fields:
  - name: FRACV
    description: FRACV.
    bit_offset: 3
    bit_size: 13
  - name: FRACLE
    description: FRACLE.
    bit_offset: 16
    bit_size: 1
fieldset/PLL4CFGR1:
  description: This register is used to configure the PLL4.
  fields:
  - name: DIVN
    description: DIVN.
    bit_offset: 0
    bit_size: 9
  - name: DIVM4
    description: DIVM4.
    bit_offset: 16
    bit_size: 6
  - name: IFRGE
    description: IFRGE.
    bit_offset: 24
    bit_size: 2
fieldset/PLL4CFGR2:
  description: This register is used to configure the PLL4.
  fields:
  - name: DIVP
    description: DIVP.
    bit_offset: 0
    bit_size: 7
  - name: DIVQ
    description: DIVQ.
    bit_offset: 8
    bit_size: 7
  - name: DIVR
    description: DIVR.
    bit_offset: 16
    bit_size: 7
fieldset/PLL4CR:
  description: This register is used to control the PLL4.
  fields:
  - name: PLLON
    description: PLLON.
    bit_offset: 0
    bit_size: 1
  - name: PLL4RDY
    description: PLL4RDY.
    bit_offset: 1
    bit_size: 1
  - name: SSCG_CTRL
    description: SSCG_CTRL.
    bit_offset: 2
    bit_size: 1
  - name: DIVPEN
    description: DIVPEN.
    bit_offset: 4
    bit_size: 1
  - name: DIVQEN
    description: DIVQEN.
    bit_offset: 5
    bit_size: 1
  - name: DIVREN
    description: DIVREN.
    bit_offset: 6
    bit_size: 1
fieldset/PLL4CSGR:
  description: 'This register is used to configure the PLL4.It is not recommended to change the content of this register when the PLL4 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode.'
  fields:
  - name: MOD_PER
    description: MOD_PER.
    bit_offset: 0
    bit_size: 13
  - name: TPDFN_DIS
    description: TPDFN_DIS.
    bit_offset: 13
    bit_size: 1
  - name: RPDFN_DIS
    description: RPDFN_DIS.
    bit_offset: 14
    bit_size: 1
  - name: SSCG_MODE
    description: SSCG_MODE.
    bit_offset: 15
    bit_size: 1
  - name: INC_STEP
    description: INC_STEP.
    bit_offset: 16
    bit_size: 15
fieldset/PLL4FRACR:
  description: This register is used to fine-tune the frequency of the PLL4 VCO.
  fields:
  - name: FRACV
    description: FRACV.
    bit_offset: 3
    bit_size: 13
  - name: FRACLE
    description: FRACLE.
    bit_offset: 16
    bit_size: 1
fieldset/PWRLPDLYCR:
  description: This register is used to program the delay between the moment where the system exits from one of the Stop modes, and the moment where it is allowed to enable the PLLs and provide a clock to bridges and processors. If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: PWRLP_DLY
    description: PWRLP_DLY.
    bit_offset: 0
    bit_size: 22
  - name: MCTMPSKP
    description: MCTMPSKP.
    bit_offset: 24
    bit_size: 1
fieldset/QSPICKSELR:
  description: 'This register is used to control the selection of the kernel clock for the QUADSPI. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: QSPISRC
    description: QSPISRC.
    bit_offset: 0
    bit_size: 2
fieldset/RCK12SELR:
  description: 'This register is used to select the reference clock for PLL1 and PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.'
  fields:
  - name: PLL12SRC
    description: PLL12SRC.
    bit_offset: 0
    bit_size: 2
  - name: PLL12SRCRDY
    description: PLL12SRCRDY.
    bit_offset: 31
    bit_size: 1
fieldset/RCK3SELR:
  description: This register is used to select the reference clock for PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
  fields:
  - name: PLL3SRC
    description: PLL3SRC.
    bit_offset: 0
    bit_size: 2
  - name: PLL3SRCRDY
    description: PLL3SRCRDY.
    bit_offset: 31
    bit_size: 1
fieldset/RCK4SELR:
  description: This register is used to select the reference clock for PLL4.
  fields:
  - name: PLL4SRC
    description: PLL4SRC.
    bit_offset: 0
    bit_size: 2
  - name: PLL4SRCRDY
    description: PLL4SRCRDY.
    bit_offset: 31
    bit_size: 1
fieldset/RDLSICR:
  description: This register is used to control the minimum NRST active duration and LSI function.0 to 7 wait states are inserted for word, half-word and byte accesses. Wait states are inserted in case of successive accesses to this register.This register is reset by the por_rst reset, and it is located into the VDD domain. If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: LSION
    description: LSION.
    bit_offset: 0
    bit_size: 1
  - name: LSIRDY
    description: LSIRDY.
    bit_offset: 1
    bit_size: 1
  - name: MRD
    description: MRD.
    bit_offset: 16
    bit_size: 5
  - name: EADLY
    description: EADLY.
    bit_offset: 24
    bit_size: 3
  - name: SPARE
    description: SPARE.
    bit_offset: 27
    bit_size: 5
fieldset/RNG1CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the RNG1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.'
  fields:
  - name: RNG1SRC
    description: RNG1SRC.
    bit_offset: 0
    bit_size: 2
fieldset/RNG2CKSELR:
  description: This register is used to control the selection of the kernel clock for the RNG2.
  fields:
  - name: RNG2SRC
    description: RNG2SRC.
    bit_offset: 0
    bit_size: 2
fieldset/RTCDIVR:
  description: This register is used to divide the HSE clock for RTC. If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: RTCDIV
    description: RTCDIV.
    bit_offset: 0
    bit_size: 6
fieldset/SAI1CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the SAI1 and DFSDM audio clock. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: SAI1SRC
    description: SAI1SRC.
    bit_offset: 0
    bit_size: 3
fieldset/SAI2CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the SAI2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: SAI2SRC
    description: SAI2SRC.
    bit_offset: 0
    bit_size: 3
fieldset/SAI3CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the SAI3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: SAI3SRC
    description: SAI3SRC.
    bit_offset: 0
    bit_size: 3
fieldset/SAI4CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the SAI4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: SAI4SRC
    description: SAI4SRC.
    bit_offset: 0
    bit_size: 3
fieldset/SDMMC12CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the SDMMC1 and SDMMC2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: SDMMC12SRC
    description: SDMMC12SRC.
    bit_offset: 0
    bit_size: 3
fieldset/SDMMC3CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the SDMMC3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: SDMMC3SRC
    description: SDMMC3SRC.
    bit_offset: 0
    bit_size: 3
fieldset/SIDR:
  description: This register gives the decoding space, which is for the RCC of 4 kB.
  fields:
  - name: SID
    description: SID.
    bit_offset: 0
    bit_size: 32
fieldset/SPDIFCKSELR:
  description: 'This register is used to control the selection of the kernel clock for the SPDIFRX. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: SPDIFSRC
    description: SPDIFSRC.
    bit_offset: 0
    bit_size: 2
fieldset/SPI2S1CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the SPI/I2S1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: SPI1SRC
    description: SPI1SRC.
    bit_offset: 0
    bit_size: 3
fieldset/SPI2S23CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the SPI/I2S2,3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: SPI23SRC
    description: SPI23SRC.
    bit_offset: 0
    bit_size: 3
fieldset/SPI45CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the SPI4,5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: SPI45SRC
    description: SPI45SRC.
    bit_offset: 0
    bit_size: 3
fieldset/SPI6CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the SPI6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.'
  fields:
  - name: SPI6SRC
    description: SPI6SRC.
    bit_offset: 0
    bit_size: 3
fieldset/STGENCKSELR:
  description: 'This register is used to select the peripheral clock for the STGEN block. Note that this clock is used to provide a time reference for the application. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.'
  fields:
  - name: STGENSRC
    description: STGENSRC.
    bit_offset: 0
    bit_size: 2
fieldset/TIMG1PRER:
  description: 'This register is used to control the prescaler value of timers located into APB1 domain. It concerns TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13 and TIM14. Refer to Section: Sub-system clock generation for additional information.'
  fields:
  - name: TIMG1PRE
    description: TIMG1PRE.
    bit_offset: 0
    bit_size: 1
  - name: TIMG1PRERDY
    description: TIMG1PRERDY.
    bit_offset: 31
    bit_size: 1
fieldset/TIMG2PRER:
  description: 'This register is used to control the prescaler value of timers located into APB2 domain. It concerns TIM1, TIM8, TIM15, TIM16, and TIM17. Refer to Section: Sub-system clock generation for additional information.'
  fields:
  - name: TIMG2PRE
    description: TIMG2PRE.
    bit_offset: 0
    bit_size: 1
  - name: TIMG2PRERDY
    description: TIMG2PRERDY.
    bit_offset: 31
    bit_size: 1
fieldset/TZAHB6RSTCLRR:
  description: This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: MDMARST
    description: MDMARST.
    bit_offset: 0
    bit_size: 1
fieldset/TZAHB6RSTSETR:
  description: This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
  fields:
  - name: MDMARST
    description: MDMARST.
    bit_offset: 0
    bit_size: 1
fieldset/TZCR:
  description: This register is used to switch the RCC into secure mode. This register can only be accessed in secure mode.
  fields:
  - name: TZEN
    description: TZEN.
    bit_offset: 0
    bit_size: 1
  - name: MCKPROT
    description: MCKPROT.
    bit_offset: 1
    bit_size: 1
fieldset/UART1CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the USART1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.'
  fields:
  - name: UART1SRC
    description: UART1SRC.
    bit_offset: 0
    bit_size: 3
fieldset/UART24CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the USART2 and UART4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: UART24SRC
    description: UART24SRC.
    bit_offset: 0
    bit_size: 3
fieldset/UART35CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the USART3 and UART5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: UART35SRC
    description: UART35SRC.
    bit_offset: 0
    bit_size: 3
fieldset/UART6CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the USART6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: UART6SRC
    description: UART6SRC.
    bit_offset: 0
    bit_size: 3
fieldset/UART78CKSELR:
  description: 'This register is used to control the selection of the kernel clock for the UART7 and UART8. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.'
  fields:
  - name: UART78SRC
    description: UART78SRC.
    bit_offset: 0
    bit_size: 3
fieldset/USBCKSELR:
  description: This register is used to control the selection of the kernel clock for the USBPHY PLL of the USB HOST and USB OTG.
  fields:
  - name: USBPHYSRC
    description: USBPHYSRC.
    bit_offset: 0
    bit_size: 2
  - name: USBOSRC
    description: USBOSRC.
    bit_offset: 4
    bit_size: 1
fieldset/VERR:
  description: This register gives the IP version.
  fields:
  - name: MINREV
    description: MINREV.
    bit_offset: 0
    bit_size: 4
  - name: MAJREV
    description: MAJREV.
    bit_offset: 4
    bit_size: 4