block/PWR:
  description: PWR.
  items:
  - name: CR1
    description: 'Reset on any system reset. This register provides write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value.'
    byte_offset: 0
    fieldset: CR1
  - name: CSR1
    description: Reset on any system reset.
    byte_offset: 4
    access: Read
    fieldset: CSR1
  - name: CR2
    description: 'Not reset by wakeup from Standby mode, Application reset (NRST, IWDG, ...) and VDD POR, but reset only by VSW POR and VSWRST. Access 6 wait states when writing this register. After reset the register is write-protected and the DBP bit in the PWR control register 1 (PWR_CR1) has to be set before it can be written. When DBP is cleared, there is no bus errors generated when writing this register. This register shall not be accessed when the RCC VSWRST register bit in Section10.7.89: RCC Backup Domain Control Register (RCC_BDCR) resets the VSW domain. This register provides Write access security when enabled by TZEN register bit in Section10.7.2: RCC TrustZone Control Register (RCC_TZCR). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.'
    byte_offset: 8
    fieldset: CR2
  - name: CR3
    description: 'Not reset by wakeup from Standby mode and Application reset (such as NRST, IWDG) but only reset by VDD POR. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.'
    byte_offset: 12
    fieldset: CR3
  - name: MPUCR
    description: 'See individual bits for reset condition. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.'
    byte_offset: 16
    fieldset: MPUCR
  - name: MCUCR
    description: See individual bits for reset condition. Access 6 wait states when writing this register. This register is always non-secure. When a system reset occurs during the register write cycle the written data is not guaranteed.
    byte_offset: 20
    fieldset: MCUCR
  - name: WKUPCR
    description: 'Not reset by wakeup from Standby mode, but by any application reset (such as NRST, IWDG). Access 6 wait states when writing this register (when clearing a WKUPF, the AHB write access completes after the WKUPF has cleared). This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access on individual WKUPC[6:1], WKUPP[6:1] bits and WKUPPUPD[6:1] bit pairs are discarded when the corresponding WKUPEN[6:1] bit in PWR MPU wakeup enable register (PWR_MPUWKUPENR) is set. No bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.'
    byte_offset: 32
    fieldset: WKUPCR
  - name: WKUPFR
    description: Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...).
    byte_offset: 36
    access: Read
    fieldset: WKUPFR
  - name: MPUWKUPENR
    description: 'Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...). Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access is discarded and a bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.'
    byte_offset: 40
    fieldset: MPUWKUPENR
  - name: MCUWKUPENR
    description: Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...) Access 6 wait states when writing this register. When a system reset occurs during the register write cycle the written data is not guaranteed.
    byte_offset: 44
    fieldset: MCUWKUPENR
  - name: VER
    description: PWR IP version register.
    byte_offset: 1012
    access: Read
    fieldset: VER
  - name: ID
    description: PWR IP identification register.
    byte_offset: 1016
    access: Read
    fieldset: ID
  - name: SID
    description: PWR size ID register.
    byte_offset: 1020
    access: Read
    fieldset: SID
fieldset/CR1:
  description: 'Reset on any system reset. This register provides write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value.'
  fields:
  - name: LPDS
    description: LPDS.
    bit_offset: 0
    bit_size: 1
  - name: LPCFG
    description: LPCFG.
    bit_offset: 1
    bit_size: 1
  - name: LVDS
    description: LVDS.
    bit_offset: 2
    bit_size: 1
  - name: PVDEN
    description: PVDEN.
    bit_offset: 4
    bit_size: 1
  - name: PLS
    description: PLS.
    bit_offset: 5
    bit_size: 3
  - name: DBP
    description: DBP.
    bit_offset: 8
    bit_size: 1
  - name: AVDEN
    description: AVDEN.
    bit_offset: 16
    bit_size: 1
  - name: ALS
    description: ALS.
    bit_offset: 17
    bit_size: 2
fieldset/CR2:
  description: 'Not reset by wakeup from Standby mode, Application reset (NRST, IWDG, ...) and VDD POR, but reset only by VSW POR and VSWRST. Access 6 wait states when writing this register. After reset the register is write-protected and the DBP bit in the PWR control register 1 (PWR_CR1) has to be set before it can be written. When DBP is cleared, there is no bus errors generated when writing this register. This register shall not be accessed when the RCC VSWRST register bit in Section10.7.89: RCC Backup Domain Control Register (RCC_BDCR) resets the VSW domain. This register provides Write access security when enabled by TZEN register bit in Section10.7.2: RCC TrustZone Control Register (RCC_TZCR). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.'
  fields:
  - name: BREN
    description: BREN.
    bit_offset: 0
    bit_size: 1
  - name: RREN
    description: RREN.
    bit_offset: 1
    bit_size: 1
  - name: MONEN
    description: MONEN.
    bit_offset: 4
    bit_size: 1
  - name: BRRDY
    description: BRRDY.
    bit_offset: 16
    bit_size: 1
  - name: RRRDY
    description: RRRDY.
    bit_offset: 17
    bit_size: 1
  - name: VBATL
    description: VBATL.
    bit_offset: 20
    bit_size: 1
  - name: VBATH
    description: VBATH.
    bit_offset: 21
    bit_size: 1
  - name: TEMPL
    description: TEMPL.
    bit_offset: 22
    bit_size: 1
  - name: TEMPH
    description: TEMPH.
    bit_offset: 23
    bit_size: 1
fieldset/CR3:
  description: 'Not reset by wakeup from Standby mode and Application reset (such as NRST, IWDG) but only reset by VDD POR. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.'
  fields:
  - name: VBE
    description: VBE.
    bit_offset: 8
    bit_size: 1
  - name: VBRS
    description: VBRS.
    bit_offset: 9
    bit_size: 1
  - name: DDRSREN
    description: DDRSREN.
    bit_offset: 10
    bit_size: 1
  - name: DDRSRDIS
    description: DDRSRDIS.
    bit_offset: 11
    bit_size: 1
  - name: DDRRETEN
    description: DDRRETEN.
    bit_offset: 12
    bit_size: 1
  - name: POPL
    description: POPL.
    bit_offset: 17
    bit_size: 5
  - name: USB33DEN
    description: USB33DEN.
    bit_offset: 24
    bit_size: 1
  - name: USB33RDY
    description: USB33RDY.
    bit_offset: 26
    bit_size: 1
  - name: REG18EN
    description: REG18EN.
    bit_offset: 28
    bit_size: 1
  - name: REG18RDY
    description: REG18RDY.
    bit_offset: 29
    bit_size: 1
  - name: REG11EN
    description: REG11EN.
    bit_offset: 30
    bit_size: 1
  - name: REG11RDY
    description: REG11RDY.
    bit_offset: 31
    bit_size: 1
fieldset/CSR1:
  description: Reset on any system reset.
  fields:
  - name: PVDO
    description: PVDO.
    bit_offset: 4
    bit_size: 1
  - name: AVDO
    description: AVDO.
    bit_offset: 16
    bit_size: 1
fieldset/ID:
  description: PWR IP identification register.
  fields:
  - name: IPID
    description: IPID.
    bit_offset: 0
    bit_size: 32
fieldset/MCUCR:
  description: See individual bits for reset condition. Access 6 wait states when writing this register. This register is always non-secure. When a system reset occurs during the register write cycle the written data is not guaranteed.
  fields:
  - name: PDDS
    description: PDDS.
    bit_offset: 0
    bit_size: 1
  - name: STOPF
    description: STOPF.
    bit_offset: 5
    bit_size: 1
  - name: SBF
    description: SBF.
    bit_offset: 6
    bit_size: 1
  - name: CSSF
    description: CSSF.
    bit_offset: 9
    bit_size: 1
  - name: DEEPSLEEP
    description: DEEPSLEEP.
    bit_offset: 15
    bit_size: 1
fieldset/MCUWKUPENR:
  description: Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...) Access 6 wait states when writing this register. When a system reset occurs during the register write cycle the written data is not guaranteed.
  fields:
  - name: WKUPEN1
    description: WKUPEN1.
    bit_offset: 0
    bit_size: 1
  - name: WKUPEN2
    description: WKUPEN2.
    bit_offset: 1
    bit_size: 1
  - name: WKUPEN3
    description: WKUPEN3.
    bit_offset: 2
    bit_size: 1
  - name: WKUPEN4
    description: WKUPEN4.
    bit_offset: 3
    bit_size: 1
  - name: WKUPEN5
    description: WKUPEN5.
    bit_offset: 4
    bit_size: 1
  - name: WKUPEN6
    description: WKUPEN6.
    bit_offset: 5
    bit_size: 1
fieldset/MPUCR:
  description: 'See individual bits for reset condition. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.'
  fields:
  - name: PDDS
    description: PDDS.
    bit_offset: 0
    bit_size: 1
  - name: CSTBYDIS
    description: CSTBYDIS.
    bit_offset: 3
    bit_size: 1
  - name: STOPF
    description: STOPF.
    bit_offset: 5
    bit_size: 1
  - name: SBF
    description: SBF.
    bit_offset: 6
    bit_size: 1
  - name: SBFMPU
    description: SBFMPU.
    bit_offset: 7
    bit_size: 1
  - name: CSSF
    description: CSSF.
    bit_offset: 9
    bit_size: 1
  - name: STANDBYWFIL2
    description: STANDBYWFIL2.
    bit_offset: 15
    bit_size: 1
fieldset/MPUWKUPENR:
  description: 'Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...). Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access is discarded and a bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.'
  fields:
  - name: WKUPEN1
    description: WKUPEN1.
    bit_offset: 0
    bit_size: 1
  - name: WKUPEN2
    description: WKUPEN2.
    bit_offset: 1
    bit_size: 1
  - name: WKUPEN3
    description: WKUPEN3.
    bit_offset: 2
    bit_size: 1
  - name: WKUPEN4
    description: WKUPEN4.
    bit_offset: 3
    bit_size: 1
  - name: WKUPEN5
    description: WKUPEN5.
    bit_offset: 4
    bit_size: 1
  - name: WKUPEN6
    description: WKUPEN6.
    bit_offset: 5
    bit_size: 1
fieldset/SID:
  description: PWR size ID register.
  fields:
  - name: SID
    description: SID.
    bit_offset: 0
    bit_size: 32
fieldset/VER:
  description: PWR IP version register.
  fields:
  - name: MINREV
    description: MINREV.
    bit_offset: 0
    bit_size: 4
  - name: MAJREV
    description: MAJREV.
    bit_offset: 4
    bit_size: 4
fieldset/WKUPCR:
  description: 'Not reset by wakeup from Standby mode, but by any application reset (such as NRST, IWDG). Access 6 wait states when writing this register (when clearing a WKUPF, the AHB write access completes after the WKUPF has cleared). This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access on individual WKUPC[6:1], WKUPP[6:1] bits and WKUPPUPD[6:1] bit pairs are discarded when the corresponding WKUPEN[6:1] bit in PWR MPU wakeup enable register (PWR_MPUWKUPENR) is set. No bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.'
  fields:
  - name: WKUPC1
    description: WKUPC1.
    bit_offset: 0
    bit_size: 1
  - name: WKUPC2
    description: WKUPC2.
    bit_offset: 1
    bit_size: 1
  - name: WKUPC3
    description: WKUPC3.
    bit_offset: 2
    bit_size: 1
  - name: WKUPC4
    description: WKUPC4.
    bit_offset: 3
    bit_size: 1
  - name: WKUPC5
    description: WKUPC5.
    bit_offset: 4
    bit_size: 1
  - name: WKUPC6
    description: WKUPC6.
    bit_offset: 5
    bit_size: 1
  - name: WKUPP1
    description: WKUPP1.
    bit_offset: 8
    bit_size: 1
  - name: WKUPP2
    description: WKUPP2.
    bit_offset: 9
    bit_size: 1
  - name: WKUPP3
    description: WKUPP3.
    bit_offset: 10
    bit_size: 1
  - name: WKUPP4
    description: WKUPP4.
    bit_offset: 11
    bit_size: 1
  - name: WKUPP5
    description: WKUPP5.
    bit_offset: 12
    bit_size: 1
  - name: WKUPP6
    description: WKUPP6.
    bit_offset: 13
    bit_size: 1
  - name: WKUPPUPD1
    description: WKUPPUPD1.
    bit_offset: 16
    bit_size: 2
  - name: WKUPPUPD2
    description: WKUPPUPD2.
    bit_offset: 18
    bit_size: 2
  - name: WKUPPUPD3
    description: WKUPPUPD3.
    bit_offset: 20
    bit_size: 2
  - name: WKUPPUPD4
    description: WKUPPUPD4.
    bit_offset: 22
    bit_size: 2
  - name: WKUPPUPD5
    description: WKUPPUPD5.
    bit_offset: 24
    bit_size: 2
  - name: WKUPPUPD6
    description: WKUPPUPD6.
    bit_offset: 26
    bit_size: 2
fieldset/WKUPFR:
  description: Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...).
  fields:
  - name: WKUPF1
    description: WKUPF1.
    bit_offset: 0
    bit_size: 1
  - name: WKUPF2
    description: WKUPF2.
    bit_offset: 1
    bit_size: 1
  - name: WKUPF3
    description: WKUPF3.
    bit_offset: 2
    bit_size: 1
  - name: WKUPF4
    description: WKUPF4.
    bit_offset: 3
    bit_size: 1
  - name: WKUPF5
    description: WKUPF5.
    bit_offset: 4
    bit_size: 1
  - name: WKUPF6
    description: WKUPF6.
    bit_offset: 5
    bit_size: 1