block/MDMA:
  description: MDMA1.
  items:
  - name: GISR0
    description: MDMA global interrupt/status register.
    byte_offset: 0
    access: Read
    fieldset: GISR0
  - name: SGISR0
    description: MDMA secure global interrupt/status register.
    byte_offset: 8
    access: Read
    fieldset: SGISR0
  - name: C0ISR
    description: MDMA channel 0 interrupt/status register.
    byte_offset: 64
    access: Read
    fieldset: C0ISR
  - name: C0IFCR
    description: MDMA channel 0 interrupt flag clear register.
    byte_offset: 68
    access: Write
    fieldset: C0IFCR
  - name: C0ESR
    description: MDMA channel 0 error status register.
    byte_offset: 72
    access: Read
    fieldset: C0ESR
  - name: C0CR
    description: This register is used to control the concerned channel.
    byte_offset: 76
    fieldset: C0CR
  - name: C0TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 80
    fieldset: C0TCR
  - name: C0BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 84
    fieldset: C0BNDTR
  - name: C0SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 88
    fieldset: C0SAR
  - name: C0DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 92
    fieldset: C0DAR
  - name: C0BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 96
    fieldset: C0BRUR
  - name: C0LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 100
    fieldset: C0LAR
  - name: C0TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 104
    fieldset: C0TBR
  - name: C0MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 112
    fieldset: C0MAR
  - name: C0MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 116
    fieldset: C0MDR
  - name: C1ISR
    description: MDMA channel 1 interrupt/status register.
    byte_offset: 128
    access: Read
    fieldset: C1ISR
  - name: C1IFCR
    description: MDMA channel 1 interrupt flag clear register.
    byte_offset: 132
    access: Write
    fieldset: C1IFCR
  - name: C1ESR
    description: MDMA channel 1 error status register.
    byte_offset: 136
    access: Read
    fieldset: C1ESR
  - name: C1CR
    description: This register is used to control the concerned channel.
    byte_offset: 140
    fieldset: C1CR
  - name: C1TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 144
    fieldset: C1TCR
  - name: C1BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 148
    fieldset: C1BNDTR
  - name: C1SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 152
    fieldset: C1SAR
  - name: C1DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 156
    fieldset: C1DAR
  - name: C1BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 160
    fieldset: C1BRUR
  - name: C1LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 164
    fieldset: C1LAR
  - name: C1TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 168
    fieldset: C1TBR
  - name: C1MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 176
    fieldset: C1MAR
  - name: C1MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 180
    fieldset: C1MDR
  - name: C2ISR
    description: MDMA channel 2 interrupt/status register.
    byte_offset: 192
    access: Read
    fieldset: C2ISR
  - name: C2IFCR
    description: MDMA channel 2 interrupt flag clear register.
    byte_offset: 196
    access: Write
    fieldset: C2IFCR
  - name: C2ESR
    description: MDMA channel 2 error status register.
    byte_offset: 200
    access: Read
    fieldset: C2ESR
  - name: C2CR
    description: This register is used to control the concerned channel.
    byte_offset: 204
    fieldset: C2CR
  - name: C2TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 208
    fieldset: C2TCR
  - name: C2BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 212
    fieldset: C2BNDTR
  - name: C2SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 216
    fieldset: C2SAR
  - name: C2DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 220
    fieldset: C2DAR
  - name: C2BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 224
    fieldset: C2BRUR
  - name: C2LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 228
    fieldset: C2LAR
  - name: C2TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 232
    fieldset: C2TBR
  - name: C2MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 240
    fieldset: C2MAR
  - name: C2MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 244
    fieldset: C2MDR
  - name: C3ISR
    description: MDMA channel 3 interrupt/status register.
    byte_offset: 256
    access: Read
    fieldset: C3ISR
  - name: C3IFCR
    description: MDMA channel 3 interrupt flag clear register.
    byte_offset: 260
    access: Write
    fieldset: C3IFCR
  - name: C3ESR
    description: MDMA channel 3 error status register.
    byte_offset: 264
    access: Read
    fieldset: C3ESR
  - name: C3CR
    description: This register is used to control the concerned channel.
    byte_offset: 268
    fieldset: C3CR
  - name: C3TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 272
    fieldset: C3TCR
  - name: C3BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 276
    fieldset: C3BNDTR
  - name: C3SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 280
    fieldset: C3SAR
  - name: C3DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 284
    fieldset: C3DAR
  - name: C3BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 288
    fieldset: C3BRUR
  - name: C3LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 292
    fieldset: C3LAR
  - name: C3TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 296
    fieldset: C3TBR
  - name: C3MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 304
    fieldset: C3MAR
  - name: C3MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 308
    fieldset: C3MDR
  - name: C4ISR
    description: MDMA channel 4 interrupt/status register.
    byte_offset: 320
    access: Read
    fieldset: C4ISR
  - name: C4IFCR
    description: MDMA channel 4 interrupt flag clear register.
    byte_offset: 324
    access: Write
    fieldset: C4IFCR
  - name: C4ESR
    description: MDMA channel 4 error status register.
    byte_offset: 328
    access: Read
    fieldset: C4ESR
  - name: C4CR
    description: This register is used to control the concerned channel.
    byte_offset: 332
    fieldset: C4CR
  - name: C4TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 336
    fieldset: C4TCR
  - name: C4BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 340
    fieldset: C4BNDTR
  - name: C4SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 344
    fieldset: C4SAR
  - name: C4DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 348
    fieldset: C4DAR
  - name: C4BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 352
    fieldset: C4BRUR
  - name: C4LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 356
    fieldset: C4LAR
  - name: C4TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 360
    fieldset: C4TBR
  - name: C4MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 368
    fieldset: C4MAR
  - name: C4MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 372
    fieldset: C4MDR
  - name: C5ISR
    description: MDMA channel 5 interrupt/status register.
    byte_offset: 384
    access: Read
    fieldset: C5ISR
  - name: C5IFCR
    description: MDMA channel 5 interrupt flag clear register.
    byte_offset: 388
    access: Write
    fieldset: C5IFCR
  - name: C5ESR
    description: MDMA channel 5 error status register.
    byte_offset: 392
    access: Read
    fieldset: C5ESR
  - name: C5CR
    description: This register is used to control the concerned channel.
    byte_offset: 396
    fieldset: C5CR
  - name: C5TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 400
    fieldset: C5TCR
  - name: C5BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 404
    fieldset: C5BNDTR
  - name: C5SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 408
    fieldset: C5SAR
  - name: C5DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 412
    fieldset: C5DAR
  - name: C5BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 416
    fieldset: C5BRUR
  - name: C5LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 420
    fieldset: C5LAR
  - name: C5TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 424
    fieldset: C5TBR
  - name: C5MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 432
    fieldset: C5MAR
  - name: C5MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 436
    fieldset: C5MDR
  - name: C6ISR
    description: MDMA channel 6 interrupt/status register.
    byte_offset: 448
    access: Read
    fieldset: C6ISR
  - name: C6IFCR
    description: MDMA channel 6 interrupt flag clear register.
    byte_offset: 452
    access: Write
    fieldset: C6IFCR
  - name: C6ESR
    description: MDMA channel 6 error status register.
    byte_offset: 456
    access: Read
    fieldset: C6ESR
  - name: C6CR
    description: This register is used to control the concerned channel.
    byte_offset: 460
    fieldset: C6CR
  - name: C6TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 464
    fieldset: C6TCR
  - name: C6BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 468
    fieldset: C6BNDTR
  - name: C6SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 472
    fieldset: C6SAR
  - name: C6DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 476
    fieldset: C6DAR
  - name: C6BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 480
    fieldset: C6BRUR
  - name: C6LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 484
    fieldset: C6LAR
  - name: C6TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 488
    fieldset: C6TBR
  - name: C6MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 496
    fieldset: C6MAR
  - name: C6MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 500
    fieldset: C6MDR
  - name: C7ISR
    description: MDMA channel 7 interrupt/status register.
    byte_offset: 512
    access: Read
    fieldset: C7ISR
  - name: C7IFCR
    description: MDMA channel 7 interrupt flag clear register.
    byte_offset: 516
    access: Write
    fieldset: C7IFCR
  - name: C7ESR
    description: MDMA channel 7 error status register.
    byte_offset: 520
    access: Read
    fieldset: C7ESR
  - name: C7CR
    description: This register is used to control the concerned channel.
    byte_offset: 524
    fieldset: C7CR
  - name: C7TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 528
    fieldset: C7TCR
  - name: C7BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 532
    fieldset: C7BNDTR
  - name: C7SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 536
    fieldset: C7SAR
  - name: C7DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 540
    fieldset: C7DAR
  - name: C7BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 544
    fieldset: C7BRUR
  - name: C7LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 548
    fieldset: C7LAR
  - name: C7TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 552
    fieldset: C7TBR
  - name: C7MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 560
    fieldset: C7MAR
  - name: C7MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 564
    fieldset: C7MDR
  - name: C8ISR
    description: MDMA channel 8 interrupt/status register.
    byte_offset: 576
    access: Read
    fieldset: C8ISR
  - name: C8IFCR
    description: MDMA channel 8 interrupt flag clear register.
    byte_offset: 580
    access: Write
    fieldset: C8IFCR
  - name: C8ESR
    description: MDMA channel 8 error status register.
    byte_offset: 584
    access: Read
    fieldset: C8ESR
  - name: C8CR
    description: This register is used to control the concerned channel.
    byte_offset: 588
    fieldset: C8CR
  - name: C8TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 592
    fieldset: C8TCR
  - name: C8BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 596
    fieldset: C8BNDTR
  - name: C8SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 600
    fieldset: C8SAR
  - name: C8DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 604
    fieldset: C8DAR
  - name: C8BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 608
    fieldset: C8BRUR
  - name: C8LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 612
    fieldset: C8LAR
  - name: C8TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 616
    fieldset: C8TBR
  - name: C8MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 624
    fieldset: C8MAR
  - name: C8MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 628
    fieldset: C8MDR
  - name: C9ISR
    description: MDMA channel 9 interrupt/status register.
    byte_offset: 640
    access: Read
    fieldset: C9ISR
  - name: C9IFCR
    description: MDMA channel 9 interrupt flag clear register.
    byte_offset: 644
    access: Write
    fieldset: C9IFCR
  - name: C9ESR
    description: MDMA channel 9 error status register.
    byte_offset: 648
    access: Read
    fieldset: C9ESR
  - name: C9CR
    description: This register is used to control the concerned channel.
    byte_offset: 652
    fieldset: C9CR
  - name: C9TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 656
    fieldset: C9TCR
  - name: C9BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 660
    fieldset: C9BNDTR
  - name: C9SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 664
    fieldset: C9SAR
  - name: C9DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 668
    fieldset: C9DAR
  - name: C9BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 672
    fieldset: C9BRUR
  - name: C9LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 676
    fieldset: C9LAR
  - name: C9TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 680
    fieldset: C9TBR
  - name: C9MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 688
    fieldset: C9MAR
  - name: C9MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 692
    fieldset: C9MDR
  - name: C10ISR
    description: MDMA channel 10 interrupt/status register.
    byte_offset: 704
    access: Read
    fieldset: C10ISR
  - name: C10IFCR
    description: MDMA channel 10 interrupt flag clear register.
    byte_offset: 708
    access: Write
    fieldset: C10IFCR
  - name: C10ESR
    description: MDMA channel 10 error status register.
    byte_offset: 712
    access: Read
    fieldset: C10ESR
  - name: C10CR
    description: This register is used to control the concerned channel.
    byte_offset: 716
    fieldset: C10CR
  - name: C10TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 720
    fieldset: C10TCR
  - name: C10BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 724
    fieldset: C10BNDTR
  - name: C10SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 728
    fieldset: C10SAR
  - name: C10DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 732
    fieldset: C10DAR
  - name: C10BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 736
    fieldset: C10BRUR
  - name: C10LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 740
    fieldset: C10LAR
  - name: C10TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 744
    fieldset: C10TBR
  - name: C10MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 752
    fieldset: C10MAR
  - name: C10MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 756
    fieldset: C10MDR
  - name: C11ISR
    description: MDMA channel 11 interrupt/status register.
    byte_offset: 768
    access: Read
    fieldset: C11ISR
  - name: C11IFCR
    description: MDMA channel 11 interrupt flag clear register.
    byte_offset: 772
    access: Write
    fieldset: C11IFCR
  - name: C11ESR
    description: MDMA channel 11 error status register.
    byte_offset: 776
    access: Read
    fieldset: C11ESR
  - name: C11CR
    description: This register is used to control the concerned channel.
    byte_offset: 780
    fieldset: C11CR
  - name: C11TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 784
    fieldset: C11TCR
  - name: C11BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 788
    fieldset: C11BNDTR
  - name: C11SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 792
    fieldset: C11SAR
  - name: C11DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 796
    fieldset: C11DAR
  - name: C11BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 800
    fieldset: C11BRUR
  - name: C11LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 804
    fieldset: C11LAR
  - name: C11TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 808
    fieldset: C11TBR
  - name: C11MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 816
    fieldset: C11MAR
  - name: C11MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 820
    fieldset: C11MDR
  - name: C12ISR
    description: MDMA channel 12 interrupt/status register.
    byte_offset: 832
    access: Read
    fieldset: C12ISR
  - name: C12IFCR
    description: MDMA channel 12 interrupt flag clear register.
    byte_offset: 836
    access: Write
    fieldset: C12IFCR
  - name: C12ESR
    description: MDMA channel 12 error status register.
    byte_offset: 840
    access: Read
    fieldset: C12ESR
  - name: C12CR
    description: This register is used to control the concerned channel.
    byte_offset: 844
    fieldset: C12CR
  - name: C12TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 848
    fieldset: C12TCR
  - name: C12BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 852
    fieldset: C12BNDTR
  - name: C12SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 856
    fieldset: C12SAR
  - name: C12DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 860
    fieldset: C12DAR
  - name: C12BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 864
    fieldset: C12BRUR
  - name: C12LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 868
    fieldset: C12LAR
  - name: C12TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 872
    fieldset: C12TBR
  - name: C12MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 880
    fieldset: C12MAR
  - name: C12MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 884
    fieldset: C12MDR
  - name: C13ISR
    description: MDMA channel 13 interrupt/status register.
    byte_offset: 896
    access: Read
    fieldset: C13ISR
  - name: C13IFCR
    description: MDMA channel 13 interrupt flag clear register.
    byte_offset: 900
    access: Write
    fieldset: C13IFCR
  - name: C13ESR
    description: MDMA channel 13 error status register.
    byte_offset: 904
    access: Read
    fieldset: C13ESR
  - name: C13CR
    description: This register is used to control the concerned channel.
    byte_offset: 908
    fieldset: C13CR
  - name: C13TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 912
    fieldset: C13TCR
  - name: C13BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 916
    fieldset: C13BNDTR
  - name: C13SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 920
    fieldset: C13SAR
  - name: C13DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 924
    fieldset: C13DAR
  - name: C13BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 928
    fieldset: C13BRUR
  - name: C13LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 932
    fieldset: C13LAR
  - name: C13TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 936
    fieldset: C13TBR
  - name: C13MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 944
    fieldset: C13MAR
  - name: C13MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 948
    fieldset: C13MDR
  - name: C14ISR
    description: MDMA channel 14 interrupt/status register.
    byte_offset: 960
    access: Read
    fieldset: C14ISR
  - name: C14IFCR
    description: MDMA channel 14 interrupt flag clear register.
    byte_offset: 964
    access: Write
    fieldset: C14IFCR
  - name: C14ESR
    description: MDMA channel 14 error status register.
    byte_offset: 968
    access: Read
    fieldset: C14ESR
  - name: C14CR
    description: This register is used to control the concerned channel.
    byte_offset: 972
    fieldset: C14CR
  - name: C14TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 976
    fieldset: C14TCR
  - name: C14BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 980
    fieldset: C14BNDTR
  - name: C14SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 984
    fieldset: C14SAR
  - name: C14DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 988
    fieldset: C14DAR
  - name: C14BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 992
    fieldset: C14BRUR
  - name: C14LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 996
    fieldset: C14LAR
  - name: C14TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 1000
    fieldset: C14TBR
  - name: C14MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 1008
    fieldset: C14MAR
  - name: C14MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 1012
    fieldset: C14MDR
  - name: C15ISR
    description: MDMA channel 15 interrupt/status register.
    byte_offset: 1024
    access: Read
    fieldset: C15ISR
  - name: C15IFCR
    description: MDMA channel 15 interrupt flag clear register.
    byte_offset: 1028
    access: Write
    fieldset: C15IFCR
  - name: C15ESR
    description: MDMA channel 15 error status register.
    byte_offset: 1032
    access: Read
    fieldset: C15ESR
  - name: C15CR
    description: This register is used to control the concerned channel.
    byte_offset: 1036
    fieldset: C15CR
  - name: C15TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 1040
    fieldset: C15TCR
  - name: C15BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 1044
    fieldset: C15BNDTR
  - name: C15SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 1048
    fieldset: C15SAR
  - name: C15DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 1052
    fieldset: C15DAR
  - name: C15BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 1056
    fieldset: C15BRUR
  - name: C15LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 1060
    fieldset: C15LAR
  - name: C15TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 1064
    fieldset: C15TBR
  - name: C15MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 1072
    fieldset: C15MAR
  - name: C15MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 1076
    fieldset: C15MDR
  - name: C16ISR
    description: MDMA channel 16 interrupt/status register.
    byte_offset: 1088
    access: Read
    fieldset: C16ISR
  - name: C16IFCR
    description: MDMA channel 16 interrupt flag clear register.
    byte_offset: 1092
    access: Write
    fieldset: C16IFCR
  - name: C16ESR
    description: MDMA channel 16 error status register.
    byte_offset: 1096
    access: Read
    fieldset: C16ESR
  - name: C16CR
    description: This register is used to control the concerned channel.
    byte_offset: 1100
    fieldset: C16CR
  - name: C16TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 1104
    fieldset: C16TCR
  - name: C16BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 1108
    fieldset: C16BNDTR
  - name: C16SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 1112
    fieldset: C16SAR
  - name: C16DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 1116
    fieldset: C16DAR
  - name: C16BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 1120
    fieldset: C16BRUR
  - name: C16LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 1124
    fieldset: C16LAR
  - name: C16TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 1128
    fieldset: C16TBR
  - name: C16MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 1136
    fieldset: C16MAR
  - name: C16MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 1140
    fieldset: C16MDR
  - name: C17ISR
    description: MDMA channel 17 interrupt/status register.
    byte_offset: 1152
    access: Read
    fieldset: C17ISR
  - name: C17IFCR
    description: MDMA channel 17 interrupt flag clear register.
    byte_offset: 1156
    access: Write
    fieldset: C17IFCR
  - name: C17ESR
    description: MDMA channel 17 error status register.
    byte_offset: 1160
    access: Read
    fieldset: C17ESR
  - name: C17CR
    description: This register is used to control the concerned channel.
    byte_offset: 1164
    fieldset: C17CR
  - name: C17TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 1168
    fieldset: C17TCR
  - name: C17BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 1172
    fieldset: C17BNDTR
  - name: C17SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 1176
    fieldset: C17SAR
  - name: C17DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 1180
    fieldset: C17DAR
  - name: C17BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 1184
    fieldset: C17BRUR
  - name: C17LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 1188
    fieldset: C17LAR
  - name: C17TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 1192
    fieldset: C17TBR
  - name: C17MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 1200
    fieldset: C17MAR
  - name: C17MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 1204
    fieldset: C17MDR
  - name: C18ISR
    description: MDMA channel 18 interrupt/status register.
    byte_offset: 1216
    access: Read
    fieldset: C18ISR
  - name: C18IFCR
    description: MDMA channel 18 interrupt flag clear register.
    byte_offset: 1220
    access: Write
    fieldset: C18IFCR
  - name: C18ESR
    description: MDMA channel 18 error status register.
    byte_offset: 1224
    access: Read
    fieldset: C18ESR
  - name: C18CR
    description: This register is used to control the concerned channel.
    byte_offset: 1228
    fieldset: C18CR
  - name: C18TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 1232
    fieldset: C18TCR
  - name: C18BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 1236
    fieldset: C18BNDTR
  - name: C18SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 1240
    fieldset: C18SAR
  - name: C18DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 1244
    fieldset: C18DAR
  - name: C18BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 1248
    fieldset: C18BRUR
  - name: C18LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 1252
    fieldset: C18LAR
  - name: C18TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 1256
    fieldset: C18TBR
  - name: C18MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 1264
    fieldset: C18MAR
  - name: C18MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 1268
    fieldset: C18MDR
  - name: C19ISR
    description: MDMA channel 19 interrupt/status register.
    byte_offset: 1280
    access: Read
    fieldset: C19ISR
  - name: C19IFCR
    description: MDMA channel 19 interrupt flag clear register.
    byte_offset: 1284
    access: Write
    fieldset: C19IFCR
  - name: C19ESR
    description: MDMA channel 19 error status register.
    byte_offset: 1288
    access: Read
    fieldset: C19ESR
  - name: C19CR
    description: This register is used to control the concerned channel.
    byte_offset: 1292
    fieldset: C19CR
  - name: C19TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 1296
    fieldset: C19TCR
  - name: C19BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 1300
    fieldset: C19BNDTR
  - name: C19SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 1304
    fieldset: C19SAR
  - name: C19DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 1308
    fieldset: C19DAR
  - name: C19BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 1312
    fieldset: C19BRUR
  - name: C19LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 1316
    fieldset: C19LAR
  - name: C19TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 1320
    fieldset: C19TBR
  - name: C19MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 1328
    fieldset: C19MAR
  - name: C19MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 1332
    fieldset: C19MDR
  - name: C20ISR
    description: MDMA channel 20 interrupt/status register.
    byte_offset: 1344
    access: Read
    fieldset: C20ISR
  - name: C20IFCR
    description: MDMA channel 20 interrupt flag clear register.
    byte_offset: 1348
    access: Write
    fieldset: C20IFCR
  - name: C20ESR
    description: MDMA channel 20 error status register.
    byte_offset: 1352
    access: Read
    fieldset: C20ESR
  - name: C20CR
    description: This register is used to control the concerned channel.
    byte_offset: 1356
    fieldset: C20CR
  - name: C20TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 1360
    fieldset: C20TCR
  - name: C20BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 1364
    fieldset: C20BNDTR
  - name: C20SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 1368
    fieldset: C20SAR
  - name: C20DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 1372
    fieldset: C20DAR
  - name: C20BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 1376
    fieldset: C20BRUR
  - name: C20LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 1380
    fieldset: C20LAR
  - name: C20TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 1384
    fieldset: C20TBR
  - name: C20MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 1392
    fieldset: C20MAR
  - name: C20MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 1396
    fieldset: C20MDR
  - name: C21ISR
    description: MDMA channel 21 interrupt/status register.
    byte_offset: 1408
    access: Read
    fieldset: C21ISR
  - name: C21IFCR
    description: MDMA channel 21 interrupt flag clear register.
    byte_offset: 1412
    access: Write
    fieldset: C21IFCR
  - name: C21ESR
    description: MDMA channel 21 error status register.
    byte_offset: 1416
    access: Read
    fieldset: C21ESR
  - name: C21CR
    description: This register is used to control the concerned channel.
    byte_offset: 1420
    fieldset: C21CR
  - name: C21TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 1424
    fieldset: C21TCR
  - name: C21BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 1428
    fieldset: C21BNDTR
  - name: C21SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 1432
    fieldset: C21SAR
  - name: C21DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 1436
    fieldset: C21DAR
  - name: C21BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 1440
    fieldset: C21BRUR
  - name: C21LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 1444
    fieldset: C21LAR
  - name: C21TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 1448
    fieldset: C21TBR
  - name: C21MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 1456
    fieldset: C21MAR
  - name: C21MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 1460
    fieldset: C21MDR
  - name: C22ISR
    description: MDMA channel 22 interrupt/status register.
    byte_offset: 1472
    access: Read
    fieldset: C22ISR
  - name: C22IFCR
    description: MDMA channel 22 interrupt flag clear register.
    byte_offset: 1476
    access: Write
    fieldset: C22IFCR
  - name: C22ESR
    description: MDMA channel 22 error status register.
    byte_offset: 1480
    access: Read
    fieldset: C22ESR
  - name: C22CR
    description: This register is used to control the concerned channel.
    byte_offset: 1484
    fieldset: C22CR
  - name: C22TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 1488
    fieldset: C22TCR
  - name: C22BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 1492
    fieldset: C22BNDTR
  - name: C22SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 1496
    fieldset: C22SAR
  - name: C22DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 1500
    fieldset: C22DAR
  - name: C22BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 1504
    fieldset: C22BRUR
  - name: C22LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 1508
    fieldset: C22LAR
  - name: C22TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 1512
    fieldset: C22TBR
  - name: C22MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 1520
    fieldset: C22MAR
  - name: C22MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 1524
    fieldset: C22MDR
  - name: C23ISR
    description: MDMA channel 23 interrupt/status register.
    byte_offset: 1536
    access: Read
    fieldset: C23ISR
  - name: C23IFCR
    description: MDMA channel 23 interrupt flag clear register.
    byte_offset: 1540
    access: Write
    fieldset: C23IFCR
  - name: C23ESR
    description: MDMA channel 23 error status register.
    byte_offset: 1544
    access: Read
    fieldset: C23ESR
  - name: C23CR
    description: This register is used to control the concerned channel.
    byte_offset: 1548
    fieldset: C23CR
  - name: C23TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 1552
    fieldset: C23TCR
  - name: C23BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 1556
    fieldset: C23BNDTR
  - name: C23SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 1560
    fieldset: C23SAR
  - name: C23DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 1564
    fieldset: C23DAR
  - name: C23BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 1568
    fieldset: C23BRUR
  - name: C23LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 1572
    fieldset: C23LAR
  - name: C23TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 1576
    fieldset: C23TBR
  - name: C23MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 1584
    fieldset: C23MAR
  - name: C23MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 1588
    fieldset: C23MDR
  - name: C24ISR
    description: MDMA channel 24 interrupt/status register.
    byte_offset: 1600
    access: Read
    fieldset: C24ISR
  - name: C24IFCR
    description: MDMA channel 24 interrupt flag clear register.
    byte_offset: 1604
    access: Write
    fieldset: C24IFCR
  - name: C24ESR
    description: MDMA channel 24 error status register.
    byte_offset: 1608
    access: Read
    fieldset: C24ESR
  - name: C24CR
    description: This register is used to control the concerned channel.
    byte_offset: 1612
    fieldset: C24CR
  - name: C24TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 1616
    fieldset: C24TCR
  - name: C24BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 1620
    fieldset: C24BNDTR
  - name: C24SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 1624
    fieldset: C24SAR
  - name: C24DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 1628
    fieldset: C24DAR
  - name: C24BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 1632
    fieldset: C24BRUR
  - name: C24LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 1636
    fieldset: C24LAR
  - name: C24TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 1640
    fieldset: C24TBR
  - name: C24MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 1648
    fieldset: C24MAR
  - name: C24MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 1652
    fieldset: C24MDR
  - name: C25ISR
    description: MDMA channel 25 interrupt/status register.
    byte_offset: 1664
    access: Read
    fieldset: C25ISR
  - name: C25IFCR
    description: MDMA channel 25 interrupt flag clear register.
    byte_offset: 1668
    access: Write
    fieldset: C25IFCR
  - name: C25ESR
    description: MDMA channel 25 error status register.
    byte_offset: 1672
    access: Read
    fieldset: C25ESR
  - name: C25CR
    description: This register is used to control the concerned channel.
    byte_offset: 1676
    fieldset: C25CR
  - name: C25TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 1680
    fieldset: C25TCR
  - name: C25BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 1684
    fieldset: C25BNDTR
  - name: C25SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 1688
    fieldset: C25SAR
  - name: C25DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 1692
    fieldset: C25DAR
  - name: C25BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 1696
    fieldset: C25BRUR
  - name: C25LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 1700
    fieldset: C25LAR
  - name: C25TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 1704
    fieldset: C25TBR
  - name: C25MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 1712
    fieldset: C25MAR
  - name: C25MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 1716
    fieldset: C25MDR
  - name: C26ISR
    description: MDMA channel 26 interrupt/status register.
    byte_offset: 1728
    access: Read
    fieldset: C26ISR
  - name: C26IFCR
    description: MDMA channel 26 interrupt flag clear register.
    byte_offset: 1732
    access: Write
    fieldset: C26IFCR
  - name: C26ESR
    description: MDMA channel 26 error status register.
    byte_offset: 1736
    access: Read
    fieldset: C26ESR
  - name: C26CR
    description: This register is used to control the concerned channel.
    byte_offset: 1740
    fieldset: C26CR
  - name: C26TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 1744
    fieldset: C26TCR
  - name: C26BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 1748
    fieldset: C26BNDTR
  - name: C26SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 1752
    fieldset: C26SAR
  - name: C26DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 1756
    fieldset: C26DAR
  - name: C26BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 1760
    fieldset: C26BRUR
  - name: C26LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 1764
    fieldset: C26LAR
  - name: C26TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 1768
    fieldset: C26TBR
  - name: C26MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 1776
    fieldset: C26MAR
  - name: C26MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 1780
    fieldset: C26MDR
  - name: C27ISR
    description: MDMA channel 27 interrupt/status register.
    byte_offset: 1792
    access: Read
    fieldset: C27ISR
  - name: C27IFCR
    description: MDMA channel 27 interrupt flag clear register.
    byte_offset: 1796
    access: Write
    fieldset: C27IFCR
  - name: C27ESR
    description: MDMA channel 27 error status register.
    byte_offset: 1800
    access: Read
    fieldset: C27ESR
  - name: C27CR
    description: This register is used to control the concerned channel.
    byte_offset: 1804
    fieldset: C27CR
  - name: C27TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 1808
    fieldset: C27TCR
  - name: C27BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 1812
    fieldset: C27BNDTR
  - name: C27SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 1816
    fieldset: C27SAR
  - name: C27DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 1820
    fieldset: C27DAR
  - name: C27BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 1824
    fieldset: C27BRUR
  - name: C27LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 1828
    fieldset: C27LAR
  - name: C27TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 1832
    fieldset: C27TBR
  - name: C27MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 1840
    fieldset: C27MAR
  - name: C27MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 1844
    fieldset: C27MDR
  - name: C28ISR
    description: MDMA channel 28 interrupt/status register.
    byte_offset: 1856
    access: Read
    fieldset: C28ISR
  - name: C28IFCR
    description: MDMA channel 28 interrupt flag clear register.
    byte_offset: 1860
    access: Write
    fieldset: C28IFCR
  - name: C28ESR
    description: MDMA channel 28 error status register.
    byte_offset: 1864
    access: Read
    fieldset: C28ESR
  - name: C28CR
    description: This register is used to control the concerned channel.
    byte_offset: 1868
    fieldset: C28CR
  - name: C28TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 1872
    fieldset: C28TCR
  - name: C28BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 1876
    fieldset: C28BNDTR
  - name: C28SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 1880
    fieldset: C28SAR
  - name: C28DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 1884
    fieldset: C28DAR
  - name: C28BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 1888
    fieldset: C28BRUR
  - name: C28LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 1892
    fieldset: C28LAR
  - name: C28TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 1896
    fieldset: C28TBR
  - name: C28MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 1904
    fieldset: C28MAR
  - name: C28MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 1908
    fieldset: C28MDR
  - name: C29ISR
    description: MDMA channel 29 interrupt/status register.
    byte_offset: 1920
    access: Read
    fieldset: C29ISR
  - name: C29IFCR
    description: MDMA channel 29 interrupt flag clear register.
    byte_offset: 1924
    access: Write
    fieldset: C29IFCR
  - name: C29ESR
    description: MDMA channel 29 error status register.
    byte_offset: 1928
    access: Read
    fieldset: C29ESR
  - name: C29CR
    description: This register is used to control the concerned channel.
    byte_offset: 1932
    fieldset: C29CR
  - name: C29TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 1936
    fieldset: C29TCR
  - name: C29BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 1940
    fieldset: C29BNDTR
  - name: C29SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 1944
    fieldset: C29SAR
  - name: C29DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 1948
    fieldset: C29DAR
  - name: C29BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 1952
    fieldset: C29BRUR
  - name: C29LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 1956
    fieldset: C29LAR
  - name: C29TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 1960
    fieldset: C29TBR
  - name: C29MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 1968
    fieldset: C29MAR
  - name: C29MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 1972
    fieldset: C29MDR
  - name: C30ISR
    description: MDMA channel 30 interrupt/status register.
    byte_offset: 1984
    access: Read
    fieldset: C30ISR
  - name: C30IFCR
    description: MDMA channel 30 interrupt flag clear register.
    byte_offset: 1988
    access: Write
    fieldset: C30IFCR
  - name: C30ESR
    description: MDMA channel 30 error status register.
    byte_offset: 1992
    access: Read
    fieldset: C30ESR
  - name: C30CR
    description: This register is used to control the concerned channel.
    byte_offset: 1996
    fieldset: C30CR
  - name: C30TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 2000
    fieldset: C30TCR
  - name: C30BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 2004
    fieldset: C30BNDTR
  - name: C30SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 2008
    fieldset: C30SAR
  - name: C30DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 2012
    fieldset: C30DAR
  - name: C30BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 2016
    fieldset: C30BRUR
  - name: C30LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 2020
    fieldset: C30LAR
  - name: C30TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 2024
    fieldset: C30TBR
  - name: C30MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 2032
    fieldset: C30MAR
  - name: C30MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 2036
    fieldset: C30MDR
  - name: C31ISR
    description: MDMA channel 31 interrupt/status register.
    byte_offset: 2048
    access: Read
    fieldset: C31ISR
  - name: C31IFCR
    description: MDMA channel 31 interrupt flag clear register.
    byte_offset: 2052
    access: Write
    fieldset: C31IFCR
  - name: C31ESR
    description: MDMA channel 31 error status register.
    byte_offset: 2056
    access: Read
    fieldset: C31ESR
  - name: C31CR
    description: This register is used to control the concerned channel.
    byte_offset: 2060
    fieldset: C31CR
  - name: C31TCR
    description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
    byte_offset: 2064
    fieldset: C31TCR
  - name: C31BNDTR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
    byte_offset: 2068
    fieldset: C31BNDTR
  - name: C31SAR
    description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
    byte_offset: 2072
    fieldset: C31SAR
  - name: C31DAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
    byte_offset: 2076
    fieldset: C31DAR
  - name: C31BRUR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
    byte_offset: 2080
    fieldset: C31BRUR
  - name: C31LAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
    byte_offset: 2084
    fieldset: C31LAR
  - name: C31TBR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
    byte_offset: 2088
    fieldset: C31TBR
  - name: C31MAR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
    byte_offset: 2096
    fieldset: C31MAR
  - name: C31MDR
    description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
    byte_offset: 2100
    fieldset: C31MDR
fieldset/C0BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C0BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C0CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C0DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C0ESR:
  description: MDMA channel 0 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C0IFCR:
  description: MDMA channel 0 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C0ISR:
  description: MDMA channel 0 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C0LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C0MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C0MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C0SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C0TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C0TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C10BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C10BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C10CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C10DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C10ESR:
  description: MDMA channel 10 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C10IFCR:
  description: MDMA channel 10 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C10ISR:
  description: MDMA channel 10 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C10LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C10MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C10MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C10SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C10TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C10TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C11BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C11BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C11CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C11DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C11ESR:
  description: MDMA channel 11 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C11IFCR:
  description: MDMA channel 11 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C11ISR:
  description: MDMA channel 11 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C11LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C11MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C11MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C11SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C11TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C11TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C12BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C12BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C12CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C12DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C12ESR:
  description: MDMA channel 12 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C12IFCR:
  description: MDMA channel 12 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C12ISR:
  description: MDMA channel 12 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C12LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C12MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C12MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C12SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C12TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C12TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C13BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C13BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C13CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C13DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C13ESR:
  description: MDMA channel 13 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C13IFCR:
  description: MDMA channel 13 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C13ISR:
  description: MDMA channel 13 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C13LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C13MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C13MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C13SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C13TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C13TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C14BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C14BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C14CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C14DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C14ESR:
  description: MDMA channel 14 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C14IFCR:
  description: MDMA channel 14 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C14ISR:
  description: MDMA channel 14 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C14LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C14MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C14MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C14SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C14TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C14TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C15BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C15BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C15CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C15DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C15ESR:
  description: MDMA channel 15 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C15IFCR:
  description: MDMA channel 15 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C15ISR:
  description: MDMA channel 15 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C15LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C15MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C15MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C15SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C15TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C15TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C16BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C16BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C16CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C16DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C16ESR:
  description: MDMA channel 16 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C16IFCR:
  description: MDMA channel 16 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C16ISR:
  description: MDMA channel 16 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C16LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C16MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C16MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C16SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C16TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C16TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C17BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C17BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C17CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C17DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C17ESR:
  description: MDMA channel 17 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C17IFCR:
  description: MDMA channel 17 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C17ISR:
  description: MDMA channel 17 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C17LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C17MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C17MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C17SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C17TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C17TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C18BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C18BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C18CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C18DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C18ESR:
  description: MDMA channel 18 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C18IFCR:
  description: MDMA channel 18 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C18ISR:
  description: MDMA channel 18 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C18LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C18MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C18MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C18SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C18TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C18TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C19BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C19BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C19CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C19DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C19ESR:
  description: MDMA channel 19 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C19IFCR:
  description: MDMA channel 19 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C19ISR:
  description: MDMA channel 19 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C19LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C19MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C19MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C19SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C19TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C19TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C1BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C1BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C1CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C1DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C1ESR:
  description: MDMA channel 1 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C1IFCR:
  description: MDMA channel 1 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C1ISR:
  description: MDMA channel 1 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C1LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C1MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C1MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C1SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C1TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C1TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C20BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C20BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C20CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C20DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C20ESR:
  description: MDMA channel 20 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C20IFCR:
  description: MDMA channel 20 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C20ISR:
  description: MDMA channel 20 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C20LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C20MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C20MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C20SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C20TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C20TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C21BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C21BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C21CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C21DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C21ESR:
  description: MDMA channel 21 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C21IFCR:
  description: MDMA channel 21 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C21ISR:
  description: MDMA channel 21 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C21LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C21MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C21MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C21SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C21TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C21TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C22BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C22BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C22CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C22DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C22ESR:
  description: MDMA channel 22 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C22IFCR:
  description: MDMA channel 22 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C22ISR:
  description: MDMA channel 22 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C22LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C22MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C22MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C22SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C22TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C22TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C23BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C23BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C23CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C23DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C23ESR:
  description: MDMA channel 23 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C23IFCR:
  description: MDMA channel 23 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C23ISR:
  description: MDMA channel 23 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C23LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C23MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C23MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C23SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C23TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C23TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C24BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C24BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C24CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C24DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C24ESR:
  description: MDMA channel 24 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C24IFCR:
  description: MDMA channel 24 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C24ISR:
  description: MDMA channel 24 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C24LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C24MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C24MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C24SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C24TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C24TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C25BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C25BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C25CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C25DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C25ESR:
  description: MDMA channel 25 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C25IFCR:
  description: MDMA channel 25 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C25ISR:
  description: MDMA channel 25 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C25LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C25MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C25MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C25SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C25TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C25TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C26BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C26BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C26CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C26DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C26ESR:
  description: MDMA channel 26 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C26IFCR:
  description: MDMA channel 26 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C26ISR:
  description: MDMA channel 26 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C26LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C26MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C26MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C26SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C26TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C26TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C27BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C27BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C27CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C27DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C27ESR:
  description: MDMA channel 27 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C27IFCR:
  description: MDMA channel 27 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C27ISR:
  description: MDMA channel 27 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C27LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C27MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C27MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C27SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C27TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C27TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C28BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C28BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C28CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C28DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C28ESR:
  description: MDMA channel 28 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C28IFCR:
  description: MDMA channel 28 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C28ISR:
  description: MDMA channel 28 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C28LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C28MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C28MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C28SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C28TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C28TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C29BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C29BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C29CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C29DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C29ESR:
  description: MDMA channel 29 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C29IFCR:
  description: MDMA channel 29 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C29ISR:
  description: MDMA channel 29 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C29LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C29MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C29MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C29SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C29TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C29TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C2BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C2BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C2CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C2DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C2ESR:
  description: MDMA channel 2 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C2IFCR:
  description: MDMA channel 2 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C2ISR:
  description: MDMA channel 2 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C2LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C2MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C2MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C2SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C2TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C2TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C30BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C30BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C30CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C30DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C30ESR:
  description: MDMA channel 30 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C30IFCR:
  description: MDMA channel 30 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C30ISR:
  description: MDMA channel 30 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C30LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C30MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C30MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C30SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C30TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C30TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C31BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C31BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C31CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C31DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C31ESR:
  description: MDMA channel 31 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C31IFCR:
  description: MDMA channel 31 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C31ISR:
  description: MDMA channel 31 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C31LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C31MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C31MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C31SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C31TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C31TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C3BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C3BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C3CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C3DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C3ESR:
  description: MDMA channel 3 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C3IFCR:
  description: MDMA channel 3 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C3ISR:
  description: MDMA channel 3 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C3LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C3MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C3MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C3SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C3TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C3TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C4BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C4BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C4CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C4DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C4ESR:
  description: MDMA channel 4 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C4IFCR:
  description: MDMA channel 4 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C4ISR:
  description: MDMA channel 4 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C4LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C4MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C4MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C4SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C4TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C4TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C5BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C5BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C5CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C5DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C5ESR:
  description: MDMA channel 5 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C5IFCR:
  description: MDMA channel 5 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C5ISR:
  description: MDMA channel 5 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C5LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C5MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C5MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C5SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C5TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C5TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C6BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C6BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C6CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C6DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C6ESR:
  description: MDMA channel 6 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C6IFCR:
  description: MDMA channel 6 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C6ISR:
  description: MDMA channel 6 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C6LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C6MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C6MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C6SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C6TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C6TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C7BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C7BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C7CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C7DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C7ESR:
  description: MDMA channel 7 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C7IFCR:
  description: MDMA channel 7 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C7ISR:
  description: MDMA channel 7 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C7LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C7MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C7MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C7SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C7TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C7TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C8BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C8BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C8CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C8DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C8ESR:
  description: MDMA channel 8 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C8IFCR:
  description: MDMA channel 8 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C8ISR:
  description: MDMA channel 8 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C8LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C8MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C8MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C8SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C8TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C8TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/C9BNDTR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).
  fields:
  - name: BNDT
    description: BNDT.
    bit_offset: 0
    bit_size: 17
  - name: BRSUM
    description: BRSUM.
    bit_offset: 18
    bit_size: 1
  - name: BRDUM
    description: BRDUM.
    bit_offset: 19
    bit_size: 1
  - name: BRC
    description: BRC.
    bit_offset: 20
    bit_size: 12
fieldset/C9BRUR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).
  fields:
  - name: SUV
    description: SUV.
    bit_offset: 0
    bit_size: 16
  - name: DUV
    description: DUV.
    bit_offset: 16
    bit_size: 16
fieldset/C9CR:
  description: This register is used to control the concerned channel.
  fields:
  - name: EN
    description: EN.
    bit_offset: 0
    bit_size: 1
  - name: TEIE
    description: TEIE.
    bit_offset: 1
    bit_size: 1
  - name: CTCIE
    description: CTCIE.
    bit_offset: 2
    bit_size: 1
  - name: BRTIE
    description: BRTIE.
    bit_offset: 3
    bit_size: 1
  - name: BTIE
    description: BTIE.
    bit_offset: 4
    bit_size: 1
  - name: TCIE
    description: TCIE.
    bit_offset: 5
    bit_size: 1
  - name: PL
    description: PL.
    bit_offset: 6
    bit_size: 2
  - name: BEX
    description: BEX.
    bit_offset: 12
    bit_size: 1
  - name: HEX
    description: HEX.
    bit_offset: 13
    bit_size: 1
  - name: WEX
    description: WEX.
    bit_offset: 14
    bit_size: 1
  - name: SWRQ
    description: SWRQ.
    bit_offset: 16
    bit_size: 1
fieldset/C9DAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M.
  fields:
  - name: DAR
    description: DAR.
    bit_offset: 0
    bit_size: 32
fieldset/C9ESR:
  description: MDMA channel 9 error status register.
  fields:
  - name: TEA
    description: TEA.
    bit_offset: 0
    bit_size: 7
  - name: TED
    description: TED.
    bit_offset: 7
    bit_size: 1
  - name: TELD
    description: TELD.
    bit_offset: 8
    bit_size: 1
  - name: TEMD
    description: TEMD.
    bit_offset: 9
    bit_size: 1
  - name: ASE
    description: ASE.
    bit_offset: 10
    bit_size: 1
  - name: BSE
    description: BSE.
    bit_offset: 11
    bit_size: 1
fieldset/C9IFCR:
  description: MDMA channel 9 interrupt flag clear register.
  fields:
  - name: CTEIF
    description: CTEIF.
    bit_offset: 0
    bit_size: 1
  - name: CCTCIF
    description: CCTCIF.
    bit_offset: 1
    bit_size: 1
  - name: CBRTIF
    description: CBRTIF.
    bit_offset: 2
    bit_size: 1
  - name: CBTIF
    description: CBTIF.
    bit_offset: 3
    bit_size: 1
  - name: CLTCIF
    description: CLTCIF.
    bit_offset: 4
    bit_size: 1
fieldset/C9ISR:
  description: MDMA channel 9 interrupt/status register.
  fields:
  - name: TEIF
    description: TEIF.
    bit_offset: 0
    bit_size: 1
  - name: CTCIF
    description: CTCIF.
    bit_offset: 1
    bit_size: 1
  - name: BRTIF
    description: BRTIF.
    bit_offset: 2
    bit_size: 1
  - name: BTIF
    description: BTIF.
    bit_offset: 3
    bit_size: 1
  - name: TCIF
    description: TCIF.
    bit_offset: 4
    bit_size: 1
  - name: CRQA
    description: CRQA.
    bit_offset: 16
    bit_size: 1
fieldset/C9LAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.
  fields:
  - name: LAR
    description: LAR.
    bit_offset: 0
    bit_size: 32
fieldset/C9MAR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).
  fields:
  - name: MAR
    description: MAR.
    bit_offset: 0
    bit_size: 32
fieldset/C9MDR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).
  fields:
  - name: MDR
    description: MDR.
    bit_offset: 0
    bit_size: 32
fieldset/C9SAR:
  description: In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).
  fields:
  - name: SAR
    description: SAR.
    bit_offset: 0
    bit_size: 32
fieldset/C9TBR:
  description: In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).
  fields:
  - name: TSEL
    description: TSEL.
    bit_offset: 0
    bit_size: 6
  - name: SBUS
    description: SBUS.
    bit_offset: 16
    bit_size: 1
  - name: DBUS
    description: DBUS.
    bit_offset: 17
    bit_size: 1
fieldset/C9TCR:
  description: This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).
  fields:
  - name: SINC
    description: SINC.
    bit_offset: 0
    bit_size: 2
  - name: DINC
    description: DINC.
    bit_offset: 2
    bit_size: 2
  - name: SSIZE
    description: SSIZE.
    bit_offset: 4
    bit_size: 2
  - name: DSIZE
    description: DSIZE.
    bit_offset: 6
    bit_size: 2
  - name: SINCOS
    description: SINCOS.
    bit_offset: 8
    bit_size: 2
  - name: DINCOS
    description: DINCOS.
    bit_offset: 10
    bit_size: 2
  - name: SBURST
    description: SBURST.
    bit_offset: 12
    bit_size: 3
  - name: DBURST
    description: DBURST.
    bit_offset: 15
    bit_size: 3
  - name: TLEN
    description: TLEN.
    bit_offset: 18
    bit_size: 7
  - name: PKE
    description: PKE.
    bit_offset: 25
    bit_size: 1
  - name: PAM
    description: PAM.
    bit_offset: 26
    bit_size: 2
  - name: TRGM
    description: TRGM.
    bit_offset: 28
    bit_size: 2
  - name: SWRM
    description: SWRM.
    bit_offset: 30
    bit_size: 1
  - name: BWM
    description: BWM.
    bit_offset: 31
    bit_size: 1
fieldset/GISR0:
  description: MDMA global interrupt/status register.
  fields:
  - name: GIF0
    description: GIF0.
    bit_offset: 0
    bit_size: 1
  - name: GIF1
    description: GIF1.
    bit_offset: 1
    bit_size: 1
  - name: GIF2
    description: GIF2.
    bit_offset: 2
    bit_size: 1
  - name: GIF3
    description: GIF3.
    bit_offset: 3
    bit_size: 1
  - name: GIF4
    description: GIF4.
    bit_offset: 4
    bit_size: 1
  - name: GIF5
    description: GIF5.
    bit_offset: 5
    bit_size: 1
  - name: GIF6
    description: GIF6.
    bit_offset: 6
    bit_size: 1
  - name: GIF7
    description: GIF7.
    bit_offset: 7
    bit_size: 1
  - name: GIF8
    description: GIF8.
    bit_offset: 8
    bit_size: 1
  - name: GIF9
    description: GIF9.
    bit_offset: 9
    bit_size: 1
  - name: GIF10
    description: GIF10.
    bit_offset: 10
    bit_size: 1
  - name: GIF11
    description: GIF11.
    bit_offset: 11
    bit_size: 1
  - name: GIF12
    description: GIF12.
    bit_offset: 12
    bit_size: 1
  - name: GIF13
    description: GIF13.
    bit_offset: 13
    bit_size: 1
  - name: GIF14
    description: GIF14.
    bit_offset: 14
    bit_size: 1
  - name: GIF15
    description: GIF15.
    bit_offset: 15
    bit_size: 1
  - name: GIF16
    description: GIF16.
    bit_offset: 16
    bit_size: 1
  - name: GIF17
    description: GIF17.
    bit_offset: 17
    bit_size: 1
  - name: GIF18
    description: GIF18.
    bit_offset: 18
    bit_size: 1
  - name: GIF19
    description: GIF19.
    bit_offset: 19
    bit_size: 1
  - name: GIF20
    description: GIF20.
    bit_offset: 20
    bit_size: 1
  - name: GIF21
    description: GIF21.
    bit_offset: 21
    bit_size: 1
  - name: GIF22
    description: GIF22.
    bit_offset: 22
    bit_size: 1
  - name: GIF23
    description: GIF23.
    bit_offset: 23
    bit_size: 1
  - name: GIF24
    description: GIF24.
    bit_offset: 24
    bit_size: 1
  - name: GIF25
    description: GIF25.
    bit_offset: 25
    bit_size: 1
  - name: GIF26
    description: GIF26.
    bit_offset: 26
    bit_size: 1
  - name: GIF27
    description: GIF27.
    bit_offset: 27
    bit_size: 1
  - name: GIF28
    description: GIF28.
    bit_offset: 28
    bit_size: 1
  - name: GIF29
    description: GIF29.
    bit_offset: 29
    bit_size: 1
  - name: GIF30
    description: GIF30.
    bit_offset: 30
    bit_size: 1
  - name: GIF31
    description: GIF31.
    bit_offset: 31
    bit_size: 1
fieldset/SGISR0:
  description: MDMA secure global interrupt/status register.
  fields:
  - name: GIF0
    description: GIF0.
    bit_offset: 0
    bit_size: 1
  - name: GIF1
    description: GIF1.
    bit_offset: 1
    bit_size: 1
  - name: GIF2
    description: GIF2.
    bit_offset: 2
    bit_size: 1
  - name: GIF3
    description: GIF3.
    bit_offset: 3
    bit_size: 1
  - name: GIF4
    description: GIF4.
    bit_offset: 4
    bit_size: 1
  - name: GIF5
    description: GIF5.
    bit_offset: 5
    bit_size: 1
  - name: GIF6
    description: GIF6.
    bit_offset: 6
    bit_size: 1
  - name: GIF7
    description: GIF7.
    bit_offset: 7
    bit_size: 1
  - name: GIF8
    description: GIF8.
    bit_offset: 8
    bit_size: 1
  - name: GIF9
    description: GIF9.
    bit_offset: 9
    bit_size: 1
  - name: GIF10
    description: GIF10.
    bit_offset: 10
    bit_size: 1
  - name: GIF11
    description: GIF11.
    bit_offset: 11
    bit_size: 1
  - name: GIF12
    description: GIF12.
    bit_offset: 12
    bit_size: 1
  - name: GIF13
    description: GIF13.
    bit_offset: 13
    bit_size: 1
  - name: GIF14
    description: GIF14.
    bit_offset: 14
    bit_size: 1
  - name: GIF15
    description: GIF15.
    bit_offset: 15
    bit_size: 1
  - name: GIF16
    description: GIF16.
    bit_offset: 16
    bit_size: 1
  - name: GIF17
    description: GIF17.
    bit_offset: 17
    bit_size: 1
  - name: GIF18
    description: GIF18.
    bit_offset: 18
    bit_size: 1
  - name: GIF19
    description: GIF19.
    bit_offset: 19
    bit_size: 1
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