block/LTDC:
  description: LTDC.
  items:
  - name: IDR
    description: LTDC identification register.
    byte_offset: 0
    access: Read
    fieldset: IDR
  - name: LCR
    description: LDTC layer count register.
    byte_offset: 4
    access: Read
    fieldset: LCR
  - name: SSCR
    description: 'This register defines the number of horizontal synchronization pixels minus 1 and the number of vertical synchronization lines minus 1. Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.'
    byte_offset: 8
    fieldset: SSCR
  - name: BPCR
    description: 'This register defines the accumulated number of horizontal synchronization and back porch pixels minus 1 (HSYNCwidth+HBP-1) and the accumulated number of vertical synchronization and back porch lines minus 1 (VSYNCheight+VBP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.'
    byte_offset: 12
    fieldset: BPCR
  - name: AWCR
    description: 'This register defines the accumulated number of horizontal synchronization, back porch and active pixels minus 1 (HSYNC width+HBP+activewidth-1) and the accumulated number of vertical synchronization, back porch lines and active lines minus 1 (VSYNCheight+BVBP+activeheight-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.'
    byte_offset: 16
    fieldset: AWCR
  - name: TWCR
    description: 'This register defines the accumulated number of horizontal synchronization, back porch, active and front porch pixels minus 1 (HSYNCwidth+HBP+activewidth+HFP-1) and the accumulated number of vertical synchronization, back porch lines, active and front lines minus 1 (VSYNCheight+BVBP+activeheight+VFP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.'
    byte_offset: 20
    fieldset: TWCR
  - name: GCR
    description: This register defines the global configuration of the LCD-TFT controller.
    byte_offset: 24
    fieldset: GCR
  - name: GC1R
    description: LTDC global configuration 1 register.
    byte_offset: 28
    access: Read
    fieldset: GC1R
  - name: GC2R
    description: LTDC global configuration 2 register.
    byte_offset: 32
    access: Read
    fieldset: GC2R
  - name: SRCR
    description: This register allows to reload either immediately or during the vertical blanking period, the shadow registers values to the active registers. The shadow registers are all Layer1 and Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR.
    byte_offset: 36
    fieldset: SRCR
  - name: BCCR
    description: This register defines the background color (RGB888).
    byte_offset: 44
    fieldset: BCCR
  - name: IER
    description: This register determines which status flags generate an interrupt request by setting the corresponding bit to 1.
    byte_offset: 52
    fieldset: IER
  - name: ISR
    description: This register returns the interrupt status flag.
    byte_offset: 56
    access: Read
    fieldset: ISR
  - name: ICR
    description: LTDC Interrupt Clear Register.
    byte_offset: 60
    access: Write
    fieldset: ICR
  - name: LIPCR
    description: This register defines the position of the line interrupt. The line value to be programmed depends on the timings parameters. Refer to Figure274.
    byte_offset: 64
    fieldset: LIPCR
  - name: CPSR
    description: LTDC current position status register.
    byte_offset: 68
    access: Read
    fieldset: CPSR
  - name: CDSR
    description: 'This register returns the status of the current display phase which is controlled by the HSYNC, VSYNC, and horizontal/vertical DE signals. Example: if the current display phase is the vertical synchronization, the VSYNCS bit is set (active high). If the current display phase is the horizontal synchronization, the HSYNCS bit is active high.'
    byte_offset: 72
    access: Read
    fieldset: CDSR
  - name: L1CR
    description: LTDC layer 1 control register.
    byte_offset: 132
    fieldset: L1CR
  - name: L1WHPCR
    description: This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register.
    byte_offset: 136
    fieldset: L1WHPCR
  - name: L1WVPCR
    description: This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register.
    byte_offset: 140
    fieldset: L1WVPCR
  - name: L1CKCR
    description: This register defines the color key value (RGB), that is used by the color keying.
    byte_offset: 144
    fieldset: L1CKCR
  - name: L1PFCR
    description: This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB).
    byte_offset: 148
    fieldset: L1PFCR
  - name: L1CACR
    description: This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register.
    byte_offset: 152
    fieldset: L1CACR
  - name: L1DCCR
    description: This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color.
    byte_offset: 156
    fieldset: L1DCCR
  - name: L1BFCR
    description: 'This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color.'
    byte_offset: 160
    fieldset: L1BFCR
  - name: L1CFBAR
    description: This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer.
    byte_offset: 172
    fieldset: L1CFBAR
  - name: L1CFBLR
    description: This register defines the color frame buffer line length and pitch.
    byte_offset: 176
    fieldset: L1CFBLR
  - name: L1CFBLNR
    description: This register defines the number of lines in the color frame buffer.
    byte_offset: 180
    fieldset: L1CFBLNR
  - name: L1CLUTWR
    description: This register defines the CLUT address and the RGB value.
    byte_offset: 196
    access: Write
    fieldset: L1CLUTWR
  - name: L2CR
    description: LTDC layer 2 control register.
    byte_offset: 260
    fieldset: L2CR
  - name: L2WHPCR
    description: This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register.
    byte_offset: 264
    fieldset: L2WHPCR
  - name: L2WVPCR
    description: This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register.
    byte_offset: 268
    fieldset: L2WVPCR
  - name: L2CKCR
    description: This register defines the color key value (RGB), that is used by the color keying.
    byte_offset: 272
    fieldset: L2CKCR
  - name: L2PFCR
    description: This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB).
    byte_offset: 276
    fieldset: L2PFCR
  - name: L2CACR
    description: This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register.
    byte_offset: 280
    fieldset: L2CACR
  - name: L2DCCR
    description: This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color.
    byte_offset: 284
    fieldset: L2DCCR
  - name: L2BFCR
    description: 'This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color.'
    byte_offset: 288
    fieldset: L2BFCR
  - name: L2CFBAR
    description: This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer.
    byte_offset: 300
    fieldset: L2CFBAR
  - name: L2CFBLR
    description: This register defines the color frame buffer line length and pitch.
    byte_offset: 304
    fieldset: L2CFBLR
  - name: L2CFBLNR
    description: This register defines the number of lines in the color frame buffer.
    byte_offset: 308
    fieldset: L2CFBLNR
  - name: L2CLUTWR
    description: This register defines the CLUT address and the RGB value.
    byte_offset: 324
    access: Write
    fieldset: L2CLUTWR
fieldset/AWCR:
  description: 'This register defines the accumulated number of horizontal synchronization, back porch and active pixels minus 1 (HSYNC width+HBP+activewidth-1) and the accumulated number of vertical synchronization, back porch lines and active lines minus 1 (VSYNCheight+BVBP+activeheight-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.'
  fields:
  - name: AAH
    description: AAH.
    bit_offset: 0
    bit_size: 12
  - name: AAW
    description: AAW.
    bit_offset: 16
    bit_size: 12
fieldset/BCCR:
  description: This register defines the background color (RGB888).
  fields:
  - name: BCBLUE
    description: BCBLUE.
    bit_offset: 0
    bit_size: 8
  - name: BCGREEN
    description: BCGREEN.
    bit_offset: 8
    bit_size: 8
  - name: BCRED
    description: BCRED.
    bit_offset: 16
    bit_size: 8
fieldset/BPCR:
  description: 'This register defines the accumulated number of horizontal synchronization and back porch pixels minus 1 (HSYNCwidth+HBP-1) and the accumulated number of vertical synchronization and back porch lines minus 1 (VSYNCheight+VBP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.'
  fields:
  - name: AVBP
    description: AVBP.
    bit_offset: 0
    bit_size: 12
  - name: AHBP
    description: AHBP.
    bit_offset: 16
    bit_size: 12
fieldset/CDSR:
  description: 'This register returns the status of the current display phase which is controlled by the HSYNC, VSYNC, and horizontal/vertical DE signals. Example: if the current display phase is the vertical synchronization, the VSYNCS bit is set (active high). If the current display phase is the horizontal synchronization, the HSYNCS bit is active high.'
  fields:
  - name: VDES
    description: VDES.
    bit_offset: 0
    bit_size: 1
  - name: HDES
    description: HDES.
    bit_offset: 1
    bit_size: 1
  - name: VSYNCS
    description: VSYNCS.
    bit_offset: 2
    bit_size: 1
  - name: HSYNCS
    description: HSYNCS.
    bit_offset: 3
    bit_size: 1
fieldset/CPSR:
  description: LTDC current position status register.
  fields:
  - name: CYPOS
    description: CYPOS.
    bit_offset: 0
    bit_size: 16
  - name: CXPOS
    description: CXPOS.
    bit_offset: 16
    bit_size: 16
fieldset/GC1R:
  description: LTDC global configuration 1 register.
  fields:
  - name: WBCH
    description: WBCH.
    bit_offset: 0
    bit_size: 4
  - name: WGCH
    description: WGCH.
    bit_offset: 4
    bit_size: 4
  - name: WRCH
    description: WRCH.
    bit_offset: 8
    bit_size: 4
  - name: PRBEN
    description: PRBEN.
    bit_offset: 12
    bit_size: 1
  - name: DT
    description: DT.
    bit_offset: 14
    bit_size: 2
  - name: GCT
    description: GCT.
    bit_offset: 17
    bit_size: 3
  - name: SHREN
    description: SHREN.
    bit_offset: 21
    bit_size: 1
  - name: BCP
    description: BCP.
    bit_offset: 22
    bit_size: 1
  - name: BBEN
    description: BBEN.
    bit_offset: 23
    bit_size: 1
  - name: LNIP
    description: LNIP.
    bit_offset: 24
    bit_size: 1
  - name: TP
    description: TP.
    bit_offset: 25
    bit_size: 1
  - name: IPP
    description: IPP.
    bit_offset: 26
    bit_size: 1
  - name: SPP
    description: SPP.
    bit_offset: 27
    bit_size: 1
  - name: DWP
    description: DWP.
    bit_offset: 28
    bit_size: 1
  - name: STREN
    description: STREN.
    bit_offset: 29
    bit_size: 1
  - name: BMEN
    description: BMEN.
    bit_offset: 31
    bit_size: 1
fieldset/GC2R:
  description: LTDC global configuration 2 register.
  fields:
  - name: EDCEN
    description: EDCEN.
    bit_offset: 0
    bit_size: 1
  - name: STSAEN
    description: STSAEN.
    bit_offset: 1
    bit_size: 1
  - name: DVAEN
    description: DVAEN.
    bit_offset: 2
    bit_size: 1
  - name: DPAEN
    description: DPAEN.
    bit_offset: 3
    bit_size: 1
  - name: BW
    description: BW.
    bit_offset: 4
    bit_size: 3
  - name: EDCA
    description: EDCA.
    bit_offset: 7
    bit_size: 1
fieldset/GCR:
  description: This register defines the global configuration of the LCD-TFT controller.
  fields:
  - name: LTDCEN
    description: LTDCEN.
    bit_offset: 0
    bit_size: 1
  - name: DBW
    description: DBW.
    bit_offset: 4
    bit_size: 3
  - name: DGW
    description: DGW.
    bit_offset: 8
    bit_size: 3
  - name: DRW
    description: DRW.
    bit_offset: 12
    bit_size: 3
  - name: DEN
    description: DEN.
    bit_offset: 16
    bit_size: 1
  - name: PCPOL
    description: PCPOL.
    bit_offset: 28
    bit_size: 1
  - name: DEPOL
    description: DEPOL.
    bit_offset: 29
    bit_size: 1
  - name: VSPOL
    description: VSPOL.
    bit_offset: 30
    bit_size: 1
  - name: HSPOL
    description: HSPOL.
    bit_offset: 31
    bit_size: 1
fieldset/ICR:
  description: LTDC Interrupt Clear Register.
  fields:
  - name: CLIF
    description: CLIF.
    bit_offset: 0
    bit_size: 1
  - name: CFUIF
    description: CFUIF.
    bit_offset: 1
    bit_size: 1
  - name: CTERRIF
    description: CTERRIF.
    bit_offset: 2
    bit_size: 1
  - name: CRRIF
    description: CRRIF.
    bit_offset: 3
    bit_size: 1
fieldset/IDR:
  description: LTDC identification register.
  fields:
  - name: REV
    description: REV.
    bit_offset: 0
    bit_size: 8
  - name: MINVER
    description: MINVER.
    bit_offset: 8
    bit_size: 8
  - name: MAJVER
    description: MAJVER.
    bit_offset: 16
    bit_size: 8
fieldset/IER:
  description: This register determines which status flags generate an interrupt request by setting the corresponding bit to 1.
  fields:
  - name: LIE
    description: LIE.
    bit_offset: 0
    bit_size: 1
  - name: FUIE
    description: FUIE.
    bit_offset: 1
    bit_size: 1
  - name: TERRIE
    description: TERRIE.
    bit_offset: 2
    bit_size: 1
  - name: RRIE
    description: RRIE.
    bit_offset: 3
    bit_size: 1
fieldset/ISR:
  description: This register returns the interrupt status flag.
  fields:
  - name: LIF
    description: LIF.
    bit_offset: 0
    bit_size: 1
  - name: FUIF
    description: FUIF.
    bit_offset: 1
    bit_size: 1
  - name: TERRIF
    description: TERRIF.
    bit_offset: 2
    bit_size: 1
  - name: RRIF
    description: RRIF.
    bit_offset: 3
    bit_size: 1
fieldset/L1BFCR:
  description: 'This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color.'
  fields:
  - name: BF2
    description: BF2.
    bit_offset: 0
    bit_size: 3
  - name: BF1
    description: BF1.
    bit_offset: 8
    bit_size: 3
fieldset/L1CACR:
  description: This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register.
  fields:
  - name: CONSTA
    description: CONSTA.
    bit_offset: 0
    bit_size: 8
fieldset/L1CFBAR:
  description: This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer.
  fields:
  - name: CFBADD
    description: CFBADD.
    bit_offset: 0
    bit_size: 32
fieldset/L1CFBLNR:
  description: This register defines the number of lines in the color frame buffer.
  fields:
  - name: CFBLNBR
    description: CFBLNBR.
    bit_offset: 0
    bit_size: 12
fieldset/L1CFBLR:
  description: This register defines the color frame buffer line length and pitch.
  fields:
  - name: CFBLL
    description: CFBLL.
    bit_offset: 0
    bit_size: 14
  - name: CFBP
    description: CFBP.
    bit_offset: 16
    bit_size: 14
fieldset/L1CKCR:
  description: This register defines the color key value (RGB), that is used by the color keying.
  fields:
  - name: CKBLUE
    description: CKBLUE.
    bit_offset: 0
    bit_size: 8
  - name: CKGREEN
    description: CKGREEN.
    bit_offset: 8
    bit_size: 8
  - name: CKRED
    description: CKRED.
    bit_offset: 16
    bit_size: 8
fieldset/L1CLUTWR:
  description: This register defines the CLUT address and the RGB value.
  fields:
  - name: BLUE
    description: BLUE.
    bit_offset: 0
    bit_size: 8
  - name: GREEN
    description: GREEN.
    bit_offset: 8
    bit_size: 8
  - name: RED
    description: RED.
    bit_offset: 16
    bit_size: 8
  - name: CLUTADD
    description: CLUTADD.
    bit_offset: 24
    bit_size: 8
fieldset/L1CR:
  description: LTDC layer 1 control register.
  fields:
  - name: LEN
    description: LEN.
    bit_offset: 0
    bit_size: 1
  - name: COLKEN
    description: COLKEN.
    bit_offset: 1
    bit_size: 1
  - name: CLUTEN
    description: CLUTEN.
    bit_offset: 4
    bit_size: 1
fieldset/L1DCCR:
  description: This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color.
  fields:
  - name: DCBLUE
    description: DCBLUE.
    bit_offset: 0
    bit_size: 8
  - name: DCGREEN
    description: DCGREEN.
    bit_offset: 8
    bit_size: 8
  - name: DCRED
    description: DCRED.
    bit_offset: 16
    bit_size: 8
  - name: DCALPHA
    description: DCALPHA.
    bit_offset: 24
    bit_size: 8
fieldset/L1PFCR:
  description: This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB).
  fields:
  - name: PF
    description: PF.
    bit_offset: 0
    bit_size: 3
fieldset/L1WHPCR:
  description: This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register.
  fields:
  - name: WHSTPOS
    description: WHSTPOS.
    bit_offset: 0
    bit_size: 12
  - name: WHSPPOS
    description: WHSPPOS.
    bit_offset: 16
    bit_size: 12
fieldset/L1WVPCR:
  description: This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register.
  fields:
  - name: WVSTPOS
    description: WVSTPOS.
    bit_offset: 0
    bit_size: 12
  - name: WVSPPOS
    description: WVSPPOS.
    bit_offset: 16
    bit_size: 12
fieldset/L2BFCR:
  description: 'This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color.'
  fields:
  - name: BF2
    description: BF2.
    bit_offset: 0
    bit_size: 3
  - name: BF1
    description: BF1.
    bit_offset: 8
    bit_size: 3
fieldset/L2CACR:
  description: This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register.
  fields:
  - name: CONSTA
    description: CONSTA.
    bit_offset: 0
    bit_size: 8
fieldset/L2CFBAR:
  description: This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer.
  fields:
  - name: CFBADD
    description: CFBADD.
    bit_offset: 0
    bit_size: 32
fieldset/L2CFBLNR:
  description: This register defines the number of lines in the color frame buffer.
  fields:
  - name: CFBLNBR
    description: CFBLNBR.
    bit_offset: 0
    bit_size: 12
fieldset/L2CFBLR:
  description: This register defines the color frame buffer line length and pitch.
  fields:
  - name: CFBLL
    description: CFBLL.
    bit_offset: 0
    bit_size: 14
  - name: CFBP
    description: CFBP.
    bit_offset: 16
    bit_size: 14
fieldset/L2CKCR:
  description: This register defines the color key value (RGB), that is used by the color keying.
  fields:
  - name: CKBLUE
    description: CKBLUE.
    bit_offset: 0
    bit_size: 8
  - name: CKGREEN
    description: CKGREEN.
    bit_offset: 8
    bit_size: 8
  - name: CKRED
    description: CKRED.
    bit_offset: 16
    bit_size: 8
fieldset/L2CLUTWR:
  description: This register defines the CLUT address and the RGB value.
  fields:
  - name: BLUE
    description: BLUE.
    bit_offset: 0
    bit_size: 8
  - name: GREEN
    description: GREEN.
    bit_offset: 8
    bit_size: 8
  - name: RED
    description: RED.
    bit_offset: 16
    bit_size: 8
  - name: CLUTADD
    description: CLUTADD.
    bit_offset: 24
    bit_size: 8
fieldset/L2CR:
  description: LTDC layer 2 control register.
  fields:
  - name: LEN
    description: LEN.
    bit_offset: 0
    bit_size: 1
  - name: COLKEN
    description: COLKEN.
    bit_offset: 1
    bit_size: 1
  - name: CLUTEN
    description: CLUTEN.
    bit_offset: 4
    bit_size: 1
fieldset/L2DCCR:
  description: This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color.
  fields:
  - name: DCBLUE
    description: DCBLUE.
    bit_offset: 0
    bit_size: 8
  - name: DCGREEN
    description: DCGREEN.
    bit_offset: 8
    bit_size: 8
  - name: DCRED
    description: DCRED.
    bit_offset: 16
    bit_size: 8
  - name: DCALPHA
    description: DCALPHA.
    bit_offset: 24
    bit_size: 8
fieldset/L2PFCR:
  description: This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB).
  fields:
  - name: PF
    description: PF.
    bit_offset: 0
    bit_size: 3
fieldset/L2WHPCR:
  description: This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register.
  fields:
  - name: WHSTPOS
    description: WHSTPOS.
    bit_offset: 0
    bit_size: 12
  - name: WHSPPOS
    description: WHSPPOS.
    bit_offset: 16
    bit_size: 12
fieldset/L2WVPCR:
  description: This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register.
  fields:
  - name: WVSTPOS
    description: WVSTPOS.
    bit_offset: 0
    bit_size: 12
  - name: WVSPPOS
    description: WVSPPOS.
    bit_offset: 16
    bit_size: 12
fieldset/LCR:
  description: LDTC layer count register.
  fields:
  - name: LNBR
    description: LNBR.
    bit_offset: 0
    bit_size: 8
fieldset/LIPCR:
  description: This register defines the position of the line interrupt. The line value to be programmed depends on the timings parameters. Refer to Figure274.
  fields:
  - name: LIPOS
    description: LIPOS.
    bit_offset: 0
    bit_size: 12
fieldset/SRCR:
  description: This register allows to reload either immediately or during the vertical blanking period, the shadow registers values to the active registers. The shadow registers are all Layer1 and Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR.
  fields:
  - name: IMR
    description: IMR.
    bit_offset: 0
    bit_size: 1
  - name: VBR
    description: VBR.
    bit_offset: 1
    bit_size: 1
fieldset/SSCR:
  description: 'This register defines the number of horizontal synchronization pixels minus 1 and the number of vertical synchronization lines minus 1. Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.'
  fields:
  - name: VSH
    description: VSH.
    bit_offset: 0
    bit_size: 12
  - name: HSW
    description: HSW.
    bit_offset: 16
    bit_size: 12
fieldset/TWCR:
  description: 'This register defines the accumulated number of horizontal synchronization, back porch, active and front porch pixels minus 1 (HSYNCwidth+HBP+activewidth+HFP-1) and the accumulated number of vertical synchronization, back porch lines, active and front lines minus 1 (VSYNCheight+BVBP+activeheight+VFP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.'
  fields:
  - name: TOTALH
    description: TOTALH.
    bit_offset: 0
    bit_size: 12
  - name: TOTALW
    description: TOTALW.
    bit_offset: 16
    bit_size: 12