block/GPIOA:
  description: GPIOA.
  items:
  - name: MODER
    description: GPIO port mode register.
    byte_offset: 0
    fieldset: MODER
  - name: OTYPER
    description: GPIO port output type register.
    byte_offset: 4
    fieldset: OTYPER
  - name: OSPEEDR
    description: GPIO port output speed register.
    byte_offset: 8
    fieldset: OSPEEDR
  - name: PUPDR
    description: GPIO port pull-up/pull-down register.
    byte_offset: 12
    fieldset: PUPDR
  - name: IDR
    description: GPIO port input data register.
    byte_offset: 16
    access: Read
    fieldset: IDR
  - name: ODR
    description: GPIO port output data register.
    byte_offset: 20
    fieldset: ODR
  - name: BSRR
    description: GPIO port bit set/reset register.
    byte_offset: 24
    access: Write
    fieldset: BSRR
  - name: LCKR
    description: This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).
    byte_offset: 28
    fieldset: LCKR
  - name: AFRL
    description: GPIO alternate function low register.
    byte_offset: 32
    fieldset: AFRL
  - name: AFRH
    description: GPIO alternate function high register.
    byte_offset: 36
    fieldset: AFRH
  - name: BRR
    description: GPIO port bit reset register.
    byte_offset: 40
    access: Write
    fieldset: BRR
  - name: HWCFGR10
    description: 'For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:.'
    byte_offset: 968
    access: Read
    fieldset: HWCFGR10
  - name: HWCFGR9
    description: 'For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:.'
    byte_offset: 972
    access: Read
    fieldset: HWCFGR9
  - name: HWCFGR8
    description: 'For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:.'
    byte_offset: 976
    access: Read
    fieldset: HWCFGR8
  - name: HWCFGR7
    description: GPIO hardware configuration register 7.
    byte_offset: 980
    access: Read
    fieldset: HWCFGR7
  - name: HWCFGR6
    description: GPIO hardware configuration register 6.
    byte_offset: 984
    access: Read
    fieldset: HWCFGR6
  - name: HWCFGR5
    description: GPIO hardware configuration register 5.
    byte_offset: 988
    access: Read
    fieldset: HWCFGR5
  - name: HWCFGR4
    description: GPIO hardware configuration register 4.
    byte_offset: 992
    access: Read
    fieldset: HWCFGR4
  - name: HWCFGR3
    description: GPIO hardware configuration register 3.
    byte_offset: 996
    access: Read
    fieldset: HWCFGR3
  - name: HWCFGR2
    description: GPIO hardware configuration register 2.
    byte_offset: 1000
    access: Read
    fieldset: HWCFGR2
  - name: HWCFGR1
    description: GPIO hardware configuration register 1.
    byte_offset: 1004
    access: Read
    fieldset: HWCFGR1
  - name: HWCFGR0
    description: GPIO hardware configuration register 0.
    byte_offset: 1008
    access: Read
    fieldset: HWCFGR0
  - name: VERR
    description: GPIO version register.
    byte_offset: 1012
    access: Read
    fieldset: VERR
  - name: IPIDR
    description: GPIO identification register.
    byte_offset: 1016
    access: Read
    fieldset: IPIDR
  - name: SIDR
    description: GPIO size identification register.
    byte_offset: 1020
    access: Read
    fieldset: SIDR
fieldset/AFRH:
  description: GPIO alternate function high register.
  fields: []
fieldset/AFRL:
  description: GPIO alternate function low register.
  fields:
  - name: AFR
    description: AFR%s.
    bit_offset: 0
    bit_size: 4
    array:
      len: 8
      stride: 4
    enum: AFR
fieldset/BRR:
  description: GPIO port bit reset register.
  fields:
  - name: BR
    description: Port x reset pin %s.
    bit_offset: 0
    bit_size: 1
    array:
      len: 16
      stride: 1
    enum: BRR_BR
fieldset/BSRR:
  description: GPIO port bit set/reset register.
  fields:
  - name: BS
    description: Port x set pin %s.
    bit_offset: 0
    bit_size: 1
    array:
      len: 16
      stride: 1
    enum: BS
  - name: BR
    description: Port x reset pin %s.
    bit_offset: 16
    bit_size: 1
    array:
      len: 16
      stride: 1
    enum: BSRR_BR
fieldset/HWCFGR0:
  description: GPIO hardware configuration register 0.
  fields:
  - name: OR_RES
    description: OR_RES.
    bit_offset: 0
    bit_size: 16
fieldset/HWCFGR1:
  description: GPIO hardware configuration register 1.
  fields:
  - name: AFRH_RES
    description: AFRH_RES.
    bit_offset: 0
    bit_size: 32
fieldset/HWCFGR10:
  description: 'For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:.'
  fields:
  - name: AHB_IOP
    description: AHB_IOP.
    bit_offset: 0
    bit_size: 4
  - name: AF_SIZE
    description: AF_SIZE.
    bit_offset: 4
    bit_size: 4
  - name: SPEED_CFG
    description: SPEED_CFG.
    bit_offset: 8
    bit_size: 4
  - name: LOCK_CFG
    description: LOCK_CFG.
    bit_offset: 12
    bit_size: 4
  - name: SEC_CFG
    description: SEC_CFG.
    bit_offset: 16
    bit_size: 4
  - name: OR_CFG
    description: OR_CFG.
    bit_offset: 20
    bit_size: 4
fieldset/HWCFGR2:
  description: GPIO hardware configuration register 2.
  fields:
  - name: AFRL_RES
    description: AFRL_RES.
    bit_offset: 0
    bit_size: 32
fieldset/HWCFGR3:
  description: GPIO hardware configuration register 3.
  fields:
  - name: ODR_RES
    description: ODR_RES.
    bit_offset: 0
    bit_size: 16
  - name: OTYPER_RES
    description: OTYPER_RES.
    bit_offset: 16
    bit_size: 16
fieldset/HWCFGR4:
  description: GPIO hardware configuration register 4.
  fields:
  - name: OSPEED_RES
    description: OSPEED_RES.
    bit_offset: 0
    bit_size: 32
fieldset/HWCFGR5:
  description: GPIO hardware configuration register 5.
  fields:
  - name: PUPDR_RES
    description: PUPDR_RES.
    bit_offset: 0
    bit_size: 32
fieldset/HWCFGR6:
  description: GPIO hardware configuration register 6.
  fields:
  - name: MODER_RES
    description: MODER_RES.
    bit_offset: 0
    bit_size: 32
fieldset/HWCFGR7:
  description: GPIO hardware configuration register 7.
  fields:
  - name: AF_PRIO0
    description: AF_PRIO0.
    bit_offset: 0
    bit_size: 4
  - name: AF_PRIO1
    description: AF_PRIO1.
    bit_offset: 4
    bit_size: 4
  - name: AF_PRIO2
    description: AF_PRIO2.
    bit_offset: 8
    bit_size: 4
  - name: AF_PRIO3
    description: AF_PRIO3.
    bit_offset: 12
    bit_size: 4
  - name: AF_PRIO4
    description: AF_PRIO4.
    bit_offset: 16
    bit_size: 4
  - name: AF_PRIO5
    description: AF_PRIO5.
    bit_offset: 20
    bit_size: 4
  - name: AF_PRIO6
    description: AF_PRIO6.
    bit_offset: 24
    bit_size: 4
  - name: AF_PRIO7
    description: AF_PRIO7.
    bit_offset: 28
    bit_size: 4
fieldset/HWCFGR8:
  description: 'For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:.'
  fields:
  - name: AF_PRIO8
    description: AF_PRIO8.
    bit_offset: 0
    bit_size: 4
  - name: AF_PRIO9
    description: AF_PRIO9.
    bit_offset: 4
    bit_size: 4
  - name: AF_PRIO10
    description: AF_PRIO10.
    bit_offset: 8
    bit_size: 4
  - name: AF_PRIO11
    description: AF_PRIO11.
    bit_offset: 12
    bit_size: 4
  - name: AF_PRIO12
    description: AF_PRIO12.
    bit_offset: 16
    bit_size: 4
  - name: AF_PRIO13
    description: AF_PRIO13.
    bit_offset: 20
    bit_size: 4
  - name: AF_PRIO14
    description: AF_PRIO14.
    bit_offset: 24
    bit_size: 4
  - name: AF_PRIO15
    description: AF_PRIO15.
    bit_offset: 28
    bit_size: 4
fieldset/HWCFGR9:
  description: 'For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:.'
  fields:
  - name: EN_IO
    description: EN_IO.
    bit_offset: 0
    bit_size: 16
fieldset/IDR:
  description: GPIO port input data register.
  fields:
  - name: IDR
    description: Port input data pin %s.
    bit_offset: 0
    bit_size: 1
    array:
      len: 16
      stride: 1
    enum: IDR
fieldset/IPIDR:
  description: GPIO identification register.
  fields:
  - name: IPIDR
    description: IPIDR.
    bit_offset: 0
    bit_size: 32
fieldset/LCKR:
  description: This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).
  fields:
  - name: LCK
    description: Port x lock pin %s.
    bit_offset: 0
    bit_size: 1
    array:
      len: 16
      stride: 1
    enum: LCK
  - name: LCKK
    description: LCKK.
    bit_offset: 16
    bit_size: 1
    enum: LCKK
fieldset/MODER:
  description: GPIO port mode register.
  fields:
  - name: MODER
    description: Port x configuration pin %s.
    bit_offset: 0
    bit_size: 2
    array:
      len: 16
      stride: 2
    enum: MODER
fieldset/ODR:
  description: GPIO port output data register.
  fields:
  - name: ODR
    description: Port output data pin %s.
    bit_offset: 0
    bit_size: 1
    array:
      len: 16
      stride: 1
    enum: ODR
fieldset/OSPEEDR:
  description: GPIO port output speed register.
  fields:
  - name: OSPEEDR
    description: Port x configuration pin %s.
    bit_offset: 0
    bit_size: 2
    array:
      len: 16
      stride: 2
    enum: OSPEEDR
fieldset/OTYPER:
  description: GPIO port output type register.
  fields:
  - name: OT
    description: Port x configuration pin %s.
    bit_offset: 0
    bit_size: 1
    array:
      len: 16
      stride: 1
    enum: OT
fieldset/PUPDR:
  description: GPIO port pull-up/pull-down register.
  fields:
  - name: PUPDR
    description: Port x configuration pin %s.
    bit_offset: 0
    bit_size: 2
    array:
      len: 16
      stride: 2
    enum: PUPDR
fieldset/SIDR:
  description: GPIO size identification register.
  fields:
  - name: SIDR
    description: SIDR.
    bit_offset: 0
    bit_size: 32
fieldset/VERR:
  description: GPIO version register.
  fields:
  - name: MINREV
    description: MINREV.
    bit_offset: 0
    bit_size: 4
  - name: MAJREV
    description: MAJREV.
    bit_offset: 4
    bit_size: 4
enum/AFR:
  bit_size: 4
  variants:
  - name: AF0
    description: AF0.
    value: 0
  - name: AF1
    description: AF1.
    value: 1
  - name: AF2
    description: AF2.
    value: 2
  - name: AF3
    description: AF3.
    value: 3
  - name: AF4
    description: AF4.
    value: 4
  - name: AF5
    description: AF5.
    value: 5
  - name: AF6
    description: AF6.
    value: 6
  - name: AF7
    description: AF7.
    value: 7
  - name: AF8
    description: AF8.
    value: 8
  - name: AF9
    description: AF9.
    value: 9
  - name: AF10
    description: AF10.
    value: 10
  - name: AF11
    description: AF11.
    value: 11
  - name: AF12
    description: AF12.
    value: 12
  - name: AF13
    description: AF13.
    value: 13
  - name: AF14
    description: AF14.
    value: 14
  - name: AF15
    description: AF15.
    value: 15
enum/BRR_BR:
  bit_size: 1
  variants:
  - name: NoAction
    description: No action on the corresponding ODx bit.
    value: 0
  - name: Reset
    description: Reset the ODx bit.
    value: 1
enum/BS:
  bit_size: 1
  variants:
  - name: Set
    description: Sets the corresponding ODRx bit.
    value: 1
enum/BSRR_BR:
  bit_size: 1
  variants:
  - name: Reset
    description: Resets the corresponding ODRx bit.
    value: 1
enum/IDR:
  bit_size: 1
  variants:
  - name: Low
    description: Input is logic low.
    value: 0
  - name: High
    description: Input is logic high.
    value: 1
enum/LCK:
  bit_size: 1
  variants:
  - name: Unlocked
    description: Port configuration not locked.
    value: 0
  - name: Locked
    description: Port configuration locked.
    value: 1
enum/LCKK:
  bit_size: 1
  variants:
  - name: NotActive
    description: Port configuration lock key not active.
    value: 0
  - name: Active
    description: Port configuration lock key active.
    value: 1
enum/MODER:
  bit_size: 2
  variants:
  - name: Input
    description: Input mode (reset state).
    value: 0
  - name: Output
    description: General purpose output mode.
    value: 1
  - name: Alternate
    description: Alternate function mode.
    value: 2
  - name: Analog
    description: Analog mode.
    value: 3
enum/ODR:
  bit_size: 1
  variants:
  - name: Low
    description: Set output to logic low.
    value: 0
  - name: High
    description: Set output to logic high.
    value: 1
enum/OSPEEDR:
  bit_size: 2
  variants:
  - name: LowSpeed
    description: Low speed.
    value: 0
  - name: MediumSpeed
    description: Medium speed.
    value: 1
  - name: HighSpeed
    description: High speed.
    value: 2
  - name: VeryHighSpeed
    description: Very high speed.
    value: 3
enum/OT:
  bit_size: 1
  variants:
  - name: PushPull
    description: Output push-pull (reset state).
    value: 0
  - name: OpenDrain
    description: Output open-drain.
    value: 1
enum/PUPDR:
  bit_size: 2
  variants:
  - name: Floating
    description: No pull-up, pull-down.
    value: 0
  - name: PullUp
    description: Pull-up.
    value: 1
  - name: PullDown
    description: Pull-down.
    value: 2