block/FMC:
  description: FMC register block.
  items:
  - name: BCR1
    description: This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
    byte_offset: 0
    fieldset: BCR1
  - name: BTR1
    description: 'This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).'
    byte_offset: 4
    fieldset: BTR1
  - name: BCR2
    description: This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
    byte_offset: 8
    fieldset: BCR2
  - name: BTR2
    description: 'This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).'
    byte_offset: 12
    fieldset: BTR2
  - name: BCR3
    description: This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
    byte_offset: 16
    fieldset: BCR3
  - name: BTR3
    description: 'This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).'
    byte_offset: 20
    fieldset: BTR3
  - name: BCR4
    description: This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
    byte_offset: 24
    fieldset: BCR4
  - name: BTR4
    description: 'This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).'
    byte_offset: 28
    fieldset: BTR4
  - name: PCSCNTR
    description: This register contains the PSRAM chip select counter value for synchronous mode. The chip select counter is common to all banks and can be enabled separately on each bank. During PSRAM read or write accesses, this value is loaded into a timer which is decremented using the fmc_ker_ck while the NE signal is held low. When the timer reaches 0, the PSRAM controller splits the current access, toggles NE to allow PSRAM device refresh and restarts a new access. The programmed counter value guarantees a maximum NE pulse width (tCEM) as specified for PSRAM devices. The counter is reloaded and starts decrementing each time a new access is started by a transition of NE from high to low. h.
    byte_offset: 32
    fieldset: PCSCNTR
  - name: PCR
    description: NAND Flash Programmable control register.
    byte_offset: 128
    fieldset: PCR
  - name: SR
    description: This register contains information about the AXI interface isolation status and the NAND write requests status. The FMC has to be disabled before modifying some registers. As requests might be pending, it is necessary to wait till the AXI interface is stable and the core of the block is totally isolated from its AXI interface before reconfiguring the registers. The PEF and PNWEF bits indicate the status of the pipe. If Hamming algorithm is used, the ECC is calculated while data are written to the memory. To read the correct ECC, the software must consequently wait untill no write request to the NAND controller are pending, by polling PEF and NWRF bits.
    byte_offset: 132
    access: Read
    fieldset: SR
  - name: PMEM
    description: The FMC_PMEM read/write register contains NAND Flash memory bank timing information. This information is used to access the NAND Flash common memory space for command, address write accesses or data read/write accesses.
    byte_offset: 136
    fieldset: PMEM
  - name: PATT
    description: 'The FMC_PATT read/write register contains NAND Flash memory bank timing information. It is used for 8-bit accesses to the NAND Flash attribute memory space during the last address write access when the timing differs from previous accesses (for Ready/Busy management, refer to Section25.8.5: NAND Flash prewait function).'
    byte_offset: 140
    fieldset: PATT
  - name: HPR
    description: This register is used during read accesses in conjunction with the FMC sequencer. It contains the current error correction code value computed by the FMC NAND controller Hamming module. When the FMC sequencer reads data from a NAND Flash memory page at the correct address, the data read are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area and stored in the and the FMC_HPR, to determine whether a page is valid, and to correct it otherwise. The FMC_HPR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
    byte_offset: 144
    access: Read
    fieldset: HPR
  - name: HECCR
    description: 'This register contain the current error correction code value computed by the FMC NAND controller Hamming module.When the CPU reads/writes data from/to a NAND Flash memory page at the correct address (refer to Section25.8.6: NAND ECC controller), the data read/written from/to the NAND Flash memory are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and to correct it otherwise. The FMC_HECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.'
    byte_offset: 148
    access: Read
    fieldset: HECCR
  - name: BWTR1
    description: This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
    byte_offset: 260
    fieldset: BWTR1
  - name: BWTR2
    description: This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
    byte_offset: 268
    fieldset: BWTR2
  - name: BWTR3
    description: This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
    byte_offset: 276
    fieldset: BWTR3
  - name: BWTR4
    description: This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
    byte_offset: 284
    fieldset: BWTR4
  - name: CSQCR
    description: FMC NAND Command Sequencer Control Register.
    byte_offset: 512
    access: Write
    fieldset: CSQCR
  - name: CSQCFGR1
    description: FMC NAND Command Sequencer Configuration Register 1.
    byte_offset: 516
    fieldset: CSQCFGR1
  - name: CSQCFGR2
    description: This register is used to configure the command sequencer to issue random read/ write commands to read/ write data by sector and automatically read/write data from NAND Flash memory at a programmable address offset. This is useful when performing a sector read/write operation followed by an ECC read/write operation in the NAND Flash spare area.The command sequencer generates the random commands untill all the sectors are read/written..
    byte_offset: 520
    fieldset: CSQCFGR2
  - name: CSQCFGR3
    description: FMC NAND sequencer configuration register 3.
    byte_offset: 524
    fieldset: CSQCFGR3
  - name: CSQAR1
    description: This register is used to define the value of address cycles 1 to 4 to be issued by the command sequencer.
    byte_offset: 528
    fieldset: CSQAR1
  - name: CSQAR2
    description: This register is used to program the fifth address cycle and the address offset in spare area. It also selects the chip enable.
    byte_offset: 532
    fieldset: CSQAR2
  - name: CSQIER
    description: FMC NAND Command Sequencer Interrupt Enable Register.
    byte_offset: 544
    fieldset: CSQIER
  - name: CSQISR
    description: FMC NAND Command Sequencer Interrupt Status Register.
    byte_offset: 548
    fieldset: CSQISR
  - name: CSQICR
    description: FMC NAND Command Sequencer Interrupt Clear Register.
    byte_offset: 552
    access: Write
    fieldset: CSQICR
  - name: CSQEMSR
    description: This register holds a sector error mapping status when the whole transfer is complete.
    byte_offset: 560
    access: Read
    fieldset: CSQEMSR
  - name: BCHIER
    description: FMC BCH Interrupt enable register.
    byte_offset: 592
    fieldset: BCHIER
  - name: BCHISR
    description: This register holds the status of BCH encoder/decoder after processing each sector. When the sequencer is used, this register is automatically cleared.
    byte_offset: 596
    access: Read
    fieldset: BCHISR
  - name: BCHICR
    description: FMC BCH Interrupt Clear Register.
    byte_offset: 600
    access: Write
    fieldset: BCHICR
  - name: BCHPBR1
    description: These registers contain the BCH parity bits (BCHPB). For the BCH 4-bit, only BCHPB[51:0] are significant and for the BCH 8-bit BCHPB[103:0] are significant.
    byte_offset: 608
    access: Read
    fieldset: BCHPBR1
  - name: BCHPBR2
    description: FMC BCH Parity Bits Register 2.
    byte_offset: 612
    access: Read
    fieldset: BCHPBR2
  - name: BCHPBR3
    description: FMC BCH Parity Bits Register 3.
    byte_offset: 616
    access: Read
    fieldset: BCHPBR3
  - name: BCHPBR4
    description: FMC BCH Parity Bits Register 4.
    byte_offset: 620
    access: Read
    fieldset: BCHPBR4
  - name: BCHDSR0
    description: This register contains some fields already available in other registers but that require to be saved when error correction is performed on several sectors at a time (for example a whole NAND Flash page). This allows a DMA channel to transfer the content of FMC_BCHDSR0..4 to a decoding status buffer..
    byte_offset: 636
    access: Read
    fieldset: BCHDSR0
  - name: BCHDSR1
    description: The maximum error correction capability of the BCH block embedded in the FMC is 8 errors.
    byte_offset: 640
    access: Read
    fieldset: BCHDSR1
  - name: BCHDSR2
    description: The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 3rd and 4th error bits in EBP3 and EPB4 fields, respectively.
    byte_offset: 644
    access: Read
    fieldset: BCHDSR2
  - name: BCHDSR3
    description: The maximum error correction capability of the BCH block embedded in the FMC is 8 errors.
    byte_offset: 648
    access: Read
    fieldset: BCHDSR3
  - name: BCHDSR4
    description: The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 7th and 8th error bits in EBP7 and EPB8 fields, respectively..
    byte_offset: 652
    access: Read
    fieldset: BCHDSR4
  - name: HWCFGR2
    description: FMC Hardware configuration register 2.
    byte_offset: 1004
    access: Read
    fieldset: HWCFGR2
  - name: HWCFGR1
    description: FMC Hardware configuration register 1.
    byte_offset: 1008
    access: Read
    fieldset: HWCFGR1
  - name: VERR
    description: FMC Version register.
    byte_offset: 1012
    access: Read
    fieldset: VERR
  - name: IPIDR
    description: FMC Identification register.
    byte_offset: 1016
    access: Read
    fieldset: IPIDR
  - name: SIDR
    description: FMC Size Identification register.
    byte_offset: 1020
    access: Read
    fieldset: SIDR
fieldset/BCHDSR0:
  description: This register contains some fields already available in other registers but that require to be saved when error correction is performed on several sectors at a time (for example a whole NAND Flash page). This allows a DMA channel to transfer the content of FMC_BCHDSR0..4 to a decoding status buffer..
  fields:
  - name: DUE
    description: DUE.
    bit_offset: 0
    bit_size: 1
  - name: DEF
    description: DEF.
    bit_offset: 1
    bit_size: 1
  - name: DEN
    description: DEN.
    bit_offset: 4
    bit_size: 4
fieldset/BCHDSR1:
  description: The maximum error correction capability of the BCH block embedded in the FMC is 8 errors.
  fields:
  - name: EBP1
    description: EBP1.
    bit_offset: 0
    bit_size: 13
  - name: EBP2
    description: EBP2.
    bit_offset: 16
    bit_size: 13
fieldset/BCHDSR2:
  description: The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 3rd and 4th error bits in EBP3 and EPB4 fields, respectively.
  fields:
  - name: EBP3
    description: EBP3.
    bit_offset: 0
    bit_size: 13
  - name: EBP4
    description: EBP4.
    bit_offset: 16
    bit_size: 13
fieldset/BCHDSR3:
  description: The maximum error correction capability of the BCH block embedded in the FMC is 8 errors.
  fields:
  - name: EBP5
    description: EBP5.
    bit_offset: 0
    bit_size: 13
  - name: EBP6
    description: EBP6.
    bit_offset: 16
    bit_size: 13
fieldset/BCHDSR4:
  description: The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 7th and 8th error bits in EBP7 and EPB8 fields, respectively..
  fields:
  - name: EBP7
    description: EBP7.
    bit_offset: 0
    bit_size: 13
  - name: EBP8
    description: EBP8.
    bit_offset: 16
    bit_size: 13
fieldset/BCHICR:
  description: FMC BCH Interrupt Clear Register.
  fields:
  - name: CDUEF
    description: CDUEF.
    bit_offset: 0
    bit_size: 1
  - name: CDERF
    description: CDERF.
    bit_offset: 1
    bit_size: 1
  - name: CDEFF
    description: CDEFF.
    bit_offset: 2
    bit_size: 1
  - name: CDSRF
    description: CDSRF.
    bit_offset: 3
    bit_size: 1
  - name: CEPBRF
    description: CEPBRF.
    bit_offset: 4
    bit_size: 1
fieldset/BCHIER:
  description: FMC BCH Interrupt enable register.
  fields:
  - name: DUEIE
    description: DUEIE.
    bit_offset: 0
    bit_size: 1
  - name: DERIE
    description: DERIE.
    bit_offset: 1
    bit_size: 1
  - name: DEFIE
    description: DEFIE.
    bit_offset: 2
    bit_size: 1
  - name: DSRIE
    description: DSRIE.
    bit_offset: 3
    bit_size: 1
  - name: EPBRIE
    description: EPBRIE.
    bit_offset: 4
    bit_size: 1
fieldset/BCHISR:
  description: This register holds the status of BCH encoder/decoder after processing each sector. When the sequencer is used, this register is automatically cleared.
  fields:
  - name: DUEF
    description: DUEF.
    bit_offset: 0
    bit_size: 1
  - name: DERF
    description: DERF.
    bit_offset: 1
    bit_size: 1
  - name: DEFF
    description: DEFF.
    bit_offset: 2
    bit_size: 1
  - name: DSRF
    description: DSRF.
    bit_offset: 3
    bit_size: 1
  - name: EPBRF
    description: EPBRF.
    bit_offset: 4
    bit_size: 1
fieldset/BCHPBR1:
  description: These registers contain the BCH parity bits (BCHPB). For the BCH 4-bit, only BCHPB[51:0] are significant and for the BCH 8-bit BCHPB[103:0] are significant.
  fields:
  - name: BCHPB
    description: BCHPB.
    bit_offset: 0
    bit_size: 32
fieldset/BCHPBR2:
  description: FMC BCH Parity Bits Register 2.
  fields:
  - name: BCHPB
    description: BCHPB.
    bit_offset: 0
    bit_size: 32
fieldset/BCHPBR3:
  description: FMC BCH Parity Bits Register 3.
  fields:
  - name: BCHPB
    description: BCHPB.
    bit_offset: 0
    bit_size: 32
fieldset/BCHPBR4:
  description: FMC BCH Parity Bits Register 4.
  fields:
  - name: BCHPB
    description: BCHPB.
    bit_offset: 0
    bit_size: 8
fieldset/BCR1:
  description: This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
  fields:
  - name: MBKEN
    description: MBKEN.
    bit_offset: 0
    bit_size: 1
  - name: MUXEN
    description: MUXEN.
    bit_offset: 1
    bit_size: 1
  - name: MTYP
    description: MTYP.
    bit_offset: 2
    bit_size: 2
  - name: MWID
    description: MWID.
    bit_offset: 4
    bit_size: 2
  - name: FACCEN
    description: FACCEN.
    bit_offset: 6
    bit_size: 1
  - name: BURSTEN
    description: BURSTEN.
    bit_offset: 8
    bit_size: 1
  - name: WAITPOL
    description: WAITPOL.
    bit_offset: 9
    bit_size: 1
  - name: WAITCFG
    description: WAITCFG.
    bit_offset: 11
    bit_size: 1
  - name: WREN
    description: WREN.
    bit_offset: 12
    bit_size: 1
  - name: WAITEN
    description: WAITEN.
    bit_offset: 13
    bit_size: 1
  - name: EXTMOD
    description: EXTMOD.
    bit_offset: 14
    bit_size: 1
  - name: ASYNCWAIT
    description: ASYNCWAIT.
    bit_offset: 15
    bit_size: 1
  - name: CPSIZE
    description: CPSIZE.
    bit_offset: 16
    bit_size: 3
  - name: CBURSTRW
    description: CBURSTRW.
    bit_offset: 19
    bit_size: 1
  - name: CCLKEN
    description: CCLKEN.
    bit_offset: 20
    bit_size: 1
  - name: NBLSET
    description: NBLSET.
    bit_offset: 22
    bit_size: 2
  - name: FMCEN
    description: FMCEN.
    bit_offset: 31
    bit_size: 1
fieldset/BCR2:
  description: This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
  fields:
  - name: MBKEN
    description: MBKEN.
    bit_offset: 0
    bit_size: 1
  - name: MUXEN
    description: MUXEN.
    bit_offset: 1
    bit_size: 1
  - name: MTYP
    description: MTYP.
    bit_offset: 2
    bit_size: 2
  - name: MWID
    description: MWID.
    bit_offset: 4
    bit_size: 2
  - name: FACCEN
    description: FACCEN.
    bit_offset: 6
    bit_size: 1
  - name: BURSTEN
    description: BURSTEN.
    bit_offset: 8
    bit_size: 1
  - name: WAITPOL
    description: WAITPOL.
    bit_offset: 9
    bit_size: 1
  - name: WAITCFG
    description: WAITCFG.
    bit_offset: 11
    bit_size: 1
  - name: WREN
    description: WREN.
    bit_offset: 12
    bit_size: 1
  - name: WAITEN
    description: WAITEN.
    bit_offset: 13
    bit_size: 1
  - name: EXTMOD
    description: EXTMOD.
    bit_offset: 14
    bit_size: 1
  - name: ASYNCWAIT
    description: ASYNCWAIT.
    bit_offset: 15
    bit_size: 1
  - name: CPSIZE
    description: CPSIZE.
    bit_offset: 16
    bit_size: 3
  - name: CBURSTRW
    description: CBURSTRW.
    bit_offset: 19
    bit_size: 1
  - name: CCLKEN
    description: CCLKEN.
    bit_offset: 20
    bit_size: 1
  - name: NBLSET
    description: NBLSET.
    bit_offset: 22
    bit_size: 2
  - name: FMCEN
    description: FMCEN.
    bit_offset: 31
    bit_size: 1
fieldset/BCR3:
  description: This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
  fields:
  - name: MBKEN
    description: MBKEN.
    bit_offset: 0
    bit_size: 1
  - name: MUXEN
    description: MUXEN.
    bit_offset: 1
    bit_size: 1
  - name: MTYP
    description: MTYP.
    bit_offset: 2
    bit_size: 2
  - name: MWID
    description: MWID.
    bit_offset: 4
    bit_size: 2
  - name: FACCEN
    description: FACCEN.
    bit_offset: 6
    bit_size: 1
  - name: BURSTEN
    description: BURSTEN.
    bit_offset: 8
    bit_size: 1
  - name: WAITPOL
    description: WAITPOL.
    bit_offset: 9
    bit_size: 1
  - name: WAITCFG
    description: WAITCFG.
    bit_offset: 11
    bit_size: 1
  - name: WREN
    description: WREN.
    bit_offset: 12
    bit_size: 1
  - name: WAITEN
    description: WAITEN.
    bit_offset: 13
    bit_size: 1
  - name: EXTMOD
    description: EXTMOD.
    bit_offset: 14
    bit_size: 1
  - name: ASYNCWAIT
    description: ASYNCWAIT.
    bit_offset: 15
    bit_size: 1
  - name: CPSIZE
    description: CPSIZE.
    bit_offset: 16
    bit_size: 3
  - name: CBURSTRW
    description: CBURSTRW.
    bit_offset: 19
    bit_size: 1
  - name: CCLKEN
    description: CCLKEN.
    bit_offset: 20
    bit_size: 1
  - name: NBLSET
    description: NBLSET.
    bit_offset: 22
    bit_size: 2
  - name: FMCEN
    description: FMCEN.
    bit_offset: 31
    bit_size: 1
fieldset/BCR4:
  description: This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.
  fields:
  - name: MBKEN
    description: MBKEN.
    bit_offset: 0
    bit_size: 1
  - name: MUXEN
    description: MUXEN.
    bit_offset: 1
    bit_size: 1
  - name: MTYP
    description: MTYP.
    bit_offset: 2
    bit_size: 2
  - name: MWID
    description: MWID.
    bit_offset: 4
    bit_size: 2
  - name: FACCEN
    description: FACCEN.
    bit_offset: 6
    bit_size: 1
  - name: BURSTEN
    description: BURSTEN.
    bit_offset: 8
    bit_size: 1
  - name: WAITPOL
    description: WAITPOL.
    bit_offset: 9
    bit_size: 1
  - name: WAITCFG
    description: WAITCFG.
    bit_offset: 11
    bit_size: 1
  - name: WREN
    description: WREN.
    bit_offset: 12
    bit_size: 1
  - name: WAITEN
    description: WAITEN.
    bit_offset: 13
    bit_size: 1
  - name: EXTMOD
    description: EXTMOD.
    bit_offset: 14
    bit_size: 1
  - name: ASYNCWAIT
    description: ASYNCWAIT.
    bit_offset: 15
    bit_size: 1
  - name: CPSIZE
    description: CPSIZE.
    bit_offset: 16
    bit_size: 3
  - name: CBURSTRW
    description: CBURSTRW.
    bit_offset: 19
    bit_size: 1
  - name: CCLKEN
    description: CCLKEN.
    bit_offset: 20
    bit_size: 1
  - name: NBLSET
    description: NBLSET.
    bit_offset: 22
    bit_size: 2
  - name: FMCEN
    description: FMCEN.
    bit_offset: 31
    bit_size: 1
fieldset/BTR1:
  description: 'This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).'
  fields:
  - name: ADDSET
    description: ADDSET.
    bit_offset: 0
    bit_size: 4
  - name: ADDHLD
    description: ADDHLD.
    bit_offset: 4
    bit_size: 4
  - name: DATAST
    description: DATAST.
    bit_offset: 8
    bit_size: 8
  - name: BUSTURN
    description: BUSTURN.
    bit_offset: 16
    bit_size: 4
  - name: CLKDIV
    description: CLKDIV.
    bit_offset: 20
    bit_size: 4
  - name: DATLAT
    description: DATLAT.
    bit_offset: 24
    bit_size: 4
  - name: ACCMOD
    description: ACCMOD.
    bit_offset: 28
    bit_size: 2
  - name: DATAHLD
    description: DATAHLD.
    bit_offset: 30
    bit_size: 2
fieldset/BTR2:
  description: 'This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).'
  fields:
  - name: ADDSET
    description: ADDSET.
    bit_offset: 0
    bit_size: 4
  - name: ADDHLD
    description: ADDHLD.
    bit_offset: 4
    bit_size: 4
  - name: DATAST
    description: DATAST.
    bit_offset: 8
    bit_size: 8
  - name: BUSTURN
    description: BUSTURN.
    bit_offset: 16
    bit_size: 4
  - name: CLKDIV
    description: CLKDIV.
    bit_offset: 20
    bit_size: 4
  - name: DATLAT
    description: DATLAT.
    bit_offset: 24
    bit_size: 4
  - name: ACCMOD
    description: ACCMOD.
    bit_offset: 28
    bit_size: 2
  - name: DATAHLD
    description: DATAHLD.
    bit_offset: 30
    bit_size: 2
fieldset/BTR3:
  description: 'This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).'
  fields:
  - name: ADDSET
    description: ADDSET.
    bit_offset: 0
    bit_size: 4
  - name: ADDHLD
    description: ADDHLD.
    bit_offset: 4
    bit_size: 4
  - name: DATAST
    description: DATAST.
    bit_offset: 8
    bit_size: 8
  - name: BUSTURN
    description: BUSTURN.
    bit_offset: 16
    bit_size: 4
  - name: CLKDIV
    description: CLKDIV.
    bit_offset: 20
    bit_size: 4
  - name: DATLAT
    description: DATLAT.
    bit_offset: 24
    bit_size: 4
  - name: ACCMOD
    description: ACCMOD.
    bit_offset: 28
    bit_size: 2
  - name: DATAHLD
    description: DATAHLD.
    bit_offset: 30
    bit_size: 2
fieldset/BTR4:
  description: 'This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).'
  fields:
  - name: ADDSET
    description: ADDSET.
    bit_offset: 0
    bit_size: 4
  - name: ADDHLD
    description: ADDHLD.
    bit_offset: 4
    bit_size: 4
  - name: DATAST
    description: DATAST.
    bit_offset: 8
    bit_size: 8
  - name: BUSTURN
    description: BUSTURN.
    bit_offset: 16
    bit_size: 4
  - name: CLKDIV
    description: CLKDIV.
    bit_offset: 20
    bit_size: 4
  - name: DATLAT
    description: DATLAT.
    bit_offset: 24
    bit_size: 4
  - name: ACCMOD
    description: ACCMOD.
    bit_offset: 28
    bit_size: 2
  - name: DATAHLD
    description: DATAHLD.
    bit_offset: 30
    bit_size: 2
fieldset/BWTR1:
  description: This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
  fields:
  - name: ADDSET
    description: ADDSET.
    bit_offset: 0
    bit_size: 4
  - name: ADDHLD
    description: ADDHLD.
    bit_offset: 4
    bit_size: 4
  - name: DATAST
    description: DATAST.
    bit_offset: 8
    bit_size: 8
  - name: BUSTURN
    description: BUSTURN.
    bit_offset: 16
    bit_size: 4
  - name: ACCMOD
    description: ACCMOD.
    bit_offset: 28
    bit_size: 2
  - name: DATAHLD
    description: DATAHLD.
    bit_offset: 30
    bit_size: 2
fieldset/BWTR2:
  description: This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
  fields:
  - name: ADDSET
    description: ADDSET.
    bit_offset: 0
    bit_size: 4
  - name: ADDHLD
    description: ADDHLD.
    bit_offset: 4
    bit_size: 4
  - name: DATAST
    description: DATAST.
    bit_offset: 8
    bit_size: 8
  - name: BUSTURN
    description: BUSTURN.
    bit_offset: 16
    bit_size: 4
  - name: ACCMOD
    description: ACCMOD.
    bit_offset: 28
    bit_size: 2
  - name: DATAHLD
    description: DATAHLD.
    bit_offset: 30
    bit_size: 2
fieldset/BWTR3:
  description: This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
  fields:
  - name: ADDSET
    description: ADDSET.
    bit_offset: 0
    bit_size: 4
  - name: ADDHLD
    description: ADDHLD.
    bit_offset: 4
    bit_size: 4
  - name: DATAST
    description: DATAST.
    bit_offset: 8
    bit_size: 8
  - name: BUSTURN
    description: BUSTURN.
    bit_offset: 16
    bit_size: 4
  - name: ACCMOD
    description: ACCMOD.
    bit_offset: 28
    bit_size: 2
  - name: DATAHLD
    description: DATAHLD.
    bit_offset: 30
    bit_size: 2
fieldset/BWTR4:
  description: This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
  fields:
  - name: ADDSET
    description: ADDSET.
    bit_offset: 0
    bit_size: 4
  - name: ADDHLD
    description: ADDHLD.
    bit_offset: 4
    bit_size: 4
  - name: DATAST
    description: DATAST.
    bit_offset: 8
    bit_size: 8
  - name: BUSTURN
    description: BUSTURN.
    bit_offset: 16
    bit_size: 4
  - name: ACCMOD
    description: ACCMOD.
    bit_offset: 28
    bit_size: 2
  - name: DATAHLD
    description: DATAHLD.
    bit_offset: 30
    bit_size: 2
fieldset/CSQAR1:
  description: This register is used to define the value of address cycles 1 to 4 to be issued by the command sequencer.
  fields:
  - name: ADDC1
    description: ADDC1.
    bit_offset: 0
    bit_size: 8
  - name: ADDC2
    description: ADDC2.
    bit_offset: 8
    bit_size: 8
  - name: ADDC3
    description: ADDC3.
    bit_offset: 16
    bit_size: 8
  - name: ADDC4
    description: ADDC4.
    bit_offset: 24
    bit_size: 8
fieldset/CSQAR2:
  description: This register is used to program the fifth address cycle and the address offset in spare area. It also selects the chip enable.
  fields:
  - name: ADDC5
    description: ADDC5.
    bit_offset: 0
    bit_size: 8
  - name: NANDCEN0
    description: NANDCEN0.
    bit_offset: 10
    bit_size: 1
  - name: NANDCEN1
    description: NANDCEN1.
    bit_offset: 11
    bit_size: 1
  - name: SAO
    description: SAO.
    bit_offset: 16
    bit_size: 16
fieldset/CSQCFGR1:
  description: FMC NAND Command Sequencer Configuration Register 1.
  fields:
  - name: CMD2EN
    description: CMD2EN.
    bit_offset: 1
    bit_size: 1
  - name: DMADEN
    description: DMADEN.
    bit_offset: 2
    bit_size: 1
  - name: ACYNBR
    description: ACYNBR.
    bit_offset: 4
    bit_size: 3
  - name: CMD1
    description: CMD1.
    bit_offset: 8
    bit_size: 8
  - name: CMD2
    description: CMD2.
    bit_offset: 16
    bit_size: 8
  - name: CMD1T
    description: CMD1T.
    bit_offset: 24
    bit_size: 1
  - name: CMD2T
    description: CMD2T.
    bit_offset: 25
    bit_size: 1
fieldset/CSQCFGR2:
  description: This register is used to configure the command sequencer to issue random read/ write commands to read/ write data by sector and automatically read/write data from NAND Flash memory at a programmable address offset. This is useful when performing a sector read/write operation followed by an ECC read/write operation in the NAND Flash spare area.The command sequencer generates the random commands untill all the sectors are read/written..
  fields:
  - name: SQSDTEN
    description: SQSDTEN.
    bit_offset: 0
    bit_size: 1
  - name: RCMD2EN
    description: RCMD2EN.
    bit_offset: 1
    bit_size: 1
  - name: DMASEN
    description: DMASEN.
    bit_offset: 2
    bit_size: 1
  - name: RCMD1
    description: RCMD1.
    bit_offset: 8
    bit_size: 8
  - name: RCMD2
    description: RCMD2.
    bit_offset: 16
    bit_size: 8
  - name: RCMD1T
    description: RCMD1T.
    bit_offset: 24
    bit_size: 1
  - name: RCMD2T
    description: RCMD2T.
    bit_offset: 25
    bit_size: 1
fieldset/CSQCFGR3:
  description: FMC NAND sequencer configuration register 3.
  fields:
  - name: SNBR
    description: SNBR.
    bit_offset: 8
    bit_size: 6
  - name: AC1T
    description: AC1T.
    bit_offset: 16
    bit_size: 1
  - name: AC2T
    description: AC2T.
    bit_offset: 17
    bit_size: 1
  - name: AC3T
    description: AC3T.
    bit_offset: 18
    bit_size: 1
  - name: AC4T
    description: AC4T.
    bit_offset: 19
    bit_size: 1
  - name: AC5T
    description: AC5T.
    bit_offset: 20
    bit_size: 1
  - name: SDT
    description: SDT.
    bit_offset: 21
    bit_size: 1
  - name: RAC1T
    description: RAC1T.
    bit_offset: 22
    bit_size: 1
  - name: RAC2T
    description: RAC2T.
    bit_offset: 23
    bit_size: 1
fieldset/CSQCR:
  description: FMC NAND Command Sequencer Control Register.
  fields:
  - name: CSQSTART
    description: CSQSTART.
    bit_offset: 0
    bit_size: 1
fieldset/CSQEMSR:
  description: This register holds a sector error mapping status when the whole transfer is complete.
  fields:
  - name: SEM
    description: SEM.
    bit_offset: 0
    bit_size: 16
fieldset/CSQICR:
  description: FMC NAND Command Sequencer Interrupt Clear Register.
  fields:
  - name: CTCF
    description: CTCF.
    bit_offset: 0
    bit_size: 1
  - name: CSCF
    description: CSCF.
    bit_offset: 1
    bit_size: 1
  - name: CSEF
    description: CSEF.
    bit_offset: 2
    bit_size: 1
  - name: CSUEF
    description: CSUEF.
    bit_offset: 3
    bit_size: 1
  - name: CCMDTCF
    description: CCMDTCF.
    bit_offset: 4
    bit_size: 1
fieldset/CSQIER:
  description: FMC NAND Command Sequencer Interrupt Enable Register.
  fields:
  - name: TCIE
    description: TCIE.
    bit_offset: 0
    bit_size: 1
  - name: SCIE
    description: SCIE.
    bit_offset: 1
    bit_size: 1
  - name: SEIE
    description: SEIE.
    bit_offset: 2
    bit_size: 1
  - name: SUEIE
    description: SUEIE.
    bit_offset: 3
    bit_size: 1
  - name: CMDTCIE
    description: CMDTCIE.
    bit_offset: 4
    bit_size: 1
fieldset/CSQISR:
  description: FMC NAND Command Sequencer Interrupt Status Register.
  fields:
  - name: TCF
    description: TCF.
    bit_offset: 0
    bit_size: 1
  - name: SCF
    description: SCF.
    bit_offset: 1
    bit_size: 1
  - name: SEF
    description: SEF.
    bit_offset: 2
    bit_size: 1
  - name: SUEF
    description: SUEF.
    bit_offset: 3
    bit_size: 1
  - name: CMDTCF
    description: CMDTCF.
    bit_offset: 4
    bit_size: 1
fieldset/HECCR:
  description: 'This register contain the current error correction code value computed by the FMC NAND controller Hamming module.When the CPU reads/writes data from/to a NAND Flash memory page at the correct address (refer to Section25.8.6: NAND ECC controller), the data read/written from/to the NAND Flash memory are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and to correct it otherwise. The FMC_HECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.'
  fields:
  - name: HECC
    description: HECC.
    bit_offset: 0
    bit_size: 32
fieldset/HPR:
  description: This register is used during read accesses in conjunction with the FMC sequencer. It contains the current error correction code value computed by the FMC NAND controller Hamming module. When the FMC sequencer reads data from a NAND Flash memory page at the correct address, the data read are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area and stored in the and the FMC_HPR, to determine whether a page is valid, and to correct it otherwise. The FMC_HPR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
  fields:
  - name: HPR
    description: HPR.
    bit_offset: 0
    bit_size: 32
fieldset/HWCFGR1:
  description: FMC Hardware configuration register 1.
  fields:
  - name: NAND_SEL
    description: NAND_SEL.
    bit_offset: 0
    bit_size: 1
  - name: NAND_ECC
    description: NAND_ECC.
    bit_offset: 4
    bit_size: 1
  - name: SDRAM_SEL
    description: SDRAM_SEL.
    bit_offset: 8
    bit_size: 1
  - name: ID_SIZE
    description: ID_SIZE.
    bit_offset: 12
    bit_size: 4
  - name: WA_LN2DPTH
    description: WA_LN2DPTH.
    bit_offset: 16
    bit_size: 4
  - name: WD_LN2DPTH
    description: WD_LN2DPTH.
    bit_offset: 20
    bit_size: 4
  - name: WR_LN2DPTH
    description: WR_LN2DPTH.
    bit_offset: 24
    bit_size: 4
  - name: RA_LN2DPTH
    description: RA_LN2DPTH.
    bit_offset: 28
    bit_size: 4
fieldset/HWCFGR2:
  description: FMC Hardware configuration register 2.
  fields:
  - name: RD_LN2DPTH
    description: RD_LN2DPTH.
    bit_offset: 0
    bit_size: 4
  - name: NOR_BASE
    description: NOR_BASE.
    bit_offset: 4
    bit_size: 4
  - name: SDRAM_RBASE
    description: SDRAM_RBASE.
    bit_offset: 8
    bit_size: 4
  - name: NAND_BASE
    description: NAND_BASE.
    bit_offset: 12
    bit_size: 4
  - name: SDRAM1_BASE
    description: SDRAM1_BASE.
    bit_offset: 16
    bit_size: 4
  - name: SDRAM2_BASE
    description: SDRAM2_BASE.
    bit_offset: 20
    bit_size: 4
fieldset/IPIDR:
  description: FMC Identification register.
  fields:
  - name: ID
    description: ID.
    bit_offset: 0
    bit_size: 32
fieldset/PATT:
  description: 'The FMC_PATT read/write register contains NAND Flash memory bank timing information. It is used for 8-bit accesses to the NAND Flash attribute memory space during the last address write access when the timing differs from previous accesses (for Ready/Busy management, refer to Section25.8.5: NAND Flash prewait function).'
  fields:
  - name: ATTSET
    description: ATTSET.
    bit_offset: 0
    bit_size: 8
  - name: ATTWAIT
    description: ATTWAIT.
    bit_offset: 8
    bit_size: 8
  - name: ATTHOLD
    description: ATTHOLD.
    bit_offset: 16
    bit_size: 8
  - name: ATTHIZ
    description: ATTHIZ.
    bit_offset: 24
    bit_size: 8
fieldset/PCR:
  description: NAND Flash Programmable control register.
  fields:
  - name: PWAITEN
    description: PWAITEN.
    bit_offset: 1
    bit_size: 1
  - name: PBKEN
    description: PBKEN.
    bit_offset: 2
    bit_size: 1
  - name: PWID
    description: PWID.
    bit_offset: 4
    bit_size: 2
  - name: ECCEN
    description: ECCEN.
    bit_offset: 6
    bit_size: 1
  - name: ECCALG
    description: ECCALG.
    bit_offset: 8
    bit_size: 1
  - name: TCLR
    description: TCLR.
    bit_offset: 9
    bit_size: 4
  - name: TAR
    description: TAR.
    bit_offset: 13
    bit_size: 4
  - name: ECCSS
    description: ECCSS.
    bit_offset: 17
    bit_size: 3
  - name: TCEH
    description: TCEH.
    bit_offset: 20
    bit_size: 4
  - name: BCHECC
    description: BCHECC.
    bit_offset: 24
    bit_size: 1
  - name: WEN
    description: WEN.
    bit_offset: 25
    bit_size: 1
fieldset/PCSCNTR:
  description: This register contains the PSRAM chip select counter value for synchronous mode. The chip select counter is common to all banks and can be enabled separately on each bank. During PSRAM read or write accesses, this value is loaded into a timer which is decremented using the fmc_ker_ck while the NE signal is held low. When the timer reaches 0, the PSRAM controller splits the current access, toggles NE to allow PSRAM device refresh and restarts a new access. The programmed counter value guarantees a maximum NE pulse width (tCEM) as specified for PSRAM devices. The counter is reloaded and starts decrementing each time a new access is started by a transition of NE from high to low. h.
  fields:
  - name: CSCOUNT
    description: CSCOUNT.
    bit_offset: 0
    bit_size: 16
  - name: CNTB1EN
    description: CNTB1EN.
    bit_offset: 16
    bit_size: 1
  - name: CNTB2EN
    description: CNTB2EN.
    bit_offset: 17
    bit_size: 1
  - name: CNTB3EN
    description: CNTB3EN.
    bit_offset: 18
    bit_size: 1
  - name: CNTB4EN
    description: CNTB4EN.
    bit_offset: 19
    bit_size: 1
fieldset/PMEM:
  description: The FMC_PMEM read/write register contains NAND Flash memory bank timing information. This information is used to access the NAND Flash common memory space for command, address write accesses or data read/write accesses.
  fields:
  - name: MEMSET
    description: MEMSET.
    bit_offset: 0
    bit_size: 8
  - name: MEMWAIT
    description: MEMWAIT.
    bit_offset: 8
    bit_size: 8
  - name: MEMHOLD
    description: MEMHOLD.
    bit_offset: 16
    bit_size: 8
  - name: MEMHIZ
    description: MEMHIZ.
    bit_offset: 24
    bit_size: 8
fieldset/SIDR:
  description: FMC Size Identification register.
  fields:
  - name: SID
    description: SID.
    bit_offset: 0
    bit_size: 32
fieldset/SR:
  description: This register contains information about the AXI interface isolation status and the NAND write requests status. The FMC has to be disabled before modifying some registers. As requests might be pending, it is necessary to wait till the AXI interface is stable and the core of the block is totally isolated from its AXI interface before reconfiguring the registers. The PEF and PNWEF bits indicate the status of the pipe. If Hamming algorithm is used, the ECC is calculated while data are written to the memory. To read the correct ECC, the software must consequently wait untill no write request to the NAND controller are pending, by polling PEF and NWRF bits.
  fields:
  - name: ISOST
    description: ISOST.
    bit_offset: 0
    bit_size: 2
  - name: PEF
    description: PEF.
    bit_offset: 4
    bit_size: 1
  - name: NWRF
    description: NWRF.
    bit_offset: 6
    bit_size: 1
fieldset/VERR:
  description: FMC Version register.
  fields:
  - name: MINREV
    description: MINREV.
    bit_offset: 0
    bit_size: 4
  - name: MAJREV
    description: MAJREV.
    bit_offset: 4
    bit_size: 4