block/DDRCTRL: description: DDRCTRL. items: - name: MSTR description: DDRCTRL master register 0. byte_offset: 0 fieldset: MSTR - name: STAT description: DDRCTRL operating mode status register. byte_offset: 4 access: Read fieldset: STAT - name: MRCTRL0 description: 'Mode Register Read/Write Control Register 0. Do not enable more than one of the following fields simultaneously: sw_init_int pda_en mpr_en.' byte_offset: 16 fieldset: MRCTRL0 - name: MRCTRL1 description: DDRCTRL mode register read/write control register 1. byte_offset: 20 fieldset: MRCTRL1 - name: MRSTAT description: DDRCTRL mode register read/write status register. byte_offset: 24 access: Read fieldset: MRSTAT - name: DERATEEN description: DDRCTRL temperature derate enable register. byte_offset: 32 fieldset: DERATEEN - name: DERATEINT description: DDRCTRL temperature derate interval register. byte_offset: 36 fieldset: DERATEINT - name: PWRCTL description: DDRCTRL low power control register. byte_offset: 48 fieldset: PWRCTL - name: PWRTMG description: DDRCTRL low power timing register. byte_offset: 52 fieldset: PWRTMG - name: HWLPCTL description: DDRCTRL hardware low power control register. byte_offset: 56 fieldset: HWLPCTL - name: RFSHCTL0 description: DDRCTRL refresh control register 0. byte_offset: 80 fieldset: RFSHCTL0 - name: RFSHCTL3 description: DDRCTRL refresh control register 3. byte_offset: 96 fieldset: RFSHCTL3 - name: RFSHTMG description: DDRCTRL refresh timing register. byte_offset: 100 fieldset: RFSHTMG - name: CRCPARCTL0 description: DDRCTRL CRC parity control register 0. byte_offset: 192 fieldset: CRCPARCTL0 - name: CRCPARSTAT description: DDRCTRL CRC parity status register. byte_offset: 204 access: Read fieldset: CRCPARSTAT - name: INIT0 description: DDRCTRL SDRAM initialization register 0. byte_offset: 208 fieldset: INIT0 - name: INIT1 description: DDRCTRL SDRAM initialization register 1. byte_offset: 212 fieldset: INIT1 - name: INIT2 description: DDRCTRL SDRAM initialization register 2. byte_offset: 216 fieldset: INIT2 - name: INIT3 description: DDRCTRL SDRAM initialization register 3. byte_offset: 220 fieldset: INIT3 - name: INIT4 description: DDRCTRL SDRAM initialization register 4. byte_offset: 224 fieldset: INIT4 - name: INIT5 description: DDRCTRL SDRAM initialization register 5. byte_offset: 228 fieldset: INIT5 - name: DIMMCTL description: DDRCTRL DIMM control register. byte_offset: 240 fieldset: DIMMCTL - name: DRAMTMG0 description: DDRCTRL SDRAM timing register 0. byte_offset: 256 fieldset: DRAMTMG0 - name: DRAMTMG1 description: DDRCTRL SDRAM timing register 1. byte_offset: 260 fieldset: DRAMTMG1 - name: DRAMTMG2 description: DDRCTRL SDRAM timing register 2. byte_offset: 264 fieldset: DRAMTMG2 - name: DRAMTMG3 description: DDRCTRL SDRAM timing register 3. byte_offset: 268 fieldset: DRAMTMG3 - name: DRAMTMG4 description: DDRCTRL SDRAM timing register 4. byte_offset: 272 fieldset: DRAMTMG4 - name: DRAMTMG5 description: DDRCTRL SDRAM timing register 5. byte_offset: 276 fieldset: DRAMTMG5 - name: DRAMTMG6 description: DDRCTRL SDRAM timing register 6. byte_offset: 280 fieldset: DRAMTMG6 - name: DRAMTMG7 description: DDRCTRL SDRAM timing register 7. byte_offset: 284 fieldset: DRAMTMG7 - name: DRAMTMG8 description: DDRCTRL SDRAM timing register 8. byte_offset: 288 fieldset: DRAMTMG8 - name: DRAMTMG14 description: DDRCTRL SDRAM timing register 14. byte_offset: 312 fieldset: DRAMTMG14 - name: DRAMTMG15 description: DDRCTRL SDRAM timing register 15. byte_offset: 316 fieldset: DRAMTMG15 - name: ZQCTL0 description: DDRCTRL ZQ control register 0. byte_offset: 384 fieldset: ZQCTL0 - name: ZQCTL1 description: DDRCTRL ZQ control register 1. byte_offset: 388 fieldset: ZQCTL1 - name: ZQCTL2 description: DDRCTRL ZQ control register 2. byte_offset: 392 fieldset: ZQCTL2 - name: ZQSTAT description: DDRCTRL ZQ status register. byte_offset: 396 access: Read fieldset: ZQSTAT - name: DFITMG0 description: DDRCTRL DFI timing register 0. byte_offset: 400 fieldset: DFITMG0 - name: DFITMG1 description: DDRCTRL DFI timing register 1. byte_offset: 404 fieldset: DFITMG1 - name: DFILPCFG0 description: DDRCTRL low power configuration register 0. byte_offset: 408 fieldset: DFILPCFG0 - name: DFIUPD0 description: DDRCTRL DFI update register 0. byte_offset: 416 fieldset: DFIUPD0 - name: DFIUPD1 description: DDRCTRL DFI update register 1. byte_offset: 420 fieldset: DFIUPD1 - name: DFIUPD2 description: DDRCTRL DFI update register 2. byte_offset: 424 fieldset: DFIUPD2 - name: DFIMISC description: DDRCTRL DFI miscellaneous control register. byte_offset: 432 fieldset: DFIMISC - name: DFISTAT description: DDRCTRL DFI status register. byte_offset: 444 access: Read fieldset: DFISTAT - name: DFIPHYMSTR description: DDRCTRL DFI PHY master register. byte_offset: 452 fieldset: DFIPHYMSTR - name: ADDRMAP1 description: DDRCTRL address map register 1. byte_offset: 516 fieldset: ADDRMAP1 - name: ADDRMAP2 description: DDRCTRL address map register 2. byte_offset: 520 fieldset: ADDRMAP2 - name: ADDRMAP3 description: DDRCTRL address map register 3. byte_offset: 524 fieldset: ADDRMAP3 - name: ADDRMAP4 description: DDRCTRL address map register 4. byte_offset: 528 fieldset: ADDRMAP4 - name: ADDRMAP5 description: DDRCTRL address map register 5. byte_offset: 532 fieldset: ADDRMAP5 - name: ADDRMAP6 description: DDRCTRL address register 6. byte_offset: 536 fieldset: ADDRMAP6 - name: ADDRMAP9 description: DDRCTRL address map register 9. byte_offset: 548 fieldset: ADDRMAP9 - name: ADDRMAP10 description: DDRCTRL address map register 10. byte_offset: 552 fieldset: ADDRMAP10 - name: ADDRMAP11 description: DDRCTRL address map register 11. byte_offset: 556 fieldset: ADDRMAP11 - name: ODTCFG description: DDRCTRL ODT configuration register. byte_offset: 576 fieldset: ODTCFG - name: ODTMAP description: DDRCTRL ODT/Rank map register. byte_offset: 580 fieldset: ODTMAP - name: SCHED description: DDRCTRL scheduler control register. byte_offset: 592 fieldset: SCHED - name: SCHED1 description: DDRCTRL scheduler control register 1. byte_offset: 596 fieldset: SCHED1 - name: PERFHPR1 description: DDRCTRL high priority read CAM register 1. byte_offset: 604 fieldset: PERFHPR1 - name: PERFLPR1 description: DDRCTRL low priority read CAM register 1. byte_offset: 612 fieldset: PERFLPR1 - name: PERFWR1 description: DDRCTRL write CAM register 1. byte_offset: 620 fieldset: PERFWR1 - name: DBG0 description: DDRCTRL debug register 0. byte_offset: 768 fieldset: DBG0 - name: DBG1 description: DDRCTRL debug register 1. byte_offset: 772 fieldset: DBG1 - name: DBGCAM description: DDRCTRL CAM debug register. byte_offset: 776 access: Read fieldset: DBGCAM - name: DBGCMD description: DDRCTRL command debug register. byte_offset: 780 fieldset: DBGCMD - name: DBGSTAT description: DDRCTRL status debug register. byte_offset: 784 access: Read fieldset: DBGSTAT - name: SWCTL description: DDRCTRL software register programming control enable. byte_offset: 800 fieldset: SWCTL - name: SWSTAT description: DDRCTRL software register programming control status. byte_offset: 804 access: Read fieldset: SWSTAT - name: POISONCFG description: AXI Poison configuration register common for all AXI ports. byte_offset: 876 fieldset: POISONCFG - name: POISONSTAT description: DDRCTRL AXI Poison status register. byte_offset: 880 access: Read fieldset: POISONSTAT - name: PSTAT description: DDRCTRL port status register. byte_offset: 1020 access: Read fieldset: PSTAT - name: PCCFG description: DDRCTRL port common configuration register. byte_offset: 1024 fieldset: PCCFG - name: PCFGR_0 description: DDRCTRL port 0 configuration read register. byte_offset: 1028 fieldset: PCFGR_0 - name: PCFGW_0 description: DDRCTRL port 0 configuration write register. byte_offset: 1032 fieldset: PCFGW_0 - name: PCTRL_0 description: DDRCTRL port 0 control register. byte_offset: 1168 fieldset: PCTRL_0 - name: PCFGQOS0_0 description: DDRCTRL port 0 read Q0S configuration register 0. byte_offset: 1172 fieldset: PCFGQOS0_0 - name: PCFGQOS1_0 description: DDRCTRL port 0 read Q0S configuration register 1. byte_offset: 1176 fieldset: PCFGQOS1_0 - name: PCFGWQOS0_0 description: DDRCTRL port 0 write Q0S configuration register 0. byte_offset: 1180 fieldset: PCFGWQOS0_0 - name: PCFGWQOS1_0 description: DDRCTRL port 0 write Q0S configuration register 1. byte_offset: 1184 fieldset: PCFGWQOS1_0 - name: PCFGR_1 description: DDRCTRL port 1 configuration read register. byte_offset: 1204 fieldset: PCFGR_1 - name: PCFGW_1 description: DDRCTRL port 1 configuration write register. byte_offset: 1208 fieldset: PCFGW_1 - name: PCTRL_1 description: DDRCTRL port 1 control register. byte_offset: 1344 fieldset: PCTRL_1 - name: PCFGQOS0_1 description: DDRCTRL port 1 read Q0S configuration register 0. byte_offset: 1348 fieldset: PCFGQOS0_1 - name: PCFGQOS1_1 description: DDRCTRL port 1 read Q0S configuration register 1. byte_offset: 1352 fieldset: PCFGQOS1_1 - name: PCFGWQOS0_1 description: DDRCTRL port 1 write Q0S configuration register 0. byte_offset: 1356 fieldset: PCFGWQOS0_1 - name: PCFGWQOS1_1 description: DDRCTRL port 1 write Q0S configuration register 1. byte_offset: 1360 fieldset: PCFGWQOS1_1 fieldset/ADDRMAP1: description: DDRCTRL address map register 1. fields: - name: ADDRMAP_BANK_B0 description: ADDRMAP_BANK_B0. bit_offset: 0 bit_size: 6 - name: ADDRMAP_BANK_B1 description: ADDRMAP_BANK_B1. bit_offset: 8 bit_size: 6 - name: ADDRMAP_BANK_B2 description: ADDRMAP_BANK_B2. bit_offset: 16 bit_size: 6 fieldset/ADDRMAP10: description: DDRCTRL address map register 10. fields: - name: ADDRMAP_ROW_B6 description: ADDRMAP_ROW_B6. bit_offset: 0 bit_size: 4 - name: ADDRMAP_ROW_B7 description: ADDRMAP_ROW_B7. bit_offset: 8 bit_size: 4 - name: ADDRMAP_ROW_B8 description: ADDRMAP_ROW_B8. bit_offset: 16 bit_size: 4 - name: ADDRMAP_ROW_B9 description: ADDRMAP_ROW_B9. bit_offset: 24 bit_size: 4 fieldset/ADDRMAP11: description: DDRCTRL address map register 11. fields: - name: ADDRMAP_ROW_B10 description: ADDRMAP_ROW_B10. bit_offset: 0 bit_size: 4 fieldset/ADDRMAP2: description: DDRCTRL address map register 2. fields: - name: ADDRMAP_COL_B2 description: ADDRMAP_COL_B2. bit_offset: 0 bit_size: 4 - name: ADDRMAP_COL_B3 description: ADDRMAP_COL_B3. bit_offset: 8 bit_size: 4 - name: ADDRMAP_COL_B4 description: ADDRMAP_COL_B4. bit_offset: 16 bit_size: 4 - name: ADDRMAP_COL_B5 description: ADDRMAP_COL_B5. bit_offset: 24 bit_size: 4 fieldset/ADDRMAP3: description: DDRCTRL address map register 3. fields: - name: ADDRMAP_COL_B6 description: ADDRMAP_COL_B6. bit_offset: 0 bit_size: 4 - name: ADDRMAP_COL_B7 description: ADDRMAP_COL_B7. bit_offset: 8 bit_size: 5 - name: ADDRMAP_COL_B8 description: ADDRMAP_COL_B8. bit_offset: 16 bit_size: 5 - name: ADDRMAP_COL_B9 description: ADDRMAP_COL_B9. bit_offset: 24 bit_size: 5 fieldset/ADDRMAP4: description: DDRCTRL address map register 4. fields: - name: ADDRMAP_COL_B10 description: ADDRMAP_COL_B10. bit_offset: 0 bit_size: 5 - name: ADDRMAP_COL_B11 description: ADDRMAP_COL_B11. bit_offset: 8 bit_size: 5 fieldset/ADDRMAP5: description: DDRCTRL address map register 5. fields: - name: ADDRMAP_ROW_B0 description: ADDRMAP_ROW_B0. bit_offset: 0 bit_size: 4 - name: ADDRMAP_ROW_B1 description: ADDRMAP_ROW_B1. bit_offset: 8 bit_size: 4 - name: ADDRMAP_ROW_B2_10 description: ADDRMAP_ROW_B2_10. bit_offset: 16 bit_size: 4 - name: ADDRMAP_ROW_B11 description: ADDRMAP_ROW_B11. bit_offset: 24 bit_size: 4 fieldset/ADDRMAP6: description: DDRCTRL address register 6. fields: - name: ADDRMAP_ROW_B12 description: ADDRMAP_ROW_B12. bit_offset: 0 bit_size: 4 - name: ADDRMAP_ROW_B13 description: ADDRMAP_ROW_B13. bit_offset: 8 bit_size: 4 - name: ADDRMAP_ROW_B14 description: ADDRMAP_ROW_B14. bit_offset: 16 bit_size: 4 - name: ADDRMAP_ROW_B15 description: ADDRMAP_ROW_B15. bit_offset: 24 bit_size: 4 - name: LPDDR3_6GB_12GB description: LPDDR3_6GB_12GB. bit_offset: 31 bit_size: 1 fieldset/ADDRMAP9: description: DDRCTRL address map register 9. fields: - name: ADDRMAP_ROW_B2 description: ADDRMAP_ROW_B2. bit_offset: 0 bit_size: 4 - name: ADDRMAP_ROW_B3 description: ADDRMAP_ROW_B3. bit_offset: 8 bit_size: 4 - name: ADDRMAP_ROW_B4 description: ADDRMAP_ROW_B4. bit_offset: 16 bit_size: 4 - name: ADDRMAP_ROW_B5 description: ADDRMAP_ROW_B5. bit_offset: 24 bit_size: 4 fieldset/CRCPARCTL0: description: DDRCTRL CRC parity control register 0. fields: - name: DFI_ALERT_ERR_INT_EN description: DFI_ALERT_ERR_INT_EN. bit_offset: 0 bit_size: 1 - name: DFI_ALERT_ERR_INT_CLR description: DFI_ALERT_ERR_INT_CLR. bit_offset: 1 bit_size: 1 - name: DFI_ALERT_ERR_CNT_CLR description: DFI_ALERT_ERR_CNT_CLR. bit_offset: 2 bit_size: 1 fieldset/CRCPARSTAT: description: DDRCTRL CRC parity status register. fields: - name: DFI_ALERT_ERR_CNT description: DFI_ALERT_ERR_CNT. bit_offset: 0 bit_size: 16 - name: DFI_ALERT_ERR_INT description: DFI_ALERT_ERR_INT. bit_offset: 16 bit_size: 1 fieldset/DBG0: description: DDRCTRL debug register 0. fields: - name: DIS_WC description: DIS_WC. bit_offset: 0 bit_size: 1 - name: DIS_COLLISION_PAGE_OPT description: DIS_COLLISION_PAGE_OPT. bit_offset: 4 bit_size: 1 fieldset/DBG1: description: DDRCTRL debug register 1. fields: - name: DIS_DQ description: DIS_DQ. bit_offset: 0 bit_size: 1 - name: DIS_HIF description: DIS_HIF. bit_offset: 1 bit_size: 1 fieldset/DBGCAM: description: DDRCTRL CAM debug register. fields: - name: DBG_HPR_Q_DEPTH description: DBG_HPR_Q_DEPTH. bit_offset: 0 bit_size: 5 - name: DBG_LPR_Q_DEPTH description: DBG_LPR_Q_DEPTH. bit_offset: 8 bit_size: 5 - name: DBG_W_Q_DEPTH description: DBG_W_Q_DEPTH. bit_offset: 16 bit_size: 5 - name: DBG_STALL description: DBG_STALL. bit_offset: 24 bit_size: 1 - name: DBG_RD_Q_EMPTY description: DBG_RD_Q_EMPTY. bit_offset: 25 bit_size: 1 - name: DBG_WR_Q_EMPTY description: DBG_WR_Q_EMPTY. bit_offset: 26 bit_size: 1 - name: RD_DATA_PIPELINE_EMPTY description: RD_DATA_PIPELINE_EMPTY. bit_offset: 28 bit_size: 1 - name: WR_DATA_PIPELINE_EMPTY description: WR_DATA_PIPELINE_EMPTY. bit_offset: 29 bit_size: 1 fieldset/DBGCMD: description: DDRCTRL command debug register. fields: - name: RANK0_REFRESH description: RANK0_REFRESH. bit_offset: 0 bit_size: 1 - name: ZQ_CALIB_SHORT description: ZQ_CALIB_SHORT. bit_offset: 4 bit_size: 1 - name: CTRLUPD description: CTRLUPD. bit_offset: 5 bit_size: 1 fieldset/DBGSTAT: description: DDRCTRL status debug register. fields: - name: RANK0_REFRESH_BUSY description: RANK0_REFRESH_BUSY. bit_offset: 0 bit_size: 1 - name: ZQ_CALIB_SHORT_BUSY description: ZQ_CALIB_SHORT_BUSY. bit_offset: 4 bit_size: 1 - name: CTRLUPD_BUSY description: CTRLUPD_BUSY. bit_offset: 5 bit_size: 1 fieldset/DERATEEN: description: DDRCTRL temperature derate enable register. fields: - name: DERATE_ENABLE description: DERATE_ENABLE. bit_offset: 0 bit_size: 1 - name: DERATE_VALUE description: DERATE_VALUE. bit_offset: 1 bit_size: 2 - name: DERATE_BYTE description: DERATE_BYTE. bit_offset: 4 bit_size: 4 fieldset/DERATEINT: description: DDRCTRL temperature derate interval register. fields: - name: MR4_READ_INTERVAL description: MR4_READ_INTERVAL. bit_offset: 0 bit_size: 32 fieldset/DFILPCFG0: description: DDRCTRL low power configuration register 0. fields: - name: DFI_LP_EN_PD description: DFI_LP_EN_PD. bit_offset: 0 bit_size: 1 - name: DFI_LP_WAKEUP_PD description: DFI_LP_WAKEUP_PD. bit_offset: 4 bit_size: 4 - name: DFI_LP_EN_SR description: DFI_LP_EN_SR. bit_offset: 8 bit_size: 1 - name: DFI_LP_WAKEUP_SR description: DFI_LP_WAKEUP_SR. bit_offset: 12 bit_size: 4 - name: DFI_LP_EN_DPD description: DFI_LP_EN_DPD. bit_offset: 16 bit_size: 1 - name: DFI_LP_WAKEUP_DPD description: DFI_LP_WAKEUP_DPD. bit_offset: 20 bit_size: 4 - name: DFI_TLP_RESP description: DFI_TLP_RESP. bit_offset: 24 bit_size: 5 fieldset/DFIMISC: description: DDRCTRL DFI miscellaneous control register. fields: - name: DFI_INIT_COMPLETE_EN description: DFI_INIT_COMPLETE_EN. bit_offset: 0 bit_size: 1 - name: CTL_IDLE_EN description: CTL_IDLE_EN. bit_offset: 4 bit_size: 1 - name: DFI_INIT_START description: DFI_INIT_START. bit_offset: 5 bit_size: 1 - name: DFI_FREQUENCY description: DFI_FREQUENCY. bit_offset: 8 bit_size: 5 fieldset/DFIPHYMSTR: description: DDRCTRL DFI PHY master register. fields: - name: DFI_PHYMSTR_EN description: DFI_PHYMSTR_EN. bit_offset: 0 bit_size: 1 fieldset/DFISTAT: description: DDRCTRL DFI status register. fields: - name: DFI_INIT_COMPLETE description: DFI_INIT_COMPLETE. bit_offset: 0 bit_size: 1 - name: DFI_LP_ACK description: DFI_LP_ACK. bit_offset: 1 bit_size: 1 fieldset/DFITMG0: description: DDRCTRL DFI timing register 0. fields: - name: DFI_TPHY_WRLAT description: DFI_TPHY_WRLAT. bit_offset: 0 bit_size: 6 - name: DFI_TPHY_WRDATA description: DFI_TPHY_WRDATA. bit_offset: 8 bit_size: 6 - name: DFI_T_RDDATA_EN description: DFI_T_RDDATA_EN. bit_offset: 16 bit_size: 7 - name: DFI_T_CTRL_DELAY description: DFI_T_CTRL_DELAY. bit_offset: 24 bit_size: 5 fieldset/DFITMG1: description: DDRCTRL DFI timing register 1. fields: - name: DFI_T_DRAM_CLK_ENABLE description: DFI_T_DRAM_CLK_ENABLE. bit_offset: 0 bit_size: 5 - name: DFI_T_DRAM_CLK_DISABLE description: DFI_T_DRAM_CLK_DISABLE. bit_offset: 8 bit_size: 5 - name: DFI_T_WRDATA_DELAY description: DFI_T_WRDATA_DELAY. bit_offset: 16 bit_size: 5 fieldset/DFIUPD0: description: DDRCTRL DFI update register 0. fields: - name: DFI_T_CTRLUP_MIN description: DFI_T_CTRLUP_MIN. bit_offset: 0 bit_size: 10 - name: DFI_T_CTRLUP_MAX description: DFI_T_CTRLUP_MAX. bit_offset: 16 bit_size: 10 - name: CTRLUPD_PRE_SRX description: CTRLUPD_PRE_SRX. bit_offset: 29 bit_size: 1 - name: DIS_AUTO_CTRLUPD_SRX description: DIS_AUTO_CTRLUPD_SRX. bit_offset: 30 bit_size: 1 - name: DIS_AUTO_CTRLUPD description: DIS_AUTO_CTRLUPD. bit_offset: 31 bit_size: 1 fieldset/DFIUPD1: description: DDRCTRL DFI update register 1. fields: - name: DFI_T_CTRLUPD_INTERVAL_MAX_X1024 description: DFI_T_CTRLUPD_INTERVAL_MAX_X1024. bit_offset: 0 bit_size: 8 - name: DFI_T_CTRLUPD_INTERVAL_MIN_X1024 description: DFI_T_CTRLUPD_INTERVAL_MIN_X1024. bit_offset: 16 bit_size: 8 fieldset/DFIUPD2: description: DDRCTRL DFI update register 2. fields: - name: DFI_PHYUPD_EN description: DFI_PHYUPD_EN. bit_offset: 31 bit_size: 1 fieldset/DIMMCTL: description: DDRCTRL DIMM control register. fields: - name: DIMM_STAGGER_CS_EN description: DIMM_STAGGER_CS_EN. bit_offset: 0 bit_size: 1 - name: DIMM_ADDR_MIRR_EN description: DIMM_ADDR_MIRR_EN. bit_offset: 1 bit_size: 1 fieldset/DRAMTMG0: description: DDRCTRL SDRAM timing register 0. fields: - name: T_RAS_MIN description: T_RAS_MIN. bit_offset: 0 bit_size: 6 - name: T_RAS_MAX description: T_RAS_MAX. bit_offset: 8 bit_size: 7 - name: T_FAW description: T_FAW. bit_offset: 16 bit_size: 6 - name: WR2PRE description: WR2PRE. bit_offset: 24 bit_size: 7 fieldset/DRAMTMG1: description: DDRCTRL SDRAM timing register 1. fields: - name: T_RC description: T_RC. bit_offset: 0 bit_size: 7 - name: RD2PRE description: RD2PRE. bit_offset: 8 bit_size: 6 - name: T_XP description: T_XP. bit_offset: 16 bit_size: 5 fieldset/DRAMTMG14: description: DDRCTRL SDRAM timing register 14. fields: - name: T_XSR description: T_XSR. bit_offset: 0 bit_size: 12 fieldset/DRAMTMG15: description: DDRCTRL SDRAM timing register 15. fields: - name: T_STAB_X32 description: T_STAB_X32. bit_offset: 0 bit_size: 8 - name: EN_DFI_LP_T_STAB description: EN_DFI_LP_T_STAB. bit_offset: 31 bit_size: 1 fieldset/DRAMTMG2: description: DDRCTRL SDRAM timing register 2. fields: - name: WR2RD description: WR2RD. bit_offset: 0 bit_size: 6 - name: RD2WR description: RD2WR. bit_offset: 8 bit_size: 6 - name: READ_LATENCY description: READ_LATENCY. bit_offset: 16 bit_size: 6 - name: WRITE_LATENCY description: WRITE_LATENCY. bit_offset: 24 bit_size: 6 fieldset/DRAMTMG3: description: DDRCTRL SDRAM timing register 3. fields: - name: T_MOD description: T_MOD. bit_offset: 0 bit_size: 10 - name: T_MRD description: T_MRD. bit_offset: 12 bit_size: 6 - name: T_MRW description: T_MRW. bit_offset: 20 bit_size: 10 fieldset/DRAMTMG4: description: DDRCTRL SDRAM timing register 4. fields: - name: T_RP description: T_RP. bit_offset: 0 bit_size: 5 - name: T_RRD description: T_RRD. bit_offset: 8 bit_size: 4 - name: T_CCD description: T_CCD. bit_offset: 16 bit_size: 4 - name: T_RCD description: T_RCD. bit_offset: 24 bit_size: 5 fieldset/DRAMTMG5: description: DDRCTRL SDRAM timing register 5. fields: - name: T_CKE description: T_CKE. bit_offset: 0 bit_size: 5 - name: T_CKESR description: T_CKESR. bit_offset: 8 bit_size: 6 - name: T_CKSRE description: T_CKSRE. bit_offset: 16 bit_size: 4 - name: T_CKSRX description: T_CKSRX. bit_offset: 24 bit_size: 4 fieldset/DRAMTMG6: description: DDRCTRL SDRAM timing register 6. fields: - name: T_CKCSX description: T_CKCSX. bit_offset: 0 bit_size: 4 - name: T_CKDPDX description: T_CKDPDX. bit_offset: 16 bit_size: 4 - name: T_CKDPDE description: T_CKDPDE. bit_offset: 24 bit_size: 4 fieldset/DRAMTMG7: description: DDRCTRL SDRAM timing register 7. fields: - name: T_CKPDX description: T_CKPDX. bit_offset: 0 bit_size: 4 - name: T_CKPDE description: T_CKPDE. bit_offset: 8 bit_size: 4 fieldset/DRAMTMG8: description: DDRCTRL SDRAM timing register 8. fields: - name: T_XS_X32 description: T_XS_X32. bit_offset: 0 bit_size: 7 - name: T_XS_DLL_X32 description: T_XS_DLL_X32. bit_offset: 8 bit_size: 7 fieldset/HWLPCTL: description: DDRCTRL hardware low power control register. fields: - name: HW_LP_EN description: HW_LP_EN. bit_offset: 0 bit_size: 1 - name: HW_LP_EXIT_IDLE_EN description: HW_LP_EXIT_IDLE_EN. bit_offset: 1 bit_size: 1 - name: HW_LP_IDLE_X32 description: HW_LP_IDLE_X32. bit_offset: 16 bit_size: 12 fieldset/INIT0: description: DDRCTRL SDRAM initialization register 0. fields: - name: PRE_CKE_X1024 description: PRE_CKE_X1024. bit_offset: 0 bit_size: 12 - name: POST_CKE_X1024 description: POST_CKE_X1024. bit_offset: 16 bit_size: 10 - name: SKIP_DRAM_INIT description: SKIP_DRAM_INIT. bit_offset: 30 bit_size: 2 fieldset/INIT1: description: DDRCTRL SDRAM initialization register 1. fields: - name: PRE_OCD_X32 description: PRE_OCD_X32. bit_offset: 0 bit_size: 4 - name: DRAM_RSTN_X1024 description: DRAM_RSTN_X1024. bit_offset: 16 bit_size: 9 fieldset/INIT2: description: DDRCTRL SDRAM initialization register 2. fields: - name: MIN_STABLE_CLOCK_X1 description: MIN_STABLE_CLOCK_X1. bit_offset: 0 bit_size: 4 - name: IDLE_AFTER_RESET_X32 description: IDLE_AFTER_RESET_X32. bit_offset: 8 bit_size: 8 fieldset/INIT3: description: DDRCTRL SDRAM initialization register 3. fields: - name: EMR description: EMR. bit_offset: 0 bit_size: 16 - name: MR description: MR. bit_offset: 16 bit_size: 16 fieldset/INIT4: description: DDRCTRL SDRAM initialization register 4. fields: - name: EMR3 description: EMR3. bit_offset: 0 bit_size: 16 - name: EMR2 description: EMR2. bit_offset: 16 bit_size: 16 fieldset/INIT5: description: DDRCTRL SDRAM initialization register 5. fields: - name: MAX_AUTO_INIT_X1024 description: MAX_AUTO_INIT_X1024. bit_offset: 0 bit_size: 10 - name: DEV_ZQINIT_X32 description: DEV_ZQINIT_X32. bit_offset: 16 bit_size: 8 fieldset/MRCTRL0: description: 'Mode Register Read/Write Control Register 0. Do not enable more than one of the following fields simultaneously: sw_init_int pda_en mpr_en.' fields: - name: MR_TYPE description: MR_TYPE. bit_offset: 0 bit_size: 1 - name: MR_RANK description: MR_RANK. bit_offset: 4 bit_size: 1 - name: MR_ADDR description: MR_ADDR. bit_offset: 12 bit_size: 4 - name: MR_WR description: MR_WR. bit_offset: 31 bit_size: 1 fieldset/MRCTRL1: description: DDRCTRL mode register read/write control register 1. fields: - name: MR_DATA description: MR_DATA. bit_offset: 0 bit_size: 16 fieldset/MRSTAT: description: DDRCTRL mode register read/write status register. fields: - name: MR_WR_BUSY description: MR_WR_BUSY. bit_offset: 0 bit_size: 1 fieldset/MSTR: description: DDRCTRL master register 0. fields: - name: DDR3 description: DDR3. bit_offset: 0 bit_size: 1 - name: LPDDR2 description: LPDDR2. bit_offset: 2 bit_size: 1 - name: LPDDR3 description: LPDDR3. bit_offset: 3 bit_size: 1 - name: BURSTCHOP description: BURSTCHOP. bit_offset: 9 bit_size: 1 - name: EN_2T_TIMING_MODE description: EN_2T_TIMING_MODE. bit_offset: 10 bit_size: 1 - name: DATA_BUS_WIDTH description: DATA_BUS_WIDTH. bit_offset: 12 bit_size: 2 - name: DLL_OFF_MODE description: DLL_OFF_MODE. bit_offset: 15 bit_size: 1 - name: BURST_RDWR description: BURST_RDWR. bit_offset: 16 bit_size: 4 fieldset/ODTCFG: description: DDRCTRL ODT configuration register. fields: - name: RD_ODT_DELAY description: RD_ODT_DELAY. bit_offset: 2 bit_size: 5 - name: RD_ODT_HOLD description: RD_ODT_HOLD. bit_offset: 8 bit_size: 4 - name: WR_ODT_DELAY description: WR_ODT_DELAY. bit_offset: 16 bit_size: 5 - name: WR_ODT_HOLD description: WR_ODT_HOLD. bit_offset: 24 bit_size: 4 fieldset/ODTMAP: description: DDRCTRL ODT/Rank map register. fields: - name: RANK0_WR_ODT description: RANK0_WR_ODT. bit_offset: 0 bit_size: 1 - name: RANK0_RD_ODT description: RANK0_RD_ODT. bit_offset: 4 bit_size: 1 fieldset/PCCFG: description: DDRCTRL port common configuration register. fields: - name: GO2CRITICAL_EN description: GO2CRITICAL_EN. bit_offset: 0 bit_size: 1 - name: PAGEMATCH_LIMIT description: PAGEMATCH_LIMIT. bit_offset: 4 bit_size: 1 - name: BL_EXP_MODE description: BL_EXP_MODE. bit_offset: 8 bit_size: 1 fieldset/PCFGQOS0_0: description: DDRCTRL port 0 read Q0S configuration register 0. fields: - name: RQOS_MAP_LEVEL1 description: RQOS_MAP_LEVEL1. bit_offset: 0 bit_size: 4 - name: RQOS_MAP_LEVEL2 description: RQOS_MAP_LEVEL2. bit_offset: 8 bit_size: 4 - name: RQOS_MAP_REGION0 description: RQOS_MAP_REGION0. bit_offset: 16 bit_size: 2 - name: RQOS_MAP_REGION1 description: RQOS_MAP_REGION1. bit_offset: 20 bit_size: 2 - name: RQOS_MAP_REGION2 description: RQOS_MAP_REGION2. bit_offset: 24 bit_size: 2 fieldset/PCFGQOS0_1: description: DDRCTRL port 1 read Q0S configuration register 0. fields: - name: RQOS_MAP_LEVEL1 description: RQOS_MAP_LEVEL1. bit_offset: 0 bit_size: 4 - name: RQOS_MAP_LEVEL2 description: RQOS_MAP_LEVEL2. bit_offset: 8 bit_size: 4 - name: RQOS_MAP_REGION0 description: RQOS_MAP_REGION0. bit_offset: 16 bit_size: 2 - name: RQOS_MAP_REGION1 description: RQOS_MAP_REGION1. bit_offset: 20 bit_size: 2 - name: RQOS_MAP_REGION2 description: RQOS_MAP_REGION2. bit_offset: 24 bit_size: 2 fieldset/PCFGQOS1_0: description: DDRCTRL port 0 read Q0S configuration register 1. fields: - name: RQOS_MAP_TIMEOUTB description: RQOS_MAP_TIMEOUTB. bit_offset: 0 bit_size: 11 - name: RQOS_MAP_TIMEOUTR description: RQOS_MAP_TIMEOUTR. bit_offset: 16 bit_size: 11 fieldset/PCFGQOS1_1: description: DDRCTRL port 1 read Q0S configuration register 1. fields: - name: RQOS_MAP_TIMEOUTB description: RQOS_MAP_TIMEOUTB. bit_offset: 0 bit_size: 11 - name: RQOS_MAP_TIMEOUTR description: RQOS_MAP_TIMEOUTR. bit_offset: 16 bit_size: 11 fieldset/PCFGR_0: description: DDRCTRL port 0 configuration read register. fields: - name: RD_PORT_PRIORITY description: RD_PORT_PRIORITY. bit_offset: 0 bit_size: 10 - name: RD_PORT_AGING_EN description: RD_PORT_AGING_EN. bit_offset: 12 bit_size: 1 - name: RD_PORT_URGENT_EN description: RD_PORT_URGENT_EN. bit_offset: 13 bit_size: 1 - name: RD_PORT_PAGEMATCH_EN description: RD_PORT_PAGEMATCH_EN. bit_offset: 14 bit_size: 1 - name: RDWR_ORDERED_EN description: RDWR_ORDERED_EN. bit_offset: 16 bit_size: 1 fieldset/PCFGR_1: description: DDRCTRL port 1 configuration read register. fields: - name: RD_PORT_PRIORITY description: RD_PORT_PRIORITY. bit_offset: 0 bit_size: 10 - name: RD_PORT_AGING_EN description: RD_PORT_AGING_EN. bit_offset: 12 bit_size: 1 - name: RD_PORT_URGENT_EN description: RD_PORT_URGENT_EN. bit_offset: 13 bit_size: 1 - name: RD_PORT_PAGEMATCH_EN description: RD_PORT_PAGEMATCH_EN. bit_offset: 14 bit_size: 1 - name: RDWR_ORDERED_EN description: RDWR_ORDERED_EN. bit_offset: 16 bit_size: 1 fieldset/PCFGWQOS0_0: description: DDRCTRL port 0 write Q0S configuration register 0. fields: - name: WQOS_MAP_LEVEL1 description: WQOS_MAP_LEVEL1. bit_offset: 0 bit_size: 4 - name: WQOS_MAP_LEVEL2 description: WQOS_MAP_LEVEL2. bit_offset: 8 bit_size: 4 - name: WQOS_MAP_REGION0 description: WQOS_MAP_REGION0. bit_offset: 16 bit_size: 2 - name: WQOS_MAP_REGION1 description: WQOS_MAP_REGION1. bit_offset: 20 bit_size: 2 - name: WQOS_MAP_REGION2 description: WQOS_MAP_REGION2. bit_offset: 24 bit_size: 2 fieldset/PCFGWQOS0_1: description: DDRCTRL port 1 write Q0S configuration register 0. fields: - name: WQOS_MAP_LEVEL1 description: WQOS_MAP_LEVEL1. bit_offset: 0 bit_size: 4 - name: WQOS_MAP_LEVEL2 description: WQOS_MAP_LEVEL2. bit_offset: 8 bit_size: 4 - name: WQOS_MAP_REGION0 description: WQOS_MAP_REGION0. bit_offset: 16 bit_size: 2 - name: WQOS_MAP_REGION1 description: WQOS_MAP_REGION1. bit_offset: 20 bit_size: 2 - name: WQOS_MAP_REGION2 description: WQOS_MAP_REGION2. bit_offset: 24 bit_size: 2 fieldset/PCFGWQOS1_0: description: DDRCTRL port 0 write Q0S configuration register 1. fields: - name: WQOS_MAP_TIMEOUT1 description: WQOS_MAP_TIMEOUT1. bit_offset: 0 bit_size: 11 - name: WQOS_MAP_TIMEOUT2 description: WQOS_MAP_TIMEOUT2. bit_offset: 16 bit_size: 11 fieldset/PCFGWQOS1_1: description: DDRCTRL port 1 write Q0S configuration register 1. fields: - name: WQOS_MAP_TIMEOUT1 description: WQOS_MAP_TIMEOUT1. bit_offset: 0 bit_size: 11 - name: WQOS_MAP_TIMEOUT2 description: WQOS_MAP_TIMEOUT2. bit_offset: 16 bit_size: 11 fieldset/PCFGW_0: description: DDRCTRL port 0 configuration write register. fields: - name: WR_PORT_PRIORITY description: WR_PORT_PRIORITY. bit_offset: 0 bit_size: 10 - name: WR_PORT_AGING_EN description: WR_PORT_AGING_EN. bit_offset: 12 bit_size: 1 - name: WR_PORT_URGENT_EN description: WR_PORT_URGENT_EN. bit_offset: 13 bit_size: 1 - name: WR_PORT_PAGEMATCH_EN description: WR_PORT_PAGEMATCH_EN. bit_offset: 14 bit_size: 1 fieldset/PCFGW_1: description: DDRCTRL port 1 configuration write register. fields: - name: WR_PORT_PRIORITY description: WR_PORT_PRIORITY. bit_offset: 0 bit_size: 10 - name: WR_PORT_AGING_EN description: WR_PORT_AGING_EN. bit_offset: 12 bit_size: 1 - name: WR_PORT_URGENT_EN description: WR_PORT_URGENT_EN. bit_offset: 13 bit_size: 1 - name: WR_PORT_PAGEMATCH_EN description: WR_PORT_PAGEMATCH_EN. bit_offset: 14 bit_size: 1 fieldset/PCTRL_0: description: DDRCTRL port 0 control register. fields: - name: PORT_EN description: PORT_EN. bit_offset: 0 bit_size: 1 fieldset/PCTRL_1: description: DDRCTRL port 1 control register. fields: - name: PORT_EN description: PORT_EN. bit_offset: 0 bit_size: 1 fieldset/PERFHPR1: description: DDRCTRL high priority read CAM register 1. fields: - name: HPR_MAX_STARVE description: HPR_MAX_STARVE. bit_offset: 0 bit_size: 16 - name: HPR_XACT_RUN_LENGTH description: HPR_XACT_RUN_LENGTH. bit_offset: 24 bit_size: 8 fieldset/PERFLPR1: description: DDRCTRL low priority read CAM register 1. fields: - name: LPR_MAX_STARVE description: LPR_MAX_STARVE. bit_offset: 0 bit_size: 16 - name: LPR_XACT_RUN_LENGTH description: LPR_XACT_RUN_LENGTH. bit_offset: 24 bit_size: 8 fieldset/PERFWR1: description: DDRCTRL write CAM register 1. fields: - name: W_MAX_STARVE description: W_MAX_STARVE. bit_offset: 0 bit_size: 16 - name: W_XACT_RUN_LENGTH description: W_XACT_RUN_LENGTH. bit_offset: 24 bit_size: 8 fieldset/POISONCFG: description: AXI Poison configuration register common for all AXI ports. fields: - name: WR_POISON_SLVERR_EN description: WR_POISON_SLVERR_EN. bit_offset: 0 bit_size: 1 - name: WR_POISON_INTR_EN description: WR_POISON_INTR_EN. bit_offset: 4 bit_size: 1 - name: WR_POISON_INTR_CLR description: WR_POISON_INTR_CLR. bit_offset: 8 bit_size: 1 - name: RD_POISON_SLVERR_EN description: RD_POISON_SLVERR_EN. bit_offset: 16 bit_size: 1 - name: RD_POISON_INTR_EN description: RD_POISON_INTR_EN. bit_offset: 20 bit_size: 1 - name: RD_POISON_INTR_CLR description: RD_POISON_INTR_CLR. bit_offset: 24 bit_size: 1 fieldset/POISONSTAT: description: DDRCTRL AXI Poison status register. fields: - name: WR_POISON_INTR_0 description: WR_POISON_INTR_0. bit_offset: 0 bit_size: 1 - name: WR_POISON_INTR_1 description: WR_POISON_INTR_1. bit_offset: 1 bit_size: 1 - name: RD_POISON_INTR_0 description: RD_POISON_INTR_0. bit_offset: 16 bit_size: 1 - name: RD_POISON_INTR_1 description: RD_POISON_INTR_1. bit_offset: 17 bit_size: 1 fieldset/PSTAT: description: DDRCTRL port status register. fields: - name: RD_PORT_BUSY_0 description: RD_PORT_BUSY_0. bit_offset: 0 bit_size: 1 - name: RD_PORT_BUSY_1 description: RD_PORT_BUSY_1. bit_offset: 1 bit_size: 1 - name: WR_PORT_BUSY_0 description: WR_PORT_BUSY_0. bit_offset: 16 bit_size: 1 - name: WR_PORT_BUSY_1 description: WR_PORT_BUSY_1. bit_offset: 17 bit_size: 1 fieldset/PWRCTL: description: DDRCTRL low power control register. fields: - name: SELFREF_EN description: SELFREF_EN. bit_offset: 0 bit_size: 1 - name: POWERDOWN_EN description: POWERDOWN_EN. bit_offset: 1 bit_size: 1 - name: DEEPPOWERDOWN_EN description: DEEPPOWERDOWN_EN. bit_offset: 2 bit_size: 1 - name: EN_DFI_DRAM_CLK_DISABLE description: EN_DFI_DRAM_CLK_DISABLE. bit_offset: 3 bit_size: 1 - name: SELFREF_SW description: SELFREF_SW. bit_offset: 5 bit_size: 1 - name: DIS_CAM_DRAIN_SELFREF description: DIS_CAM_DRAIN_SELFREF. bit_offset: 7 bit_size: 1 fieldset/PWRTMG: description: DDRCTRL low power timing register. fields: - name: POWERDOWN_TO_X32 description: POWERDOWN_TO_X32. bit_offset: 0 bit_size: 5 - name: T_DPD_X4096 description: T_DPD_X4096. bit_offset: 8 bit_size: 8 - name: SELFREF_TO_X32 description: SELFREF_TO_X32. bit_offset: 16 bit_size: 8 fieldset/RFSHCTL0: description: DDRCTRL refresh control register 0. fields: - name: PER_BANK_REFRESH description: PER_BANK_REFRESH. bit_offset: 2 bit_size: 1 - name: REFRESH_BURST description: REFRESH_BURST. bit_offset: 4 bit_size: 5 - name: REFRESH_TO_X32 description: REFRESH_TO_X32. bit_offset: 12 bit_size: 5 - name: REFRESH_MARGIN description: REFRESH_MARGIN. bit_offset: 20 bit_size: 4 fieldset/RFSHCTL3: description: DDRCTRL refresh control register 3. fields: - name: DIS_AUTO_REFRESH description: DIS_AUTO_REFRESH. bit_offset: 0 bit_size: 1 - name: REFRESH_UPDATE_LEVEL description: REFRESH_UPDATE_LEVEL. bit_offset: 1 bit_size: 1 fieldset/RFSHTMG: description: DDRCTRL refresh timing register. fields: - name: T_RFC_MIN description: T_RFC_MIN. bit_offset: 0 bit_size: 10 - name: LPDDR3_TREFBW_EN description: LPDDR3_TREFBW_EN. bit_offset: 15 bit_size: 1 - name: T_RFC_NOM_X1_X32 description: T_RFC_NOM_X1_X32. bit_offset: 16 bit_size: 12 - name: T_RFC_NOM_X1_SEL description: T_RFC_NOM_X1_SEL. bit_offset: 31 bit_size: 1 fieldset/SCHED: description: DDRCTRL scheduler control register. fields: - name: FORCE_LOW_PRI_N description: FORCE_LOW_PRI_N. bit_offset: 0 bit_size: 1 - name: PREFER_WRITE description: PREFER_WRITE. bit_offset: 1 bit_size: 1 - name: PAGECLOSE description: PAGECLOSE. bit_offset: 2 bit_size: 1 - name: LPR_NUM_ENTRIES description: LPR_NUM_ENTRIES. bit_offset: 8 bit_size: 4 - name: GO2CRITICAL_HYSTERESIS description: GO2CRITICAL_HYSTERESIS. bit_offset: 16 bit_size: 8 - name: RDWR_IDLE_GAP description: RDWR_IDLE_GAP. bit_offset: 24 bit_size: 7 fieldset/SCHED1: description: DDRCTRL scheduler control register 1. fields: - name: PAGECLOSE_TIMER description: PAGECLOSE_TIMER. bit_offset: 0 bit_size: 8 fieldset/STAT: description: DDRCTRL operating mode status register. fields: - name: OPERATING_MODE description: OPERATING_MODE. bit_offset: 0 bit_size: 3 - name: SELFREF_TYPE description: SELFREF_TYPE. bit_offset: 4 bit_size: 2 - name: SELFREF_CAM_NOT_EMPTY description: SELFREF_CAM_NOT_EMPTY. bit_offset: 12 bit_size: 1 fieldset/SWCTL: description: DDRCTRL software register programming control enable. fields: - name: SW_DONE description: SW_DONE. bit_offset: 0 bit_size: 1 fieldset/SWSTAT: description: DDRCTRL software register programming control status. fields: - name: SW_DONE_ACK description: SW_DONE_ACK. bit_offset: 0 bit_size: 1 fieldset/ZQCTL0: description: DDRCTRL ZQ control register 0. fields: - name: T_ZQ_SHORT_NOP description: T_ZQ_SHORT_NOP. bit_offset: 0 bit_size: 10 - name: T_ZQ_LONG_NOP description: T_ZQ_LONG_NOP. bit_offset: 16 bit_size: 11 - name: ZQ_RESISTOR_SHARED description: ZQ_RESISTOR_SHARED. bit_offset: 29 bit_size: 1 - name: DIS_SRX_ZQCL description: DIS_SRX_ZQCL. bit_offset: 30 bit_size: 1 - name: DIS_AUTO_ZQ description: DIS_AUTO_ZQ. bit_offset: 31 bit_size: 1 fieldset/ZQCTL1: description: DDRCTRL ZQ control register 1. fields: - name: T_ZQ_SHORT_INTERVAL_X1024 description: T_ZQ_SHORT_INTERVAL_X1024. bit_offset: 0 bit_size: 20 - name: T_ZQ_RESET_NOP description: T_ZQ_RESET_NOP. bit_offset: 20 bit_size: 10 fieldset/ZQCTL2: description: DDRCTRL ZQ control register 2. fields: - name: ZQ_RESET description: ZQ_RESET. bit_offset: 0 bit_size: 1 fieldset/ZQSTAT: description: DDRCTRL ZQ status register. fields: - name: ZQ_RESET_BUSY description: ZQ_RESET_BUSY. bit_offset: 0 bit_size: 1