block/DAC1:
  description: DAC1.
  items:
  - name: CR
    description: DAC control register.
    byte_offset: 0
    fieldset: CR
  - name: SWTRGR
    description: DAC software trigger register.
    byte_offset: 4
    access: Write
    fieldset: SWTRGR
  - name: DHR12R1
    description: DAC channel1 12-bit right-aligned data holding register.
    byte_offset: 8
    fieldset: DHR12R1
  - name: DHR12L1
    description: DAC channel1 12-bit left aligned data holding register.
    byte_offset: 12
    fieldset: DHR12L1
  - name: DHR8R1
    description: DAC channel1 8-bit right aligned data holding register.
    byte_offset: 16
    fieldset: DHR8R1
  - name: DHR12R2
    description: 'This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.'
    byte_offset: 20
    fieldset: DHR12R2
  - name: DHR12L2
    description: 'This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.'
    byte_offset: 24
    fieldset: DHR12L2
  - name: DHR8R2
    description: 'This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.'
    byte_offset: 28
    fieldset: DHR8R2
  - name: DHR12RD
    description: Dual DAC 12-bit right-aligned data holding register.
    byte_offset: 32
    fieldset: DHR12RD
  - name: DHR12LD
    description: Dual DAC 12-bit left aligned data holding register.
    byte_offset: 36
    fieldset: DHR12LD
  - name: DHR8RD
    description: Dual DAC 8-bit right aligned data holding register.
    byte_offset: 40
    fieldset: DHR8RD
  - name: DOR1
    description: DAC channel1 data output register.
    byte_offset: 44
    access: Read
    fieldset: DOR1
  - name: DOR2
    description: 'This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.'
    byte_offset: 48
    access: Read
    fieldset: DOR2
  - name: SR
    description: DAC status register.
    byte_offset: 52
    fieldset: SR
  - name: CCR
    description: DAC calibration control register.
    byte_offset: 56
    fieldset: CCR
  - name: MCR
    description: DAC mode control register.
    byte_offset: 60
    fieldset: MCR
  - name: SHSR1
    description: DAC channel 1 sample and hold sample time register.
    byte_offset: 64
    fieldset: SHSR1
  - name: SHSR2
    description: 'This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.'
    byte_offset: 68
    fieldset: SHSR2
  - name: SHHR
    description: DAC sample and hold time register.
    byte_offset: 72
    fieldset: SHHR
  - name: SHRR
    description: DAC sample and hold refresh time register.
    byte_offset: 76
    fieldset: SHRR
  - name: HWCFGR0
    description: DAC IP hardware configuration register.
    byte_offset: 1008
    access: Read
    fieldset: HWCFGR0
  - name: VERR
    description: No.
    byte_offset: 1012
    access: Read
    fieldset: VERR
  - name: IPIDR
    description: No.
    byte_offset: 1016
    access: Read
    fieldset: IPIDR
  - name: SIDR
    description: No.
    byte_offset: 1020
    access: Read
    fieldset: SIDR
fieldset/CCR:
  description: DAC calibration control register.
  fields:
  - name: OTRIM1
    description: OTRIM1.
    bit_offset: 0
    bit_size: 5
  - name: OTRIM2
    description: OTRIM2.
    bit_offset: 16
    bit_size: 5
fieldset/CR:
  description: DAC control register.
  fields:
  - name: EN1
    description: EN1.
    bit_offset: 0
    bit_size: 1
  - name: TEN1
    description: TEN1.
    bit_offset: 1
    bit_size: 1
  - name: TSEL10
    description: TSEL10.
    bit_offset: 2
    bit_size: 1
  - name: TSEL11
    description: TSEL11.
    bit_offset: 3
    bit_size: 1
  - name: TSEL12
    description: TSEL12.
    bit_offset: 4
    bit_size: 1
  - name: TSEL13
    description: TSEL13.
    bit_offset: 5
    bit_size: 1
  - name: WAVE1
    description: WAVE1.
    bit_offset: 6
    bit_size: 2
  - name: MAMP1
    description: MAMP1.
    bit_offset: 8
    bit_size: 4
  - name: DMAEN1
    description: DMAEN1.
    bit_offset: 12
    bit_size: 1
  - name: DMAUDRIE1
    description: DMAUDRIE1.
    bit_offset: 13
    bit_size: 1
  - name: CEN1
    description: CEN1.
    bit_offset: 14
    bit_size: 1
  - name: HFSEL
    description: HFSEL.
    bit_offset: 15
    bit_size: 1
  - name: EN2
    description: EN2.
    bit_offset: 16
    bit_size: 1
  - name: TEN2
    description: TEN2.
    bit_offset: 17
    bit_size: 1
  - name: TSEL20
    description: TSEL20.
    bit_offset: 18
    bit_size: 1
  - name: TSEL21
    description: TSEL21.
    bit_offset: 19
    bit_size: 1
  - name: TSEL22
    description: TSEL22.
    bit_offset: 20
    bit_size: 1
  - name: TSEL23
    description: TSEL23.
    bit_offset: 21
    bit_size: 1
  - name: WAVE2
    description: WAVE2.
    bit_offset: 22
    bit_size: 2
  - name: MAMP2
    description: MAMP2.
    bit_offset: 24
    bit_size: 4
  - name: DMAEN2
    description: DMAEN2.
    bit_offset: 28
    bit_size: 1
  - name: DMAUDRIE2
    description: DMAUDRIE2.
    bit_offset: 29
    bit_size: 1
  - name: CEN2
    description: CEN2.
    bit_offset: 30
    bit_size: 1
fieldset/DHR12L1:
  description: DAC channel1 12-bit left aligned data holding register.
  fields:
  - name: DACC1DHR
    description: DACC1DHR.
    bit_offset: 4
    bit_size: 12
fieldset/DHR12L2:
  description: 'This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.'
  fields:
  - name: DACC2DHR
    description: DACC2DHR.
    bit_offset: 4
    bit_size: 12
fieldset/DHR12LD:
  description: Dual DAC 12-bit left aligned data holding register.
  fields:
  - name: DACC1DHR
    description: DACC1DHR.
    bit_offset: 4
    bit_size: 12
  - name: DACC2DHR
    description: DACC2DHR.
    bit_offset: 20
    bit_size: 12
fieldset/DHR12R1:
  description: DAC channel1 12-bit right-aligned data holding register.
  fields:
  - name: DACC1DHR
    description: DACC1DHR.
    bit_offset: 0
    bit_size: 12
fieldset/DHR12R2:
  description: 'This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.'
  fields:
  - name: DACC2DHR
    description: DACC2DHR.
    bit_offset: 0
    bit_size: 12
fieldset/DHR12RD:
  description: Dual DAC 12-bit right-aligned data holding register.
  fields:
  - name: DACC1DHR
    description: DACC1DHR.
    bit_offset: 0
    bit_size: 12
  - name: DACC2DHR
    description: DACC2DHR.
    bit_offset: 16
    bit_size: 12
fieldset/DHR8R1:
  description: DAC channel1 8-bit right aligned data holding register.
  fields:
  - name: DACC1DHR
    description: DACC1DHR.
    bit_offset: 0
    bit_size: 8
fieldset/DHR8R2:
  description: 'This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.'
  fields:
  - name: DACC2DHR
    description: DACC2DHR.
    bit_offset: 0
    bit_size: 8
fieldset/DHR8RD:
  description: Dual DAC 8-bit right aligned data holding register.
  fields:
  - name: DACC1DHR
    description: DACC1DHR.
    bit_offset: 0
    bit_size: 8
  - name: DACC2DHR
    description: DACC2DHR.
    bit_offset: 8
    bit_size: 8
fieldset/DOR1:
  description: DAC channel1 data output register.
  fields:
  - name: DACC1DOR
    description: DACC1DOR.
    bit_offset: 0
    bit_size: 12
fieldset/DOR2:
  description: 'This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.'
  fields:
  - name: DACC2DOR
    description: DACC2DOR.
    bit_offset: 0
    bit_size: 12
fieldset/HWCFGR0:
  description: DAC IP hardware configuration register.
  fields:
  - name: DUAL
    description: DUAL.
    bit_offset: 0
    bit_size: 4
  - name: LFSR
    description: LFSR.
    bit_offset: 4
    bit_size: 4
  - name: TRIANGLE
    description: TRIANGLE.
    bit_offset: 8
    bit_size: 4
  - name: SAMPLE
    description: SAMPLE.
    bit_offset: 12
    bit_size: 4
  - name: OR_CFG
    description: OR_CFG.
    bit_offset: 16
    bit_size: 8
fieldset/IPIDR:
  description: No.
  fields:
  - name: ID
    description: ID.
    bit_offset: 0
    bit_size: 32
fieldset/MCR:
  description: DAC mode control register.
  fields:
  - name: MODE1
    description: MODE1.
    bit_offset: 0
    bit_size: 3
  - name: MODE2
    description: MODE2.
    bit_offset: 16
    bit_size: 3
fieldset/SHHR:
  description: DAC sample and hold time register.
  fields:
  - name: THOLD1
    description: THOLD1.
    bit_offset: 0
    bit_size: 10
  - name: THOLD2
    description: THOLD2.
    bit_offset: 16
    bit_size: 10
fieldset/SHRR:
  description: DAC sample and hold refresh time register.
  fields:
  - name: TREFRESH1
    description: TREFRESH1.
    bit_offset: 0
    bit_size: 8
  - name: TREFRESH2
    description: TREFRESH2.
    bit_offset: 16
    bit_size: 8
fieldset/SHSR1:
  description: DAC channel 1 sample and hold sample time register.
  fields:
  - name: TSAMPLE1
    description: TSAMPLE1.
    bit_offset: 0
    bit_size: 10
fieldset/SHSR2:
  description: 'This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.'
  fields:
  - name: TSAMPLE2
    description: TSAMPLE2.
    bit_offset: 0
    bit_size: 10
fieldset/SIDR:
  description: No.
  fields:
  - name: SID
    description: SID.
    bit_offset: 0
    bit_size: 32
fieldset/SR:
  description: DAC status register.
  fields:
  - name: DMAUDR1
    description: DMAUDR1.
    bit_offset: 13
    bit_size: 1
  - name: CAL_FLAG1
    description: CAL_FLAG1.
    bit_offset: 14
    bit_size: 1
  - name: BWST1
    description: BWST1.
    bit_offset: 15
    bit_size: 1
  - name: DMAUDR2
    description: DMAUDR2.
    bit_offset: 29
    bit_size: 1
  - name: CAL_FLAG2
    description: CAL_FLAG2.
    bit_offset: 30
    bit_size: 1
  - name: BWST2
    description: BWST2.
    bit_offset: 31
    bit_size: 1
fieldset/SWTRGR:
  description: DAC software trigger register.
  fields:
  - name: SWTRIG1
    description: SWTRIG1.
    bit_offset: 0
    bit_size: 1
  - name: SWTRIG2
    description: SWTRIG2.
    bit_offset: 1
    bit_size: 1
fieldset/VERR:
  description: No.
  fields:
  - name: MINREV
    description: MINREV.
    bit_offset: 0
    bit_size: 4
  - name: MAJREV
    description: MAJREV.
    bit_offset: 4
    bit_size: 4