block/TIM2:
  description: General purpose timer.
  items:
  - name: CR1
    description: control register 1.
    byte_offset: 0
    bit_size: 16
    fieldset: CR1
  - name: CR2
    description: control register 2.
    byte_offset: 4
    bit_size: 16
    fieldset: CR2
  - name: SMCR
    description: slave mode control register.
    byte_offset: 8
    bit_size: 16
    fieldset: SMCR
  - name: DIER
    description: DMA/Interrupt enable register.
    byte_offset: 12
    bit_size: 16
    fieldset: DIER
  - name: SR
    description: status register.
    byte_offset: 16
    bit_size: 16
    fieldset: SR
  - name: EGR
    description: event generation register.
    byte_offset: 20
    access: Write
    bit_size: 16
    fieldset: EGR
  - name: CCMR1_Input
    description: capture/compare mode register 1 (input mode).
    byte_offset: 24
    bit_size: 16
    fieldset: CCMR1_Input
  - name: CCMR1_Output
    description: capture/compare mode register 1 (output mode).
    byte_offset: 24
    bit_size: 16
    fieldset: CCMR1_Output
  - name: CCMR2_Input
    description: capture/compare mode register 2 (input mode).
    byte_offset: 28
    bit_size: 16
    fieldset: CCMR2_Input
  - name: CCMR2_Output
    description: capture/compare mode register 2 (output mode).
    byte_offset: 28
    bit_size: 16
    fieldset: CCMR2_Output
  - name: CCER
    description: capture/compare enable register.
    byte_offset: 32
    bit_size: 16
    fieldset: CCER
  - name: CNT
    description: counter.
    byte_offset: 36
    bit_size: 16
    fieldset: CNT
  - name: PSC
    description: prescaler.
    byte_offset: 40
    bit_size: 16
    fieldset: PSC
  - name: ARR
    description: auto-reload register.
    byte_offset: 44
    bit_size: 16
    fieldset: ARR
  - name: CCR
    description: capture/compare register.
    array:
      len: 4
      stride: 4
    byte_offset: 52
    bit_size: 16
    fieldset: CCR
  - name: DCR
    description: DMA control register.
    byte_offset: 72
    bit_size: 16
    fieldset: DCR
  - name: DMAR
    description: DMA address for full transfer.
    byte_offset: 76
    bit_size: 16
    fieldset: DMAR
fieldset/ARR:
  description: auto-reload register.
  bit_size: 16
  fields:
  - name: ARR
    description: Auto-reload value.
    bit_offset: 0
    bit_size: 16
fieldset/CCER:
  description: capture/compare enable register.
  bit_size: 16
  fields:
  - name: CCE
    description: Capture/Compare %s output enable.
    bit_offset: 0
    bit_size: 1
    array:
      len: 4
      stride: 4
    enum: CCE
  - name: CCP
    description: Capture/Compare %s output Polarity.
    bit_offset: 1
    bit_size: 1
    array:
      len: 4
      stride: 4
    enum: CCP
fieldset/CCMR1_Input:
  description: capture/compare mode register 1 (input mode).
  bit_size: 16
  fields:
  - name: CC1S
    description: Capture/Compare 1 selection.
    bit_offset: 0
    bit_size: 2
    enum: CC1S
  - name: ICPSC
    description: Input capture %s prescaler.
    bit_offset: 2
    bit_size: 2
    array:
      len: 2
      stride: 8
    enum: ICPSC
  - name: ICF
    description: Input capture %s filter.
    bit_offset: 4
    bit_size: 4
    array:
      len: 2
      stride: 8
    enum: ICF
  - name: CC2S
    description: Capture/compare 2 selection.
    bit_offset: 8
    bit_size: 2
    enum: CC2S
fieldset/CCMR1_Output:
  description: capture/compare mode register 1 (output mode).
  bit_size: 16
  fields:
  - name: CCS
    description: Capture/Compare %s selection.
    bit_offset: 0
    bit_size: 2
    array:
      len: 2
      stride: 8
    enum: CCS
  - name: OCFE
    description: Output compare %s fast enable.
    bit_offset: 2
    bit_size: 1
    array:
      len: 2
      stride: 8
    enum: OCFE
  - name: OCPE
    description: Output compare %s preload enable.
    bit_offset: 3
    bit_size: 1
    array:
      len: 2
      stride: 8
    enum: OCPE
  - name: OCM
    description: Output compare %s mode.
    bit_offset: 4
    bit_size: 3
    array:
      len: 2
      stride: 8
    enum: OCM
  - name: OCCE
    description: Output compare %s clear enable.
    bit_offset: 7
    bit_size: 1
    array:
      len: 2
      stride: 8
    enum: OCCE
fieldset/CCMR2_Input:
  description: capture/compare mode register 2 (input mode).
  bit_size: 16
  fields:
  - name: CC3S
    description: Capture/Compare 3 selection.
    bit_offset: 0
    bit_size: 2
    enum: CC3S
  - name: CC4S
    description: Capture/Compare 4 selection.
    bit_offset: 8
    bit_size: 2
    enum: CC4S
fieldset/CCMR2_Output:
  description: capture/compare mode register 2 (output mode).
  bit_size: 16
  fields: []
fieldset/CCR:
  description: capture/compare register.
  bit_size: 16
  fields:
  - name: CCR
    description: Capture/Compare value.
    bit_offset: 0
    bit_size: 16
fieldset/CNT:
  description: counter.
  bit_size: 16
  fields:
  - name: CNT
    description: counter value.
    bit_offset: 0
    bit_size: 16
fieldset/CR1:
  description: control register 1.
  bit_size: 16
  fields:
  - name: CEN
    description: Counter enable.
    bit_offset: 0
    bit_size: 1
    enum: CEN
  - name: UDIS
    description: Update disable.
    bit_offset: 1
    bit_size: 1
    enum: UDIS
  - name: URS
    description: Update request source.
    bit_offset: 2
    bit_size: 1
    enum: URS
  - name: OPM
    description: One-pulse mode.
    bit_offset: 3
    bit_size: 1
    enum: OPM
  - name: DIR
    description: Direction.
    bit_offset: 4
    bit_size: 1
    enum: DIR
  - name: CMS
    description: Center-aligned mode selection.
    bit_offset: 5
    bit_size: 2
    enum: CMS
  - name: ARPE
    description: Auto-reload preload enable.
    bit_offset: 7
    bit_size: 1
    enum: ARPE
  - name: CKD
    description: Clock division.
    bit_offset: 8
    bit_size: 2
    enum: CKD
fieldset/CR2:
  description: control register 2.
  bit_size: 16
  fields:
  - name: CCDS
    description: Capture/compare DMA selection.
    bit_offset: 3
    bit_size: 1
    enum: CCDS
  - name: MMS
    description: Master mode selection.
    bit_offset: 4
    bit_size: 3
    enum: MMS
  - name: TI1S
    description: TI1 selection.
    bit_offset: 7
    bit_size: 1
    enum: TI1S
fieldset/DCR:
  description: DMA control register.
  bit_size: 16
  fields:
  - name: DBA
    description: DMA base address.
    bit_offset: 0
    bit_size: 5
  - name: DBL
    description: DMA burst length.
    bit_offset: 8
    bit_size: 5
fieldset/DIER:
  description: DMA/Interrupt enable register.
  bit_size: 16
  fields:
  - name: UIE
    description: Update interrupt enable.
    bit_offset: 0
    bit_size: 1
    enum: UIE
  - name: CCIE
    description: Capture/Compare %s interrupt enable.
    bit_offset: 1
    bit_size: 1
    array:
      len: 4
      stride: 1
    enum: CCIE
  - name: TIE
    description: Trigger interrupt enable.
    bit_offset: 6
    bit_size: 1
    enum: TIE
  - name: UDE
    description: Update DMA request enable.
    bit_offset: 8
    bit_size: 1
    enum: UDE
  - name: CCDE
    description: Capture/Compare %s DMA request enable.
    bit_offset: 9
    bit_size: 1
    array:
      len: 4
      stride: 1
    enum: CCDE
  - name: TDE
    description: Trigger DMA request enable.
    bit_offset: 14
    bit_size: 1
    enum: TDE
fieldset/DMAR:
  description: DMA address for full transfer.
  bit_size: 16
  fields:
  - name: DMAB
    description: DMA register for burst accesses.
    bit_offset: 0
    bit_size: 16
fieldset/EGR:
  description: event generation register.
  bit_size: 16
  fields:
  - name: UG
    description: Update generation.
    bit_offset: 0
    bit_size: 1
    enum: UG
  - name: CCG
    description: Capture/compare %s generation.
    bit_offset: 1
    bit_size: 1
    array:
      len: 4
      stride: 1
    enum: CCG
  - name: TG
    description: Trigger generation.
    bit_offset: 6
    bit_size: 1
    enum: TG
fieldset/PSC:
  description: prescaler.
  bit_size: 16
  fields:
  - name: PSC
    description: Prescaler value.
    bit_offset: 0
    bit_size: 16
fieldset/SMCR:
  description: slave mode control register.
  bit_size: 16
  fields:
  - name: SMS
    description: Slave mode selection.
    bit_offset: 0
    bit_size: 3
    enum: SMS
  - name: TS
    description: Trigger selection.
    bit_offset: 4
    bit_size: 3
    enum: TS
  - name: MSM
    description: Master/Slave mode.
    bit_offset: 7
    bit_size: 1
    enum: MSM
  - name: ETF
    description: External trigger filter.
    bit_offset: 8
    bit_size: 4
    enum: ETF
  - name: ETPS
    description: External trigger prescaler.
    bit_offset: 12
    bit_size: 2
    enum: ETPS
  - name: ECE
    description: External clock enable.
    bit_offset: 14
    bit_size: 1
    enum: ECE
  - name: ETP
    description: External trigger polarity.
    bit_offset: 15
    bit_size: 1
    enum: ETP
fieldset/SR:
  description: status register.
  bit_size: 16
  fields:
  - name: UIF
    description: Update interrupt flag.
    bit_offset: 0
    bit_size: 1
    enum: UIF
  - name: CCIF
    description: Capture/compare %s interrupt flag.
    bit_offset: 1
    bit_size: 1
    array:
      len: 4
      stride: 1
    enum: CCIF
  - name: TIF
    description: Trigger interrupt flag.
    bit_offset: 6
    bit_size: 1
    enum: TIF
  - name: CCOF
    description: Capture/Compare %s overcapture flag.
    bit_offset: 9
    bit_size: 1
    array:
      len: 4
      stride: 1
    enum: CCOF
enum/ARPE:
  bit_size: 1
  variants:
  - name: Disabled
    description: TIMx_APRR register is not buffered.
    value: 0
  - name: Enabled
    description: TIMx_APRR register is buffered.
    value: 1
enum/CC1S:
  bit_size: 2
  variants:
  - name: TI1
    description: CC1 channel is configured as input, IC1 is mapped on TI1.
    value: 1
  - name: TI2
    description: CC1 channel is configured as input, IC1 is mapped on TI2.
    value: 2
  - name: TRC
    description: CC1 channel is configured as input, IC1 is mapped on TRC.
    value: 3
enum/CC2S:
  bit_size: 2
  variants:
  - name: TI2
    description: CC2 channel is configured as input, IC2 is mapped on TI2.
    value: 1
  - name: TI1
    description: CC2 channel is configured as input, IC2 is mapped on TI1.
    value: 2
  - name: TRC
    description: CC2 channel is configured as input, IC2 is mapped on TRC.
    value: 3
enum/CC3S:
  bit_size: 2
  variants:
  - name: TI3
    description: CC3 channel is configured as input, IC3 is mapped on TI3.
    value: 1
  - name: TI4
    description: CC3 channel is configured as input, IC3 is mapped on TI4.
    value: 2
  - name: TRC
    description: CC3 channel is configured as input, IC3 is mapped on TRC.
    value: 3
enum/CC4S:
  bit_size: 2
  variants:
  - name: TI4
    description: CC4 channel is configured as input, IC4 is mapped on TI4.
    value: 1
  - name: TI3
    description: CC4 channel is configured as input, IC4 is mapped on TI3.
    value: 2
  - name: TRC
    description: CC4 channel is configured as input, IC4 is mapped on TRC.
    value: 3
enum/CCDE:
  bit_size: 1
  variants:
  - name: Disabled
    description: CCx DMA request disabled.
    value: 0
  - name: Enabled
    description: CCx DMA request enabled.
    value: 1
enum/CCDS:
  bit_size: 1
  variants:
  - name: OnCompare
    description: CCx DMA request sent when CCx event occurs.
    value: 0
  - name: OnUpdate
    description: CCx DMA request sent when update event occurs.
    value: 1
enum/CCE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Capture disabled.
    value: 0
  - name: Enabled
    description: Capture enabled.
    value: 1
enum/CCG:
  bit_size: 1
  variants:
  - name: Trigger
    description: 'If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.'
    value: 1
enum/CCIE:
  bit_size: 1
  variants:
  - name: Disabled
    description: CCx interrupt disabled.
    value: 0
  - name: Enabled
    description: CCx interrupt enabled.
    value: 1
enum/CCIF:
  bit_size: 1
  variants:
  - name: R_NoMatch_W_Clear
    description: No campture/compare has been detected.
    value: 0
  - name: Match
    description: 'If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.'
    value: 1
enum/CCOF:
  bit_size: 1
  variants:
  - name: R_NoOvercapture_W_Clear
    description: No overcapture has been detected.
    value: 0
  - name: Overcapture
    description: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set.
    value: 1
enum/CCP:
  bit_size: 1
  variants:
  - name: RisingEdge
    description: Noninverted/rising edge.
    value: 0
  - name: FallingEdge
    description: Inverted/falling edge.
    value: 1
enum/CCS:
  bit_size: 2
  variants:
  - name: Output
    description: CCx channel is configured as output.
    value: 0
enum/CEN:
  bit_size: 1
  variants:
  - name: Disabled
    description: Counter disabled.
    value: 0
  - name: Enabled
    description: Counter enabled.
    value: 1
enum/CKD:
  bit_size: 2
  variants:
  - name: Div1
    description: t_DTS = t_CK_INT.
    value: 0
  - name: Div2
    description: t_DTS = 2 × t_CK_INT.
    value: 1
  - name: Div4
    description: t_DTS = 4 × t_CK_INT.
    value: 2
enum/CMS:
  bit_size: 2
  variants:
  - name: EdgeAligned
    description: The counter counts up or down depending on the direction bit.
    value: 0
  - name: CenterAligned1
    description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
    value: 1
  - name: CenterAligned2
    description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
    value: 2
  - name: CenterAligned3
    description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
    value: 3
enum/DIR:
  bit_size: 1
  variants:
  - name: Up
    description: Counter used as upcounter.
    value: 0
  - name: Down
    description: Counter used as downcounter.
    value: 1
enum/ECE:
  bit_size: 1
  variants:
  - name: Disabled
    description: External clock mode 2 disabled.
    value: 0
  - name: Enabled
    description: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
    value: 1
enum/ETF:
  bit_size: 4
  variants:
  - name: NoFilter
    description: No filter, sampling is done at fDTS.
    value: 0
  - name: FCK_INT_N2
    description: fSAMPLING=fCK_INT, N=2.
    value: 1
  - name: FCK_INT_N4
    description: fSAMPLING=fCK_INT, N=4.
    value: 2
  - name: FCK_INT_N8
    description: fSAMPLING=fCK_INT, N=8.
    value: 3
  - name: FDTS_Div2_N6
    description: fSAMPLING=fDTS/2, N=6.
    value: 4
  - name: FDTS_Div2_N8
    description: fSAMPLING=fDTS/2, N=8.
    value: 5
  - name: FDTS_Div4_N6
    description: fSAMPLING=fDTS/4, N=6.
    value: 6
  - name: FDTS_Div4_N8
    description: fSAMPLING=fDTS/4, N=8.
    value: 7
  - name: FDTS_Div8_N6
    description: fSAMPLING=fDTS/8, N=6.
    value: 8
  - name: FDTS_Div8_N8
    description: fSAMPLING=fDTS/8, N=8.
    value: 9
  - name: FDTS_Div16_N5
    description: fSAMPLING=fDTS/16, N=5.
    value: 10
  - name: FDTS_Div16_N6
    description: fSAMPLING=fDTS/16, N=6.
    value: 11
  - name: FDTS_Div16_N8
    description: fSAMPLING=fDTS/16, N=8.
    value: 12
  - name: FDTS_Div32_N5
    description: fSAMPLING=fDTS/32, N=5.
    value: 13
  - name: FDTS_Div32_N6
    description: fSAMPLING=fDTS/32, N=6.
    value: 14
  - name: FDTS_Div32_N8
    description: fSAMPLING=fDTS/32, N=8.
    value: 15
enum/ETP:
  bit_size: 1
  variants:
  - name: NotInverted
    description: ETR is noninverted, active at high level or rising edge.
    value: 0
  - name: Inverted
    description: ETR is inverted, active at low level or falling edge.
    value: 1
enum/ETPS:
  bit_size: 2
  variants:
  - name: Div1
    description: Prescaler OFF.
    value: 0
  - name: Div2
    description: ETRP frequency divided by 2.
    value: 1
  - name: Div4
    description: ETRP frequency divided by 4.
    value: 2
  - name: Div8
    description: ETRP frequency divided by 8.
    value: 3
enum/ICF:
  bit_size: 4
  variants:
  - name: NoFilter
    description: No filter, sampling is done at fDTS.
    value: 0
  - name: FCK_INT_N2
    description: fSAMPLING=fCK_INT, N=2.
    value: 1
  - name: FCK_INT_N4
    description: fSAMPLING=fCK_INT, N=4.
    value: 2
  - name: FCK_INT_N8
    description: fSAMPLING=fCK_INT, N=8.
    value: 3
  - name: FDTS_Div2_N6
    description: fSAMPLING=fDTS/2, N=6.
    value: 4
  - name: FDTS_Div2_N8
    description: fSAMPLING=fDTS/2, N=8.
    value: 5
  - name: FDTS_Div4_N6
    description: fSAMPLING=fDTS/4, N=6.
    value: 6
  - name: FDTS_Div4_N8
    description: fSAMPLING=fDTS/4, N=8.
    value: 7
  - name: FDTS_Div8_N6
    description: fSAMPLING=fDTS/8, N=6.
    value: 8
  - name: FDTS_Div8_N8
    description: fSAMPLING=fDTS/8, N=8.
    value: 9
  - name: FDTS_Div16_N5
    description: fSAMPLING=fDTS/16, N=5.
    value: 10
  - name: FDTS_Div16_N6
    description: fSAMPLING=fDTS/16, N=6.
    value: 11
  - name: FDTS_Div16_N8
    description: fSAMPLING=fDTS/16, N=8.
    value: 12
  - name: FDTS_Div32_N5
    description: fSAMPLING=fDTS/32, N=5.
    value: 13
  - name: FDTS_Div32_N6
    description: fSAMPLING=fDTS/32, N=6.
    value: 14
  - name: FDTS_Div32_N8
    description: fSAMPLING=fDTS/32, N=8.
    value: 15
enum/ICPSC:
  bit_size: 2
  variants:
  - name: NoPrescaler
    description: No prescaler, capture is done each time an edge is detected on the capture input.
    value: 0
  - name: TwoEvents
    description: Capture is done once every 2 events.
    value: 1
  - name: FourEvents
    description: Capture is done once every 4 events.
    value: 2
  - name: EightEvents
    description: Capture is done once every 8 events.
    value: 3
enum/MMS:
  bit_size: 3
  variants:
  - name: Reset
    description: The UG bit from the TIMx_EGR register is used as trigger output.
    value: 0
  - name: Enable
    description: The counter enable signal, CNT_EN, is used as trigger output.
    value: 1
  - name: Update
    description: The update event is selected as trigger output.
    value: 2
  - name: ComparePulse
    description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred.
    value: 3
  - name: CompareOC1
    description: OC1REF signal is used as trigger output.
    value: 4
  - name: CompareOC2
    description: OC2REF signal is used as trigger output.
    value: 5
  - name: CompareOC3
    description: OC3REF signal is used as trigger output.
    value: 6
  - name: CompareOC4
    description: OC4REF signal is used as trigger output.
    value: 7
enum/MSM:
  bit_size: 1
  variants:
  - name: NoSync
    description: No action.
    value: 0
  - name: Sync
    description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
    value: 1
enum/OCCE:
  bit_size: 1
  variants:
  - name: Disabled
    description: OCxRef is not affected by the ETRF signal.
    value: 0
  - name: Enabled
    description: OCxRef is cleared as soon as a High level is detected on ETRF signal.
    value: 1
enum/OCFE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Fast output disabled.
    value: 0
  - name: Enabled
    description: Fast output enabled.
    value: 1
enum/OCM:
  bit_size: 3
  variants:
  - name: Frozen
    description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs.
    value: 0
  - name: ActiveOnMatch
    description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register.
    value: 1
  - name: InactiveOnMatch
    description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register.
    value: 2
  - name: Toggle
    description: OCyREF toggles when TIMx_CNT=TIMx_CCRy.
    value: 3
  - name: ForceInactive
    description: OCyREF is forced low.
    value: 4
  - name: ForceActive
    description: OCyREF is forced high.
    value: 5
  - name: PwmMode1
    description: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active.
    value: 6
  - name: PwmMode2
    description: Inversely to PwmMode1.
    value: 7
enum/OCPE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately.
    value: 0
  - name: Enabled
    description: Preload register on CCRx enabled. Preload value is loaded into active register on each update event.
    value: 1
enum/OPM:
  bit_size: 1
  variants:
  - name: Disabled
    description: Counter is not stopped at update event.
    value: 0
  - name: Enabled
    description: Counter stops counting at the next update event (clearing the CEN bit).
    value: 1
enum/SMS:
  bit_size: 3
  variants:
  - name: Disabled
    description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
    value: 0
  - name: Encoder_Mode_1
    description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
    value: 1
  - name: Encoder_Mode_2
    description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
    value: 2
  - name: Encoder_Mode_3
    description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
    value: 3
  - name: Reset_Mode
    description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
    value: 4
  - name: Gated_Mode
    description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
    value: 5
  - name: Trigger_Mode
    description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
    value: 6
  - name: Ext_Clock_Mode
    description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
    value: 7
enum/TDE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Trigger DMA request disabled.
    value: 0
  - name: Enabled
    description: Trigger DMA request enabled.
    value: 1
enum/TG:
  bit_size: 1
  variants:
  - name: Trigger
    description: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
    value: 1
enum/TI1S:
  bit_size: 1
  variants:
  - name: Normal
    description: The TIMx_CH1 pin is connected to TI1 input.
    value: 0
  - name: XOR
    description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input.
    value: 1
enum/TIE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Trigger interrupt disabled.
    value: 0
  - name: Enabled
    description: Trigger interrupt enabled.
    value: 1
enum/TIF:
  bit_size: 1
  variants:
  - name: R_NoTrigger_W_Clear
    description: No trigger event occurred.
    value: 0
  - name: Trigger
    description: Trigger interrupt pending.
    value: 1
enum/TS:
  bit_size: 3
  variants:
  - name: ITR0
    description: Internal Trigger 0 (ITR0).
    value: 0
  - name: ITR1
    description: Internal Trigger 1 (ITR1).
    value: 1
  - name: ITR2
    description: Internal Trigger 2 (ITR2).
    value: 2
  - name: TI1F_ED
    description: TI1 Edge Detector (TI1F_ED).
    value: 4
  - name: TI1FP1
    description: Filtered Timer Input 1 (TI1FP1).
    value: 5
  - name: TI2FP2
    description: Filtered Timer Input 2 (TI2FP2).
    value: 6
  - name: ETRF
    description: External Trigger input (ETRF).
    value: 7
enum/UDE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Update DMA request disabled.
    value: 0
  - name: Enabled
    description: Update DMA request enabled.
    value: 1
enum/UDIS:
  bit_size: 1
  variants:
  - name: Enabled
    description: Update event enabled.
    value: 0
  - name: Disabled
    description: Update event disabled.
    value: 1
enum/UG:
  bit_size: 1
  variants:
  - name: Update
    description: Re-initializes the timer counter and generates an update of the registers.
    value: 1
enum/UIE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Update interrupt disabled.
    value: 0
  - name: Enabled
    description: Update interrupt enabled.
    value: 1
enum/UIF:
  bit_size: 1
  variants:
  - name: R_NoUpdateOccurred_W_Clear
    description: No update occurred.
    value: 0
  - name: UpdatePending
    description: Update interrupt pending.
    value: 1
enum/URS:
  bit_size: 1
  variants:
  - name: AnyEvent
    description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request.
    value: 0
  - name: CounterOnly
    description: Only counter overflow/underflow generates an update interrupt or DMA request.
    value: 1