block/DAC:
  description: Digital to analog converter.
  items:
  - name: CR
    description: Control register (DAC_CR).
    byte_offset: 0
    fieldset: CR
  - name: SWTRIGR
    description: DAC software trigger register (DAC_SWTRIGR).
    byte_offset: 4
    access: Write
    fieldset: SWTRIGR
  - name: DHR12R
    description: channel%s 12-bit right-aligned data holding register.
    array:
      len: 2
      stride: 12
    byte_offset: 8
    fieldset: DHR12R
  - name: DHR12L
    description: channel%s 12-bit left aligned data holding register.
    array:
      len: 2
      stride: 12
    byte_offset: 12
    fieldset: DHR12L
  - name: DHR8R
    description: channel%s 8-bit right aligned data holding register.
    array:
      len: 2
      stride: 12
    byte_offset: 16
    fieldset: DHR8R
  - name: DHR12RD
    description: Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved.
    byte_offset: 32
    fieldset: DHR12RD
  - name: DHR12LD
    description: DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved.
    byte_offset: 36
    fieldset: DHR12LD
  - name: DHR8RD
    description: DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved.
    byte_offset: 40
    fieldset: DHR8RD
  - name: DOR
    description: channel%s data output register.
    array:
      len: 2
      stride: 4
    byte_offset: 44
    access: Read
    fieldset: DOR
fieldset/CR:
  description: Control register (DAC_CR).
  fields:
  - name: EN
    description: DAC channel%s enable.
    bit_offset: 0
    bit_size: 1
    array:
      len: 2
      stride: 16
    enum: EN
  - name: BOFF
    description: DAC channel%s output buffer disable.
    bit_offset: 1
    bit_size: 1
    array:
      len: 2
      stride: 16
    enum: BOFF
  - name: TEN
    description: DAC channel%s trigger enable.
    bit_offset: 2
    bit_size: 1
    array:
      len: 2
      stride: 16
    enum: TEN
  - name: TSEL1
    description: DAC channel1 trigger selection.
    bit_offset: 3
    bit_size: 3
    enum: TSEL1
  - name: WAVE
    description: DAC channel%s noise/triangle wave generation enable.
    bit_offset: 6
    bit_size: 2
    array:
      len: 2
      stride: 16
    enum: WAVE
  - name: MAMP
    description: DAC channel%s mask/amplitude selector.
    bit_offset: 8
    bit_size: 4
    array:
      len: 2
      stride: 16
    enum: MAMP
  - name: DMAEN
    description: DAC channel%s DMA enable.
    bit_offset: 12
    bit_size: 1
    array:
      len: 2
      stride: 16
    enum: DMAEN
  - name: TSEL2
    description: DAC channel2 trigger selection.
    bit_offset: 19
    bit_size: 3
    enum: TSEL2
fieldset/DHR12L:
  description: channel%s 12-bit left aligned data holding register.
  fields:
  - name: DACCDHR
    description: DAC channel1 12-bit left-aligned data.
    bit_offset: 4
    bit_size: 12
fieldset/DHR12LD:
  description: DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved.
  fields:
  - name: DACCDHR
    description: DAC channel%s 12-bit left-aligned data.
    bit_offset: 4
    bit_size: 12
    array:
      len: 2
      stride: 16
fieldset/DHR12R:
  description: channel%s 12-bit right-aligned data holding register.
  fields:
  - name: DACCDHR
    description: DAC channel1 12-bit right-aligned data.
    bit_offset: 0
    bit_size: 12
fieldset/DHR12RD:
  description: Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved.
  fields:
  - name: DACCDHR
    description: DAC channel%s 12-bit right-aligned data.
    bit_offset: 0
    bit_size: 12
    array:
      len: 2
      stride: 16
fieldset/DHR8R:
  description: channel%s 8-bit right aligned data holding register.
  fields:
  - name: DACCDHR
    description: DAC channel1 8-bit right-aligned data.
    bit_offset: 0
    bit_size: 8
fieldset/DHR8RD:
  description: DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved.
  fields:
  - name: DACCDHR
    description: DAC channel%s 8-bit right-aligned data.
    bit_offset: 0
    bit_size: 8
    array:
      len: 2
      stride: 8
fieldset/DOR:
  description: channel%s data output register.
  fields:
  - name: DACCDOR
    description: DAC channel1 data output.
    bit_offset: 0
    bit_size: 12
fieldset/SWTRIGR:
  description: DAC software trigger register (DAC_SWTRIGR).
  fields:
  - name: SWTRIG
    description: DAC channel%s software trigger.
    bit_offset: 0
    bit_size: 1
    array:
      len: 2
      stride: 1
    enum: SWTRIG
enum/BOFF:
  bit_size: 1
  variants:
  - name: Enabled
    description: DAC channel X output buffer enabled.
    value: 0
  - name: Disabled
    description: DAC channel X output buffer disabled.
    value: 1
enum/DMAEN:
  bit_size: 1
  variants:
  - name: Disabled
    description: DAC channel X DMA mode disabled.
    value: 0
  - name: Enabled
    description: DAC channel X DMA mode enabled.
    value: 1
enum/EN:
  bit_size: 1
  variants:
  - name: Disabled
    description: DAC channel X disabled.
    value: 0
  - name: Enabled
    description: DAC channel X enabled.
    value: 1
enum/MAMP:
  bit_size: 4
  variants:
  - name: Amp1
    description: Unmask bit0 of LFSR/ triangle amplitude equal to 1.
    value: 0
  - name: Amp3
    description: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3.
    value: 1
  - name: Amp7
    description: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7.
    value: 2
  - name: Amp15
    description: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15.
    value: 3
  - name: Amp31
    description: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31.
    value: 4
  - name: Amp63
    description: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63.
    value: 5
  - name: Amp127
    description: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127.
    value: 6
  - name: Amp255
    description: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255.
    value: 7
  - name: Amp511
    description: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511.
    value: 8
  - name: Amp1023
    description: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023.
    value: 9
  - name: Amp2047
    description: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047.
    value: 10
enum/SWTRIG:
  bit_size: 1
  variants:
  - name: Disabled
    description: DAC channel X software trigger disabled.
    value: 0
  - name: Enabled
    description: DAC channel X software trigger enabled.
    value: 1
enum/TEN:
  bit_size: 1
  variants:
  - name: Disabled
    description: DAC channel X trigger disabled.
    value: 0
  - name: Enabled
    description: DAC channel X trigger enabled.
    value: 1
enum/TSEL1:
  bit_size: 3
  variants:
  - name: Tim6Trgo
    description: Timer 6 TRGO event.
    value: 0
  - name: Tim8Trgo
    description: Timer 8 TRGO event.
    value: 1
  - name: Tim7Trgo
    description: Timer 7 TRGO event.
    value: 2
  - name: Tim5Trgo
    description: Timer 5 TRGO event.
    value: 3
  - name: Tim2Trgo
    description: Timer 2 TRGO event.
    value: 4
  - name: Tim4Trgo
    description: Timer 4 TRGO event.
    value: 5
  - name: Exti9
    description: EXTI line 9.
    value: 6
  - name: Swtrig
    description: Software trigger.
    value: 7
enum/TSEL2:
  bit_size: 3
  variants:
  - name: Tim6Trgo
    description: Timer 6 TRGO event.
    value: 0
  - name: Tim8Trgo
    description: Timer 8 TRGO event.
    value: 1
  - name: Tim7Trgo
    description: Timer 7 TRGO event.
    value: 2
  - name: Tim5Trgo
    description: Timer 5 TRGO event.
    value: 3
  - name: Tim2Trgo
    description: Timer 2 TRGO event.
    value: 4
  - name: Tim4Trgo
    description: Timer 4 TRGO event.
    value: 5
  - name: Exti9
    description: EXTI line 9.
    value: 6
  - name: Swtrig
    description: Software trigger.
    value: 7
enum/WAVE:
  bit_size: 2
  variants:
  - name: Disabled
    description: Wave generation disabled.
    value: 0
  - name: Noise
    description: Noise wave generation enabled.
    value: 1