block/FLASH: description: FLASH register block. items: - name: ACR description: FLASH access control register. byte_offset: 0 fieldset: ACR - name: KEYR description: FLASH key register. byte_offset: 8 access: Write fieldset: KEYR - name: OPTKEYR description: FLASH option key register. byte_offset: 12 access: Write fieldset: OPTKEYR - name: SR description: FLASH status register. byte_offset: 16 fieldset: SR - name: CR description: FLASH control register. byte_offset: 20 fieldset: CR - name: OPTR description: FLASH option register. byte_offset: 32 fieldset: OPTR - name: PCROP1ASR description: FLASH PCROP area A start address register. byte_offset: 36 fieldset: PCROP1ASR - name: PCROP1AER description: FLASH PCROP area A end address register. byte_offset: 40 fieldset: PCROP1AER - name: WRP1AR description: FLASH WRP area A address register. byte_offset: 44 fieldset: WRP1AR - name: WRP1BR description: FLASH WRP area B address register. byte_offset: 48 fieldset: WRP1BR - name: PCROP1BSR description: FLASH PCROP area B start address register. byte_offset: 52 fieldset: PCROP1BSR - name: PCROP1BER description: FLASH PCROP area B end address register. byte_offset: 56 fieldset: PCROP1BER - name: SECR description: FLASH security register. byte_offset: 128 fieldset: SECR fieldset/ACR: description: FLASH access control register. fields: - name: LATENCY description: 'Flash memory access latency The value in this bitfield represents the number of CPU wait states when accessing the flash memory. Other: Reserved A new write into the bitfield becomes effective when it returns the same value upon read.' bit_offset: 0 bit_size: 3 - name: PRFTEN description: CPU Prefetch enable. bit_offset: 8 bit_size: 1 - name: ICEN description: CPU Instruction cache enable. bit_offset: 9 bit_size: 1 - name: ICRST description: CPU Instruction cache reset This bit can be written only when the instruction cache is disabled. bit_offset: 11 bit_size: 1 - name: EMPTY description: Main flash memory area empty This bit indicates whether the first location of the Main flash memory area was read as erased or as programmed during OBL. It is not affected by the system reset. Software may need to change this bit value after a flash memory program or erase operation. The bit can be set and reset by software. bit_offset: 16 bit_size: 1 - name: DBG_SWEN description: Debug access software enable Software may use this bit to enable/disable the debugger read access. bit_offset: 18 bit_size: 1 fieldset/CR: description: FLASH control register. fields: - name: PG description: Flash memory programming enable. bit_offset: 0 bit_size: 1 - name: PER description: Page erase enable. bit_offset: 1 bit_size: 1 - name: MER1 description: Mass erase When set, this bit triggers the mass erase, that is, all user pages. bit_offset: 2 bit_size: 1 - name: PNB description: 'Page number selection These bits select the page to erase: ... Note: Values corresponding to addresses outside the Main memory are not allowed. See Table 6 and Table 7.' bit_offset: 3 bit_size: 4 - name: STRT description: Start erase operation This bit triggers an erase operation when set. This bit is possible to set only by software and to clear only by hardware. The hardware clears it when one of BSY1 and BSY2 flags in the FLASH_SR register transits to zero. bit_offset: 16 bit_size: 1 - name: OPTSTRT description: Start of modification of option bytes This bit triggers an options operation when set. This bit is set only by software, and is cleared when the BSY1 bit is cleared in FLASH_SR. bit_offset: 17 bit_size: 1 - name: FSTPG description: Fast programming enable. bit_offset: 18 bit_size: 1 - name: EOPIE description: End-of-operation interrupt enable This bit enables the interrupt generation upon setting the EOP flag in the FLASH_SR register. bit_offset: 24 bit_size: 1 - name: ERRIE description: Error interrupt enable This bit enables the interrupt generation upon setting the OPERR flag in the FLASH_SR register. bit_offset: 25 bit_size: 1 - name: RDERRIE description: PCROP read error interrupt enable This bit enables the interrupt generation upon setting the RDERR flag in the FLASH_SR register. bit_offset: 26 bit_size: 1 - name: OBL_LAUNCH description: Option byte load launch When set, this bit triggers the load of option bytes into option registers. It is automatically cleared upon the completion of the load. The high state of the bit indicates pending option byte load. The bit cannot be cleared by software. It cannot be written as long as OPTLOCK is set. bit_offset: 27 bit_size: 1 - name: SEC_PROT description: Securable memory area protection enable This bit enables the protection on securable area, provided that a non-null securable memory area size (SEC_SIZE[4:0]) is defined in option bytes. This bit is possible to set only by software and to clear only through a system reset. bit_offset: 28 bit_size: 1 - name: OPTLOCK description: Options Lock This bit is set only. When set, all bits concerning user option in FLASH_CR register and so option page are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit must be cleared before doing the unlock sequence for OPTLOCK bit. In case of an unsuccessful unlock operation, this bit remains set until the next reset. bit_offset: 30 bit_size: 1 - name: LOCK description: FLASH_CR Lock This bit is set only. When set, the FLASH_CR register is locked. It is cleared by hardware after detecting the unlock sequence. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. bit_offset: 31 bit_size: 1 fieldset/KEYR: description: FLASH key register. fields: - name: KEY description: 'FLASH key The following values must be written consecutively to unlock the FLASH control register (FLASH_CR), thus enabling programming/erasing operations: KEY1: 0x4567 0123 KEY2: 0xCDEF 89AB.' bit_offset: 0 bit_size: 32 fieldset/OPTKEYR: description: FLASH option key register. fields: - name: OPTKEY description: 'Option byte key The following values must be written consecutively to unlock the flash memory option registers, enabling option byte programming/erasing operations: KEY1: 0x0819 2A3B KEY2: 0x4C5D 6E7F.' bit_offset: 0 bit_size: 32 fieldset/OPTR: description: FLASH option register. fields: - name: RDP description: 'Read protection level Other: Level 1, memories read protection active.' bit_offset: 0 bit_size: 8 - name: BOR_EN description: Brown out reset enable. bit_offset: 8 bit_size: 1 - name: BORR_LEV description: BOR threshold at falling VDD supply Falling VDD crossings this threshold activates the reset signal. bit_offset: 9 bit_size: 2 - name: BORF_LEV description: BOR threshold at falling VDD supply Falling VDD crossings this threshold activates the reset signal. bit_offset: 11 bit_size: 2 - name: NRST_STOP description: None. bit_offset: 13 bit_size: 1 - name: NRST_STDBY description: None. bit_offset: 14 bit_size: 1 - name: NRST_SHDW description: None. bit_offset: 15 bit_size: 1 - name: IWDG_SW description: None. bit_offset: 16 bit_size: 1 - name: IWDG_STOP description: Independent watchdog counter freeze in Stop mode. bit_offset: 17 bit_size: 1 - name: IWGD_STDBY description: None. bit_offset: 18 bit_size: 1 - name: WWDG_SW description: Window watchdog selection. bit_offset: 19 bit_size: 1 - name: HSE_NOT_REMAPPED description: 'HSE remapping enable/disable When cleared, the bit remaps the HSE clock source from PF0-OSC_IN/PF1-OSC_OUT pins to PC14-OSCX_IN/PC15-OSCX_OUT. Thus PC14-OSCX_IN/PC15-OSCX_OUT are shared by both LSE and HSE and the two clock sources cannot be use simultaneously. On packages with less than 48 pins, the remapping is always enabled (PF0-OSC_IN/PF1-OSC_OUT are not available), regardless of this bit. As all STM32C011xx packages have less than 48 pins, this bit is only applicable to STM32C031xx. Note: On 48 pins packages, when HSE_NOT_REMAPPED is reset, HSE cannot be used in bypass mode. Refer to product errata sheet for more details.' bit_offset: 21 bit_size: 1 - name: RAM_PARITY_CHECK description: SRAM parity check control enable/disable. bit_offset: 22 bit_size: 1 - name: SECURE_MUXING_EN description: Multiple-bonding security The bit allows enabling automatic I/O configuration to prevent conflicts on I/Os connected (bonded) onto the same pin. If the software sets one of the I/Os connected to the same pin as active by configuring the SYSCFG_CFGR3 register, enabling this bit automatically forces the other I/Os in digital input mode, regardless of their software configuration. When the bit is disabled, the SYSCFG_CFGR3 register setting is ignored, all GPIOs linked to a given pin are active and can be set in the mode specified by the corresponding GPIOx_MODER register. The user software must ensure that there is no conflict between GPIOs. bit_offset: 23 bit_size: 1 - name: NBOOT_SEL description: BOOT0 signal source selection This option bit defines the source of the BOOT0 signal. bit_offset: 24 bit_size: 1 - name: NBOOT1 description: 'Boot configuration Together with the BOOT0 pin or option bit nBOOT0 (depending on nBOOT_SEL option bit configuration), this bit selects boot mode from the Main flash memory, SRAM or the System memory. Refer to Section 3: Boot configuration.' bit_offset: 25 bit_size: 1 - name: NBOOT0 description: nBOOT0 option bit. bit_offset: 26 bit_size: 1 - name: NRST_MODE description: NRST pin configuration. bit_offset: 27 bit_size: 2 - name: IRHEN description: Internal reset holder enable bit. bit_offset: 29 bit_size: 1 fieldset/PCROP1AER: description: FLASH PCROP area A end address register. fields: - name: PCROP1A_END description: 'PCROP1A area end offset Contains the offset of the last subpage of the PCROP1A area. Note: The number of effective bits depends on the size of the flash memory in the device.' bit_offset: 0 bit_size: 9 - name: PCROP_RDP description: 'PCROP area erase upon RDP level regression This bit determines whether the PCROP area (and the totality of the PCROP area boundary pages) is erased by the mass erase triggered by the RDP level regression from Level 1 to Level 0: The software can only set this bit. It is automatically reset upon mass erase following the RDP regression from Level 1 to Level 0.' bit_offset: 31 bit_size: 1 fieldset/PCROP1ASR: description: FLASH PCROP area A start address register. fields: - name: PCROP1A_STRT description: 'PCROP1A area start offset Contains the offset of the first subpage of the PCROP1A area. Note: The number of effective bits depends on the size of the flash memory in the device.' bit_offset: 0 bit_size: 9 fieldset/PCROP1BER: description: FLASH PCROP area B end address register. fields: - name: PCROP1B_END description: 'PCROP1B area end offset Contains the offset of the last subpage of the PCROP1B area. Note: The number of effective bits depends on the size of the flash memory in the device.' bit_offset: 0 bit_size: 9 fieldset/PCROP1BSR: description: FLASH PCROP area B start address register. fields: - name: PCROP1B_STRT description: 'PCROP1B area start offset Contains the offset of the first subpage of the PCROP1B area. Note: The number of effective bits depends on the size of the flash memory in the device.' bit_offset: 0 bit_size: 9 fieldset/SECR: description: FLASH security register. fields: - name: SEC_SIZE description: 'Securable memory area size Contains the number of securable flash memory pages. Note: The number of effective bits depends on the size of the flash memory in the device.' bit_offset: 0 bit_size: 7 - name: BOOT_LOCK description: used to force boot from user area If the bit is set in association with RDP level 1, the debug capabilities are disabled, except in the case of a bad OBL (mismatch). bit_offset: 16 bit_size: 1 fieldset/SR: description: FLASH status register. fields: - name: EOP description: End of operation Set by hardware when one or more flash memory operation (programming / erase) has been completed successfully. This bit is set only if the end of operation interrupts are enabled (EOPIE=1). Cleared by writing 1. bit_offset: 0 bit_size: 1 - name: OPERR description: Operation error Set by hardware when a flash memory operation (program / erase) completes unsuccessfully. This bit is set only if error interrupts are enabled (ERRIE=1). Cleared by writing 1. bit_offset: 1 bit_size: 1 - name: PROGERR description: Programming error Set by hardware when a double-word address to be programmed contains a value different from '0xFFFF FFFF' before programming, except if the data to write is '0x0000 0000'. Cleared by writing 1. bit_offset: 3 bit_size: 1 - name: WRPERR description: Write protection error Set by hardware when an address to be erased/programmed belongs to a write-protected part (by WRP, PCROP or RDP Level 1) of the flash memory. Cleared by writing 1. bit_offset: 4 bit_size: 1 - name: PGAERR description: Programming alignment error Set by hardware when the data to program cannot be contained in the same double word (64-bit) flash memory in case of standard programming, or if there is a change of page during fast programming. Cleared by writing 1. bit_offset: 5 bit_size: 1 - name: SIZERR description: 'Size error Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access). Cleared by writing 1.' bit_offset: 6 bit_size: 1 - name: PGSERR description: Programming sequence error Set by hardware when a write access to the flash memory is performed by the code while PG or FSTPG have not been set previously. Set also by hardware when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous programming error. Cleared by writing 1. bit_offset: 7 bit_size: 1 - name: MISSERR description: Fast programming data miss error In Fast programming mode, 16 double words (128 bytes) must be sent to flash memory successively, and the new data must be sent to the logic control before the current data is fully programmed. MISSERR is set by hardware when the new data is not present in time. Cleared by writing 1. bit_offset: 8 bit_size: 1 - name: FASTERR description: Fast programming error Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted due to an error (alignment, size, write protection or data miss). The corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time. Cleared by writing 1. bit_offset: 9 bit_size: 1 - name: RDERR description: PCROP read error Set by hardware when an address to be read belongs to a read protected area of the flash memory (PCROP protection). An interrupt is generated if RDERRIE is set in FLASH_CR. Cleared by writing 1. bit_offset: 14 bit_size: 1 - name: OPTVERR description: Option and Engineering bits loading validity error. bit_offset: 15 bit_size: 1 - name: BSY1 description: Busy This flag indicates that a flash memory operation requested by FLASH control register (FLASH_CR) is in progress. This bit is set at the beginning of the flash memory operation, and cleared when the operation finishes or when an error occurs. bit_offset: 16 bit_size: 1 - name: CFGBSY description: 'Programming or erase configuration busy. This flag is set and reset by hardware. For flash program operation, it is set when the first word is sent, and cleared after the second word is sent when the operation completes or ends with an error. For flash erase operation, it is set when setting the STRT bit of the FLASH_CR register and cleared when the operation completes or ends with an error. When set, a programming or erase operation is ongoing and the corresponding settings in the FLASH control register (FLASH_CR) are used (busy) and cannot be changed. Any other flash operation launch must be postponed. When cleared, the programming and erase settings in the FLASH control register (FLASH_CR) can be modified. Note: The CFGBSY bit is also set when attempting to write locked flash memory (with the first byte sent). When the CFGBSY bit is set, writing into the FLASH_CR register causes HardFault.To clear the CFGBSY bit, send a double word to the flash memory and wait until the access is finished (otherwise the CFGBSY bit remains set).' bit_offset: 18 bit_size: 1 fieldset/WRP1AR: description: FLASH WRP area A address register. fields: - name: WRP1A_STRT description: 'WRP area A start offset This bitfield contains the offset of the first page of the WRP area A. Note: The number of effective bits depends on the size of the flash memory in the device.' bit_offset: 0 bit_size: 7 - name: WRP1A_END description: 'WRP area A end offset This bitfield contains the offset of the last page of the WRP area A. Note: The number of effective bits depends on the size of the flash memory in the device.' bit_offset: 16 bit_size: 7 fieldset/WRP1BR: description: FLASH WRP area B address register. fields: - name: WRP1B_STRT description: 'WRP area B start offset This bitfield contains the offset of the first page of the WRP area B. Note: The number of effective bits depends on the size of the flash memory in the device.' bit_offset: 0 bit_size: 7 - name: WRP1B_END description: 'WRP area B end offset This bitfield contains the offset of the last page of the WRP area B. Note: The number of effective bits depends on the size of the flash memory in the device.' bit_offset: 16 bit_size: 7