block/XCVR_MISC:
  description: XCVR_MISC.
  items:
  - name: XCVR_CTRL
    description: TRANSCEIVER CONTROL.
    byte_offset: 0
    fieldset: XCVR_CTRL
  - name: XCVR_STATUS
    description: TRANSCEIVER STATUS.
    byte_offset: 4
    fieldset: XCVR_STATUS
  - name: BLE_ARB_CTRL
    description: BLE ARBITRATION CONTROL.
    byte_offset: 8
    fieldset: BLE_ARB_CTRL
  - name: OVERWRITE_VER
    description: OVERWRITE VERSION.
    byte_offset: 16
    fieldset: OVERWRITE_VER
  - name: DMA_CTRL
    description: TRANSCEIVER DMA CONTROL.
    byte_offset: 20
    fieldset: DMA_CTRL
  - name: DMA_DATA
    description: TRANSCEIVER DMA DATA.
    byte_offset: 24
    access: Read
    fieldset: DMA_DATA
  - name: DTEST_CTRL
    description: DIGITAL TEST MUX CONTROL.
    byte_offset: 28
    fieldset: DTEST_CTRL
  - name: PACKET_RAM_CTRL
    description: PACKET RAM CONTROL.
    byte_offset: 32
    fieldset: PACKET_RAM_CTRL
  - name: FAD_CTRL
    description: FAD CONTROL.
    byte_offset: 36
    fieldset: FAD_CTRL
  - name: LPPS_CTRL
    description: LOW POWER PREAMBLE SEARCH CONTROL.
    byte_offset: 40
    fieldset: LPPS_CTRL
  - name: RF_NOT_ALLOWED_CTRL
    description: WIFI COEXISTENCE CONTROL.
    byte_offset: 44
    fieldset: RF_NOT_ALLOWED_CTRL
  - name: CRCW_CFG
    description: CRC/WHITENER CONTROL.
    byte_offset: 48
    fieldset: CRCW_CFG
  - name: CRC_EC_MASK
    description: CRC ERROR CORRECTION MASK.
    byte_offset: 52
    access: Read
    fieldset: CRC_EC_MASK
  - name: CRC_RES_OUT
    description: CRC RESULT.
    byte_offset: 56
    access: Read
    fieldset: CRC_RES_OUT
fieldset/BLE_ARB_CTRL:
  description: BLE ARBITRATION CONTROL.
  fields:
  - name: BLE_RELINQUISH
    description: BLE Relinquish Control.
    bit_offset: 0
    bit_size: 1
  - name: XCVR_BUSY
    description: Transceiver Busy Status Bit.
    bit_offset: 1
    bit_size: 1
    enum: XCVR_BUSY
fieldset/CRCW_CFG:
  description: CRC/WHITENER CONTROL.
  fields:
  - name: CRCW_EN
    description: CRC calculation enable.
    bit_offset: 0
    bit_size: 1
  - name: CRC_ZERO
    description: CRC zero.
    bit_offset: 1
    bit_size: 1
  - name: CRC_EARLY_FAIL
    description: CRC error correction fail.
    bit_offset: 2
    bit_size: 1
  - name: CRC_RES_OUT_VLD
    description: CRC result output valid.
    bit_offset: 3
    bit_size: 1
  - name: CRC_EC_OFFSET
    description: CRC error correction offset.
    bit_offset: 16
    bit_size: 11
  - name: CRC_EC_DONE
    description: CRC error correction done.
    bit_offset: 28
    bit_size: 1
  - name: CRC_EC_FAIL
    description: CRC error correction fail.
    bit_offset: 29
    bit_size: 1
fieldset/CRC_EC_MASK:
  description: CRC ERROR CORRECTION MASK.
  fields:
  - name: CRC_EC_MASK
    description: CRC error correction mask.
    bit_offset: 0
    bit_size: 32
fieldset/CRC_RES_OUT:
  description: CRC RESULT.
  fields:
  - name: CRC_RES_OUT
    description: CRC result output.
    bit_offset: 0
    bit_size: 32
fieldset/DMA_CTRL:
  description: TRANSCEIVER DMA CONTROL.
  fields:
  - name: DMA_PAGE
    description: Transceiver DMA Page Selector.
    bit_offset: 0
    bit_size: 4
    enum: DMA_PAGE
  - name: SINGLE_REQ_MODE
    description: DMA Single Request Mode.
    bit_offset: 4
    bit_size: 1
    enum: SINGLE_REQ_MODE
  - name: BYPASS_DMA_SYNC
    description: Bypass External DMA Synchronization.
    bit_offset: 5
    bit_size: 1
    enum: BYPASS_DMA_SYNC
  - name: DMA_TRIGGERRED
    description: DMA TRIGGERRED.
    bit_offset: 6
    bit_size: 1
  - name: DMA_TIMED_OUT
    description: DMA Transfer Timed Out.
    bit_offset: 7
    bit_size: 1
    enum: DMA_TIMED_OUT
  - name: DMA_TIMEOUT
    description: DMA Timeout.
    bit_offset: 8
    bit_size: 4
fieldset/DMA_DATA:
  description: TRANSCEIVER DMA DATA.
  fields:
  - name: DMA_DATA
    description: DMA Data Register.
    bit_offset: 0
    bit_size: 32
fieldset/DTEST_CTRL:
  description: DIGITAL TEST MUX CONTROL.
  fields:
  - name: DTEST_PAGE
    description: DTEST Page Selector.
    bit_offset: 0
    bit_size: 6
  - name: DTEST_EN
    description: DTEST Enable.
    bit_offset: 7
    bit_size: 1
    enum: DTEST_EN
  - name: GPIO0_OVLAY_PIN
    description: GPIO 0 Overlay Pin.
    bit_offset: 8
    bit_size: 4
  - name: GPIO1_OVLAY_PIN
    description: GPIO 1 Overlay Pin.
    bit_offset: 12
    bit_size: 4
  - name: TSM_GPIO_OVLAY
    description: TSM GPIO Overlay Pin Control.
    bit_offset: 16
    bit_size: 2
    enum: TSM_GPIO_OVLAY
  - name: DTEST_SHFT
    description: DTEST Shift Control.
    bit_offset: 24
    bit_size: 3
  - name: RAW_MODE_I
    description: DTEST Raw Mode Enable for I Channel.
    bit_offset: 28
    bit_size: 1
  - name: RAW_MODE_Q
    description: DTEST Raw Mode Enable for Q Channel.
    bit_offset: 29
    bit_size: 1
fieldset/FAD_CTRL:
  description: FAD CONTROL.
  fields:
  - name: FAD_EN
    description: Fast Antenna Diversity Enable.
    bit_offset: 0
    bit_size: 1
    enum: FAD_EN
  - name: ANTX
    description: Antenna Selection State.
    bit_offset: 1
    bit_size: 1
  - name: ANTX_EN
    description: FAD Antenna Controls Enable.
    bit_offset: 4
    bit_size: 2
    enum: ANTX_EN
  - name: ANTX_HZ
    description: FAD PAD Tristate Control.
    bit_offset: 6
    bit_size: 1
    enum: ANTX_HZ
  - name: ANTX_CTRLMODE
    description: Antenna Diversity Control Mode.
    bit_offset: 7
    bit_size: 1
  - name: ANTX_POL
    description: FAD Antenna Controls Polarity.
    bit_offset: 8
    bit_size: 4
  - name: FAD_NOT_GPIO
    description: FAD versus GPIO Mode Selector.
    bit_offset: 12
    bit_size: 4
fieldset/LPPS_CTRL:
  description: LOW POWER PREAMBLE SEARCH CONTROL.
  fields:
  - name: LPPS_ENABLE
    description: LPPS_ENABLE.
    bit_offset: 0
    bit_size: 1
  - name: LPPS_TZA_ALLOW
    description: LPPS_TZA_ALLOW.
    bit_offset: 1
    bit_size: 1
  - name: LPPS_BBA_ALLOW
    description: LPPS_BBA_ALLOW.
    bit_offset: 2
    bit_size: 1
  - name: LPPS_ADC_ALLOW
    description: LPPS_ADC_ALLOW.
    bit_offset: 3
    bit_size: 1
  - name: LPPS_DCOC_ALLOW
    description: LPPS_DCOC_ALLOW.
    bit_offset: 4
    bit_size: 1
  - name: LPPS_PDET_ALLOW
    description: LPPS_PDET_ALLOW.
    bit_offset: 5
    bit_size: 1
  - name: LPPS_SY_LO_ALLOW
    description: LPPS_SY_LO_ALLOW.
    bit_offset: 6
    bit_size: 1
  - name: LPPS_SY_LO_BUF_ALLOW
    description: LPPS_SY_LO_BUF_ALLOW.
    bit_offset: 7
    bit_size: 1
  - name: LPPS_RX_DIG_ALLOW
    description: LPPS_RX_DIG_ALLOW.
    bit_offset: 8
    bit_size: 1
  - name: LPPS_DCOC_DIG_ALLOW
    description: LPPS_DCOC_DIG_ALLOW.
    bit_offset: 9
    bit_size: 1
  - name: LPPS_START_RX
    description: LPPS Fast TSM RX Warmup "Jump-from" Point.
    bit_offset: 16
    bit_size: 8
  - name: LPPS_DEST_RX
    description: LPPS Fast TSM RX Warmup "Jump-to" Point.
    bit_offset: 24
    bit_size: 8
fieldset/OVERWRITE_VER:
  description: OVERWRITE VERSION.
  fields:
  - name: OVERWRITE_VER
    description: Overwrite Version Number.
    bit_offset: 0
    bit_size: 8
fieldset/PACKET_RAM_CTRL:
  description: PACKET RAM CONTROL.
  fields:
  - name: DBG_PAGE
    description: Packet RAM Debug Page Selector.
    bit_offset: 0
    bit_size: 4
    enum: DBG_PAGE
  - name: PB_PROTECT
    description: Packet Buffer Protect.
    bit_offset: 4
    bit_size: 1
    enum: PB_PROTECT
  - name: XCVR_RAM_ALLOW
    description: Allow Packet RAM Transceiver Access.
    bit_offset: 5
    bit_size: 1
    enum: XCVR_RAM_ALLOW
  - name: ALL_PROTOCOLS_ALLOW
    description: Allow IPS bus access to Packet RAM for any protocol at any time.
    bit_offset: 6
    bit_size: 1
    enum: ALL_PROTOCOLS_ALLOW
  - name: DBG_TRIGGERRED
    description: DBG_TRIGGERRED.
    bit_offset: 7
    bit_size: 1
  - name: DBG_RAM_FULL
    description: DBG_RAM_FULL[1:0].
    bit_offset: 8
    bit_size: 2
    enum: DBG_RAM_FULL
  - name: RAM0_CLK_ON_OVRD_EN
    description: Override control for RAM0 Clock Gate Enable.
    bit_offset: 10
    bit_size: 1
    enum: RAM0_CLK_ON_OVRD_EN
  - name: RAM0_CLK_ON_OVRD
    description: Override value for RAM0 Clock Gate Enable.
    bit_offset: 11
    bit_size: 1
  - name: RAM1_CLK_ON_OVRD_EN
    description: Override control for RAM1 Clock Gate Enable.
    bit_offset: 12
    bit_size: 1
    enum: RAM1_CLK_ON_OVRD_EN
  - name: RAM1_CLK_ON_OVRD
    description: Override value for RAM1 Clock Gate Enable.
    bit_offset: 13
    bit_size: 1
  - name: RAM0_CE_ON_OVRD_EN
    description: Override control for RAM0 CE (Chip Enable).
    bit_offset: 14
    bit_size: 1
    enum: RAM0_CE_ON_OVRD_EN
  - name: RAM0_CE_ON_OVRD
    description: Override value for RAM0 CE (Chip Enable).
    bit_offset: 15
    bit_size: 1
  - name: RAM1_CE_ON_OVRD_EN
    description: Override control for RAM1 CE (Chip Enable).
    bit_offset: 16
    bit_size: 1
    enum: RAM1_CE_ON_OVRD_EN
  - name: RAM1_CE_ON_OVRD
    description: Override value for RAM1 CE (Chip Enable).
    bit_offset: 17
    bit_size: 1
fieldset/RF_NOT_ALLOWED_CTRL:
  description: WIFI COEXISTENCE CONTROL.
  fields:
  - name: RF_NOT_ALLOWED_NO_TX
    description: RF_NOT_ALLOWED_NO_TX.
    bit_offset: 0
    bit_size: 1
    enum: RF_NOT_ALLOWED_NO_TX
  - name: RF_NOT_ALLOWED_NO_RX
    description: RF_NOT_ALLOWED_NO_RX.
    bit_offset: 1
    bit_size: 1
    enum: RF_NOT_ALLOWED_NO_RX
  - name: RF_NOT_ALLOWED_ASSERTED
    description: RF_NOT_ALLOWED_ASSERTED.
    bit_offset: 2
    bit_size: 1
    enum: RF_NOT_ALLOWED_ASSERTED
  - name: RF_NOT_ALLOWED_TX_ABORT
    description: RF_NOT_ALLOWED_TX_ABORT.
    bit_offset: 3
    bit_size: 1
    enum: RF_NOT_ALLOWED_TX_ABORT
  - name: RF_NOT_ALLOWED_RX_ABORT
    description: RF_NOT_ALLOWED_RX_ABORT.
    bit_offset: 4
    bit_size: 1
    enum: RF_NOT_ALLOWED_RX_ABORT
  - name: RF_NOT_ALLOWED
    description: RF_NOT_ALLOWED.
    bit_offset: 5
    bit_size: 1
fieldset/XCVR_CTRL:
  description: TRANSCEIVER CONTROL.
  fields:
  - name: PROTOCOL
    description: Radio Protocol Selection.
    bit_offset: 0
    bit_size: 4
    enum: PROTOCOL
  - name: TGT_PWR_SRC
    description: Target Power Source.
    bit_offset: 4
    bit_size: 3
  - name: REF_CLK_FREQ
    description: Radio Reference Clock Frequency.
    bit_offset: 8
    bit_size: 2
    enum: REF_CLK_FREQ
  - name: SOC_RF_OSC_CLK_GATE_EN
    description: SOC_RF_OSC_CLK_GATE_EN.
    bit_offset: 11
    bit_size: 1
  - name: DEMOD_SEL
    description: Demodulator Selector.
    bit_offset: 12
    bit_size: 2
    enum: DEMOD_SEL
  - name: RADIO0_IRQ_SEL
    description: RADIO0_IRQ_SEL.
    bit_offset: 16
    bit_size: 3
    enum: RADIO0_IRQ_SEL
  - name: RADIO1_IRQ_SEL
    description: RADIO1_IRQ_SEL.
    bit_offset: 20
    bit_size: 3
    enum: RADIO1_IRQ_SEL
fieldset/XCVR_STATUS:
  description: TRANSCEIVER STATUS.
  fields:
  - name: TSM_COUNT
    description: TSM_COUNT.
    bit_offset: 0
    bit_size: 8
  - name: PLL_SEQ_STATE
    description: PLL Sequence State.
    bit_offset: 8
    bit_size: 4
    enum: PLL_SEQ_STATE
  - name: RX_MODE
    description: Receive Mode.
    bit_offset: 12
    bit_size: 1
  - name: TX_MODE
    description: Transmit Mode.
    bit_offset: 13
    bit_size: 1
  - name: BTLE_SYSCLK_REQ
    description: BTLE System Clock Request.
    bit_offset: 16
    bit_size: 1
  - name: RIF_LL_ACTIVE
    description: Link Layer Active Indication.
    bit_offset: 17
    bit_size: 1
  - name: XTAL_READY
    description: RF Osciallator Xtal Ready.
    bit_offset: 18
    bit_size: 1
    enum: XTAL_READY
  - name: SOC_USING_RF_OSC_CLK
    description: SOC Using RF Clock Indication.
    bit_offset: 19
    bit_size: 1
  - name: TSM_IRQ0
    description: 'TSM Interrupt #0.'
    bit_offset: 24
    bit_size: 1
    enum: TSM_IRQ0
  - name: TSM_IRQ1
    description: 'TSM Interrupt #1.'
    bit_offset: 25
    bit_size: 1
    enum: TSM_IRQ1
enum/ALL_PROTOCOLS_ALLOW:
  bit_size: 1
  variants:
  - name: '0'
    description: IPS bus access to Packet RAM is restricted to the protocol engine currently selected by XCVR_CTRL[PROTOCOL].
    value: 0
  - name: '1'
    description: All IPS bus access to Packet RAM permitted, regardless of XCVR_CTRL[PROTOCOL] setting.
    value: 1
enum/ANTX_EN:
  bit_size: 2
  variants:
  - name: '00'
    description: all disabled (held low).
    value: 0
  - name: '01'
    description: only RX/TX_SWITCH enabled.
    value: 1
  - name: '10'
    description: only ANT_A/B enabled.
    value: 2
  - name: '11'
    description: all enabled.
    value: 3
enum/ANTX_HZ:
  bit_size: 1
  variants:
  - name: '0'
    description: ANT_A, ANT_B, RX_SWITCH and TX_SWITCH are actively driven outputs.
    value: 0
  - name: '1'
    description: Antenna controls high impedance- Set ANT_A, ANT_B, RX_SWITCH and TX_SWITCH in high impedance.
    value: 1
enum/BYPASS_DMA_SYNC:
  bit_size: 1
  variants:
  - name: '0'
    description: Don't Bypass External Synchronization. Use this setting if SINGLE_REQ_MODE=1.
    value: 0
  - name: '1'
    description: Bypass External Synchronization. This setting is mandatory if SINGLE_REQ_MODE=0.
    value: 1
enum/DBG_PAGE:
  bit_size: 4
  variants:
  - name: '0000'
    description: Packet RAM Debug Mode Idle.
    value: 0
  - name: '0001'
    description: RX_DIG I and Q.
    value: 1
  - name: '0100'
    description: RAW ADC I and Q.
    value: 4
  - name: '0111'
    description: DC Estimator I and Q.
    value: 7
  - name: '1010'
    description: RX_DIG Phase Output.
    value: 10
  - name: '1011'
    description: Demodulator Hard Decision.
    value: 11
  - name: '1100'
    description: Demodulator Soft Decision.
    value: 12
  - name: '1101'
    description: Demodulator Data Output.
    value: 13
  - name: '1110'
    description: Demodulator CFO Phase Output.
    value: 14
enum/DBG_RAM_FULL:
  bit_size: 2
  variants:
  - name: '00'
    description: Neither Packet RAM0 nor RAM1 is full.
    value: 0
enum/DEMOD_SEL:
  bit_size: 2
  variants:
  - name: '00'
    description: No demodulator selected.
    value: 0
  - name: '01'
    description: Use Freescale Constant Envelope demodulator.
    value: 1
  - name: '10'
    description: Use Legacy 802.15.4 demodulator.
    value: 2
enum/DMA_PAGE:
  bit_size: 4
  variants:
  - name: '0000'
    description: DMA Idle.
    value: 0
  - name: '0001'
    description: RX_DIG I and Q.
    value: 1
  - name: '0010'
    description: RX_DIG I Only.
    value: 2
  - name: '0011'
    description: RX_DIG Q Only.
    value: 3
  - name: '0100'
    description: RAW ADC I and Q.
    value: 4
  - name: '0101'
    description: RAW ADC I Only.
    value: 5
  - name: '0110'
    description: RAW ADC Q only.
    value: 6
  - name: '0111'
    description: DC Estimator I and Q.
    value: 7
  - name: '1000'
    description: DC Estimator I Only.
    value: 8
  - name: '1001'
    description: DC Estimator Q only.
    value: 9
  - name: '1010'
    description: RX_DIG Phase Output.
    value: 10
  - name: '1011'
    description: Demodulator Hard Decision.
    value: 11
  - name: '1100'
    description: Demodulator Soft Decision.
    value: 12
  - name: '1101'
    description: Demodulator Data Output.
    value: 13
  - name: '1110'
    description: Demodulator CFO Phase Output.
    value: 14
enum/DMA_TIMED_OUT:
  bit_size: 1
  variants:
  - name: '0'
    description: A DMA timeout has not occurred.
    value: 0
  - name: '1'
    description: A DMA timeout has occurred in Single Request Mode since the last time this bit was cleared.
    value: 1
enum/DTEST_EN:
  bit_size: 1
  variants:
  - name: '0'
    description: Disables DTEST. The DTEST pins assume their mission function.
    value: 0
  - name: '1'
    description: Enables DTEST. The contents of the selected page (DTEST_PAGE) will appear on the DTEST output pins.
    value: 1
enum/FAD_EN:
  bit_size: 1
  variants:
  - name: '0'
    description: Fast Antenna Diversity disabled.
    value: 0
  - name: '1'
    description: Fast Antenna Diversity enabled for 802.15.4.
    value: 1
enum/PB_PROTECT:
  bit_size: 1
  variants:
  - name: '0'
    description: Incoming received packets overwrite Packet Buffer RX contents (default).
    value: 0
  - name: '1'
    description: Incoming received packets are blocked from overwriting Packet Buffer RX contents.
    value: 1
enum/PLL_SEQ_STATE:
  bit_size: 4
  variants:
  - name: '0'
    description: PLL OFF.
    value: 0
  - name: '2'
    description: CTUNE.
    value: 2
  - name: '3'
    description: CTUNE_SETTLE.
    value: 3
  - name: '6'
    description: HPMCAL1.
    value: 6
  - name: '8'
    description: HPMCAL1_SETTLE.
    value: 8
  - name: '10'
    description: HPMCAL2.
    value: 10
  - name: '12'
    description: HPMCAL2_SETTLE.
    value: 12
  - name: '15'
    description: PLLREADY.
    value: 15
enum/PROTOCOL:
  bit_size: 4
  variants:
  - name: '0000'
    description: BLE.
    value: 0
  - name: '0001'
    description: BLE in MBAN.
    value: 1
  - name: '0010'
    description: BLE overlap MBAN.
    value: 2
  - name: '0011'
    description: ANT.
    value: 3
  - name: '0100'
    description: Zigbee.
    value: 4
  - name: '0101'
    description: 802.15.4j.
    value: 5
  - name: '0110'
    description: 128 Channel FSK.
    value: 6
  - name: '0111'
    description: 128 Channel GFSK.
    value: 7
  - name: '1000'
    description: Generic FSK.
    value: 8
  - name: '1001'
    description: MSK.
    value: 9
enum/RADIO0_IRQ_SEL:
  bit_size: 3
  variants:
  - name: '000'
    description: 'Assign Radio #0 Interrupt to BLE.'
    value: 0
  - name: '001'
    description: 'Assign Radio #0 Interrupt to 802.15.4.'
    value: 1
  - name: '010'
    description: 'Assign Radio #0 Interrupt to ANT.'
    value: 2
  - name: '011'
    description: 'Assign Radio #0 Interrupt to GENERIC_FSK.'
    value: 3
  - name: '100'
    description: 'Radio #0 Interrupt unassigned.'
    value: 4
  - name: '101'
    description: 'Radio #0 Interrupt unassigned.'
    value: 5
  - name: '110'
    description: 'Radio #0 Interrupt unassigned.'
    value: 6
  - name: '111'
    description: 'Radio #0 Interrupt unassigned.'
    value: 7
enum/RADIO1_IRQ_SEL:
  bit_size: 3
  variants:
  - name: '000'
    description: 'Assign Radio #1 Interrupt to BLE.'
    value: 0
  - name: '001'
    description: 'Assign Radio #1 Interrupt to 802.15.4.'
    value: 1
  - name: '010'
    description: 'Assign Radio #1 Interrupt to ANT.'
    value: 2
  - name: '011'
    description: 'Assign Radio #1 Interrupt to GENERIC_FSK.'
    value: 3
  - name: '100'
    description: 'Radio #1 Interrupt unassigned.'
    value: 4
  - name: '101'
    description: 'Radio #1 Interrupt unassigned.'
    value: 5
  - name: '110'
    description: 'Radio #1 Interrupt unassigned.'
    value: 6
  - name: '111'
    description: 'Radio #1 Interrupt unassigned.'
    value: 7
enum/RAM0_CE_ON_OVRD_EN:
  bit_size: 1
  variants:
  - name: '0'
    description: Normal operation.
    value: 0
  - name: '1'
    description: Use the state of RAM0_CE_ON_OVRD to override the RAM0 CE.
    value: 1
enum/RAM0_CLK_ON_OVRD_EN:
  bit_size: 1
  variants:
  - name: '0'
    description: Normal operation.
    value: 0
  - name: '1'
    description: Use the state of RAM0_CLK_ON_OVRD to override the RAM0 Clock Gate Enable.
    value: 1
enum/RAM1_CE_ON_OVRD_EN:
  bit_size: 1
  variants:
  - name: '0'
    description: Normal operation.
    value: 0
  - name: '1'
    description: Use the state of RAM1_CE_ON_OVRD to override the RAM1 CE.
    value: 1
enum/RAM1_CLK_ON_OVRD_EN:
  bit_size: 1
  variants:
  - name: '0'
    description: Normal operation.
    value: 0
  - name: '1'
    description: Use the state of RAM1_CLK_ON_OVRD to override the RAM1 Clock Gate Enable.
    value: 1
enum/REF_CLK_FREQ:
  bit_size: 2
  variants:
  - name: '00'
    description: 32 MHz.
    value: 0
  - name: '01'
    description: 26 MHz.
    value: 1
enum/RF_NOT_ALLOWED_ASSERTED:
  bit_size: 1
  variants:
  - name: '0'
    description: Assertion on RF_NOT_ALLOWED has not occurred.
    value: 0
  - name: '1'
    description: Assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared.
    value: 1
enum/RF_NOT_ALLOWED_NO_RX:
  bit_size: 1
  variants:
  - name: '0'
    description: Assertion on RF_NOT_ALLOWED has no effect on RX.
    value: 0
  - name: '1'
    description: Assertion on RF_NOT_ALLOWED can abort RX.
    value: 1
enum/RF_NOT_ALLOWED_NO_TX:
  bit_size: 1
  variants:
  - name: '0'
    description: Assertion on RF_NOT_ALLOWED has no effect on TX.
    value: 0
  - name: '1'
    description: Assertion on RF_NOT_ALLOWED can abort TX.
    value: 1
enum/RF_NOT_ALLOWED_RX_ABORT:
  bit_size: 1
  variants:
  - name: '0'
    description: A RX abort due to assertion on RF_NOT_ALLOWED has not occurred.
    value: 0
  - name: '1'
    description: A RX abort due to assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared.
    value: 1
enum/RF_NOT_ALLOWED_TX_ABORT:
  bit_size: 1
  variants:
  - name: '0'
    description: A TX abort due to assertion on RF_NOT_ALLOWED has not occurred.
    value: 0
  - name: '1'
    description: A TX abort due to assertion on RF_NOT_ALLOWED has occurred since the last time this bit was cleared.
    value: 1
enum/SINGLE_REQ_MODE:
  bit_size: 1
  variants:
  - name: '0'
    description: Disable Single Request Mode. The transceiver will assert ipd_req_radio_rx whenever it has a new sample ready for transfer.
    value: 0
  - name: '1'
    description: Enable Single Request Mode. A single initial request by the transceiver will transfer the entire DMA block of data.
    value: 1
enum/TSM_GPIO_OVLAY:
  bit_size: 2
  variants:
  - name: '00'
    description: there is no overlay, and the DTEST Page Table dictates the node that appears on each DTEST pin.
    value: 0
  - name: '01'
    description: the register GPIO0_OVLAY_PIN[3:0] selects the DTEST pin on which GPIO0_TRIG_EN will appear.
    value: 1
enum/TSM_IRQ0:
  bit_size: 1
  variants:
  - name: '0'
    description: 'TSM Interrupt #0 is not asserted.'
    value: 0
  - name: '1'
    description: 'TSM Interrupt #0 is asserted. Write ''1'' to this bit to clear it.'
    value: 1
enum/TSM_IRQ1:
  bit_size: 1
  variants:
  - name: '0'
    description: 'TSM Interrupt #1 is not asserted.'
    value: 0
  - name: '1'
    description: 'TSM Interrupt #1 is asserted. Write ''1'' to this bit to clear it.'
    value: 1
enum/XCVR_BUSY:
  bit_size: 1
  variants:
  - name: '0'
    description: RF Channel in available (TSM is idle).
    value: 0
  - name: '1'
    description: RF Channel in use (TSM is busy).
    value: 1
enum/XCVR_RAM_ALLOW:
  bit_size: 1
  variants:
  - name: '0'
    description: Protocol Engines, and associated IPS busses, have exclusive access to Packet RAM (mission mode).
    value: 0
  - name: '1'
    description: Transceiver-space access to Packet RAM, including Packet RAM debug mode, are allowed.
    value: 1
enum/XTAL_READY:
  bit_size: 1
  variants:
  - name: '0'
    description: Indicates that the RF Oscillator is disabled or has not completed its warmup.
    value: 0
  - name: '1'
    description: Indicates that the RF Oscillator has completed its warmup count and is ready for use.
    value: 1