diff --git a/data/chips/STM32H7A3AG.json b/data/chips/STM32H7A3AG.json index ce88c9a..1e8b23e 100644 --- a/data/chips/STM32H7A3AG.json +++ b/data/chips/STM32H7A3AG.json @@ -3936,6 +3936,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7A3AI.json b/data/chips/STM32H7A3AI.json index 0ed0e56..5e52e9c 100644 --- a/data/chips/STM32H7A3AI.json +++ b/data/chips/STM32H7A3AI.json @@ -3947,6 +3947,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7A3IG.json b/data/chips/STM32H7A3IG.json index db7869c..0efcae4 100644 --- a/data/chips/STM32H7A3IG.json +++ b/data/chips/STM32H7A3IG.json @@ -4238,6 +4238,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7A3II.json b/data/chips/STM32H7A3II.json index 83d5510..36659cd 100644 --- a/data/chips/STM32H7A3II.json +++ b/data/chips/STM32H7A3II.json @@ -4249,6 +4249,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7A3LG.json b/data/chips/STM32H7A3LG.json index 70296c4..f291c4c 100644 --- a/data/chips/STM32H7A3LG.json +++ b/data/chips/STM32H7A3LG.json @@ -4345,6 +4345,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7A3LI.json b/data/chips/STM32H7A3LI.json index 72aaf38..e51034c 100644 --- a/data/chips/STM32H7A3LI.json +++ b/data/chips/STM32H7A3LI.json @@ -4362,6 +4362,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7A3NG.json b/data/chips/STM32H7A3NG.json index 7b002a8..6258ebb 100644 --- a/data/chips/STM32H7A3NG.json +++ b/data/chips/STM32H7A3NG.json @@ -4307,6 +4307,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7A3NI.json b/data/chips/STM32H7A3NI.json index 6498b12..e2ba26d 100644 --- a/data/chips/STM32H7A3NI.json +++ b/data/chips/STM32H7A3NI.json @@ -4318,6 +4318,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7A3QI.json b/data/chips/STM32H7A3QI.json index 5d1de09..142c907 100644 --- a/data/chips/STM32H7A3QI.json +++ b/data/chips/STM32H7A3QI.json @@ -3577,6 +3577,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7A3RG.json b/data/chips/STM32H7A3RG.json index 6394ae3..6cac3bf 100644 --- a/data/chips/STM32H7A3RG.json +++ b/data/chips/STM32H7A3RG.json @@ -2714,6 +2714,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7A3RI.json b/data/chips/STM32H7A3RI.json index a78ec39..729446c 100644 --- a/data/chips/STM32H7A3RI.json +++ b/data/chips/STM32H7A3RI.json @@ -2725,6 +2725,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7A3VG.json b/data/chips/STM32H7A3VG.json index fc76022..ceaaffa 100644 --- a/data/chips/STM32H7A3VG.json +++ b/data/chips/STM32H7A3VG.json @@ -3460,6 +3460,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7A3VI.json b/data/chips/STM32H7A3VI.json index 54093c4..45d907c 100644 --- a/data/chips/STM32H7A3VI.json +++ b/data/chips/STM32H7A3VI.json @@ -3471,6 +3471,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7A3ZG.json b/data/chips/STM32H7A3ZG.json index c78c45d..b37249d 100644 --- a/data/chips/STM32H7A3ZG.json +++ b/data/chips/STM32H7A3ZG.json @@ -3776,6 +3776,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7A3ZI.json b/data/chips/STM32H7A3ZI.json index eceec1f..7516ef0 100644 --- a/data/chips/STM32H7A3ZI.json +++ b/data/chips/STM32H7A3ZI.json @@ -3787,6 +3787,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B0AB.json b/data/chips/STM32H7B0AB.json index 0c6a485..39394b8 100644 --- a/data/chips/STM32H7B0AB.json +++ b/data/chips/STM32H7B0AB.json @@ -4015,6 +4015,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B0IB.json b/data/chips/STM32H7B0IB.json index ccb353b..0a653a9 100644 --- a/data/chips/STM32H7B0IB.json +++ b/data/chips/STM32H7B0IB.json @@ -4274,6 +4274,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B0RB.json b/data/chips/STM32H7B0RB.json index ba3fbdf..5664dad 100644 --- a/data/chips/STM32H7B0RB.json +++ b/data/chips/STM32H7B0RB.json @@ -2793,6 +2793,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B0VB.json b/data/chips/STM32H7B0VB.json index 25cc71c..19cbcc7 100644 --- a/data/chips/STM32H7B0VB.json +++ b/data/chips/STM32H7B0VB.json @@ -3527,6 +3527,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B0ZB.json b/data/chips/STM32H7B0ZB.json index 3e7cd62..4a52927 100644 --- a/data/chips/STM32H7B0ZB.json +++ b/data/chips/STM32H7B0ZB.json @@ -3851,6 +3851,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B3AI.json b/data/chips/STM32H7B3AI.json index bb8f10b..b033957 100644 --- a/data/chips/STM32H7B3AI.json +++ b/data/chips/STM32H7B3AI.json @@ -4032,6 +4032,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B3II.json b/data/chips/STM32H7B3II.json index 42ff363..b292ed6 100644 --- a/data/chips/STM32H7B3II.json +++ b/data/chips/STM32H7B3II.json @@ -4334,6 +4334,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B3LI.json b/data/chips/STM32H7B3LI.json index 4a970a4..a32d60e 100644 --- a/data/chips/STM32H7B3LI.json +++ b/data/chips/STM32H7B3LI.json @@ -4447,6 +4447,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B3NI.json b/data/chips/STM32H7B3NI.json index 76a7336..f59970a 100644 --- a/data/chips/STM32H7B3NI.json +++ b/data/chips/STM32H7B3NI.json @@ -4403,6 +4403,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B3QI.json b/data/chips/STM32H7B3QI.json index 952c2be..f5cb10a 100644 --- a/data/chips/STM32H7B3QI.json +++ b/data/chips/STM32H7B3QI.json @@ -3662,6 +3662,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B3RI.json b/data/chips/STM32H7B3RI.json index ee94eed..226b6d9 100644 --- a/data/chips/STM32H7B3RI.json +++ b/data/chips/STM32H7B3RI.json @@ -2810,6 +2810,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B3VI.json b/data/chips/STM32H7B3VI.json index 89cb784..67218db 100644 --- a/data/chips/STM32H7B3VI.json +++ b/data/chips/STM32H7B3VI.json @@ -3556,6 +3556,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B3ZI.json b/data/chips/STM32H7B3ZI.json index 7a24766..af227a5 100644 --- a/data/chips/STM32H7B3ZI.json +++ b/data/chips/STM32H7B3ZI.json @@ -3872,6 +3872,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/registers/rcc_h7ab.json b/data/registers/rcc_h7ab.json index 782658c..087334f 100644 --- a/data/registers/rcc_h7ab.json +++ b/data/registers/rcc_h7ab.json @@ -732,8 +732,8 @@ "bit_size": 1 }, { - "name": "QUADSPIEN", - "description": "QUADSPI and QUADSPI Delay Clock Enable", + "name": "OCTOSPI1EN", + "description": "OCTOSPI1 and OCTOSPI1 Delay Clock Enable", "bit_offset": 14, "bit_size": 1 }, @@ -827,8 +827,8 @@ "bit_size": 1 }, { - "name": "QUADSPILPEN", - "description": "QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode", + "name": "OCTOSPI1LPEN", + "description": "OCTOSPI1 and OCTOSPI1 Delay Clock Enable During CSleep Mode", "bit_offset": 14, "bit_size": 1 }, @@ -916,8 +916,8 @@ "bit_size": 1 }, { - "name": "QUADSPIRST", - "description": "QUADSPI and QUADSPI delay block reset", + "name": "OCTOSPI1RST", + "description": "OCTOSPI1 and OCTOSPI1 delay block reset", "bit_offset": 14, "bit_size": 1 },